Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt

Amlogic Meson AXG DWC PCIE SoC controller

Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and
inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pcie.txt.

Additional properties are described here:

Required properties:
- compatible:
	should contain :
	- "amlogic,axg-pcie" for AXG SoC Family
	- "amlogic,g12a-pcie" for G12A SoC Family
	to identify the core.
- reg:
	should contain the configuration address space.
- reg-names: Must be
	- "elbi"	External local bus interface registers
	- "cfg"		Meson specific registers
	- "phy"		Meson PCIE PHY registers for AXG SoC Family
	- "config"	PCIe configuration space
- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Must include the following entries:
	- "pclk"       PCIe GEN 100M PLL clock
	- "port"       PCIe_x(A or B) RC clock gate
	- "general"    PCIe Phy clock
	- "mipi"       PCIe_x(A or B) 100M ref clock gate for AXG SoC Family
- resets: phandle to the reset lines.
- reset-names: must contain "phy" "port" and "apb"
       - "phy"         Share PHY reset for AXG SoC Family
       - "port"        Port A or B reset
       - "apb"         Share APB reset
- phys: should contain a phandle to the shared phy for G12A SoC Family
- device_type:
	should be "pci". As specified in designware-pcie.txt


Example configuration:

	pcie: pcie@f9800000 {
			compatible = "amlogic,axg-pcie", "snps,dw-pcie";
			reg = <0x0 0xf9800000 0x0 0x400000
					0x0 0xff646000 0x0 0x2000
					0x0 0xff644000 0x0 0x2000
					0x0 0xf9f00000 0x0 0x100000>;
			reg-names = "elbi", "cfg", "phy", "config";
			reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
			interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
			bus-range = <0x0 0xff>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;

			clocks = <&clkc CLKID_USB
					&clkc CLKID_MIPI_ENABLE
					&clkc CLKID_PCIE_A
					&clkc CLKID_PCIE_CML_EN0>;
			clock-names = "general",
					"mipi",
					"pclk",
					"port";
			resets = <&reset RESET_PCIE_PHY>,
				<&reset RESET_PCIE_A>,
				<&reset RESET_PCIE_APB>;
			reset-names = "phy",
					"port",
					"apb";
	};