| // SPDX-License-Identifier: GPL-2.0+ OR MIT |
| // |
| // Copyright (C) 2015 Freescale Semiconductor, Inc. |
| |
| /dts-v1/; |
| |
| #include "imx7d.dtsi" |
| |
| / { |
| model = "Freescale i.MX7 SabreSD Board"; |
| compatible = "fsl,imx7d-sdb", "fsl,imx7d"; |
| |
| chosen { |
| stdout-path = &uart1; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x80000000 0x80000000>; |
| }; |
| |
| gpio-keys { |
| compatible = "gpio-keys"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpio_keys>; |
| |
| volume-up { |
| label = "Volume Up"; |
| gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; |
| linux,code = <KEY_VOLUMEUP>; |
| wakeup-source; |
| }; |
| |
| volume-down { |
| label = "Volume Down"; |
| gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; |
| linux,code = <KEY_VOLUMEDOWN>; |
| wakeup-source; |
| }; |
| }; |
| |
| spi4 { |
| compatible = "spi-gpio"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi4>; |
| gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; |
| gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; |
| cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; |
| num-chipselects = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| extended_io: gpio-expander@0 { |
| compatible = "fairchild,74hc595"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0>; |
| registers-number = <1>; |
| spi-max-frequency = <100000>; |
| }; |
| }; |
| |
| reg_usb_otg1_vbus: regulator-usb-otg1-vbus { |
| compatible = "regulator-fixed"; |
| regulator-name = "usb_otg1_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_usb_otg2_vbus: regulator-usb-otg2-vbus { |
| compatible = "regulator-fixed"; |
| regulator-name = "usb_otg2_vbus"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_vref_1v8: regulator-vref-1v8 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vref-1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| }; |
| |
| reg_brcm: regulator-brcm { |
| compatible = "regulator-fixed"; |
| gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| regulator-name = "brcm_reg"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_brcm_reg>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| startup-delay-us = <200000>; |
| }; |
| |
| reg_lcd_3v3: regulator-lcd-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "lcd-3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; |
| }; |
| |
| reg_can2_3v3: regulator-can2-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "can2-3v3"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan2_reg>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; |
| }; |
| |
| reg_fec2_3v3: regulator-fec2-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "fec2-3v3"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet2_reg>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; |
| }; |
| |
| backlight: backlight { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm1 0 5000000 0>; |
| brightness-levels = <0 4 8 16 32 64 128 255>; |
| default-brightness-level = <6>; |
| status = "okay"; |
| }; |
| |
| panel { |
| compatible = "innolux,at043tn24"; |
| backlight = <&backlight>; |
| power-supply = <®_lcd_3v3>; |
| |
| port { |
| panel_in: endpoint { |
| remote-endpoint = <&display_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| &adc1 { |
| vref-supply = <®_vref_1v8>; |
| status = "okay"; |
| }; |
| |
| &adc2 { |
| vref-supply = <®_vref_1v8>; |
| status = "okay"; |
| }; |
| |
| &cpu0 { |
| cpu-supply = <&sw1a_reg>; |
| }; |
| |
| &ecspi3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi3>; |
| cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| |
| tsc2046@0 { |
| compatible = "ti,tsc2046"; |
| reg = <0>; |
| spi-max-frequency = <1000000>; |
| pinctrl-names ="default"; |
| pinctrl-0 = <&pinctrl_tsc2046_pendown>; |
| interrupt-parent = <&gpio2>; |
| interrupts = <29 0>; |
| pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; |
| ti,x-min = /bits/ 16 <0>; |
| ti,x-max = /bits/ 16 <0>; |
| ti,y-min = /bits/ 16 <0>; |
| ti,y-max = /bits/ 16 <0>; |
| ti,pressure-max = /bits/ 16 <0>; |
| ti,x-plate-ohms = /bits/ 16 <400>; |
| wakeup-source; |
| }; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet1>; |
| assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, |
| <&clks IMX7D_ENET1_TIME_ROOT_CLK>; |
| assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; |
| assigned-clock-rates = <0>, <100000000>; |
| phy-mode = "rgmii"; |
| phy-handle = <ðphy0>; |
| fsl,magic-packet; |
| phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| reg = <0>; |
| }; |
| |
| ethphy1: ethernet-phy@1 { |
| reg = <1>; |
| }; |
| }; |
| }; |
| |
| &fec2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet2>; |
| assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, |
| <&clks IMX7D_ENET2_TIME_ROOT_CLK>; |
| assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; |
| assigned-clock-rates = <0>, <100000000>; |
| phy-mode = "rgmii"; |
| phy-handle = <ðphy1>; |
| phy-supply = <®_fec2_3v3>; |
| fsl,magic-packet; |
| status = "okay"; |
| }; |
| |
| &flexcan2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan2>; |
| xceiver-supply = <®_can2_3v3>; |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| |
| pmic: pfuze3000@8 { |
| compatible = "fsl,pfuze3000"; |
| reg = <0x08>; |
| |
| regulators { |
| sw1a_reg: sw1a { |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1475000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| /* use sw1c_reg to align with pfuze100/pfuze200 */ |
| sw1c_reg: sw1b { |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1475000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| sw2_reg: sw2 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw3a_reg: sw3 { |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1650000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| swbst_reg: swbst { |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5150000>; |
| }; |
| |
| snvs_reg: vsnvs { |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vref_reg: vrefddr { |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vgen1_reg: vldo1 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen2_reg: vldo2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| }; |
| |
| vgen3_reg: vccsd { |
| regulator-min-microvolt = <2850000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen4_reg: v33 { |
| regulator-min-microvolt = <2850000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen5_reg: vldo3 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen6_reg: vldo4 { |
| regulator-min-microvolt = <2800000>; |
| regulator-max-microvolt = <2800000>; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| status = "okay"; |
| |
| mpl3115@60 { |
| compatible = "fsl,mpl3115"; |
| reg = <0x60>; |
| }; |
| }; |
| |
| &i2c3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| status = "okay"; |
| }; |
| |
| &i2c4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c4>; |
| status = "okay"; |
| |
| codec: wm8960@1a { |
| compatible = "wlf,wm8960"; |
| reg = <0x1a>; |
| clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; |
| clock-names = "mclk"; |
| wlf,shared-lrclk; |
| }; |
| }; |
| |
| &lcdif { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lcdif>; |
| status = "okay"; |
| |
| port { |
| display_out: endpoint { |
| remote-endpoint = <&panel_in>; |
| }; |
| }; |
| }; |
| |
| &pcie { |
| reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| ®_1p0d { |
| vin-supply = <&sw2_reg>; |
| }; |
| |
| ®_1p2 { |
| vin-supply = <&sw2_reg>; |
| }; |
| |
| &snvs_pwrkey { |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; |
| assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; |
| status = "okay"; |
| }; |
| |
| &uart6 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart6>; |
| assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; |
| assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; |
| uart-has-rtscts; |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| vbus-supply = <®_usb_otg1_vbus>; |
| status = "okay"; |
| }; |
| |
| &usbotg2 { |
| vbus-supply = <®_usb_otg2_vbus>; |
| dr_mode = "host"; |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; |
| wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; |
| wakeup-source; |
| keep-power-in-suspend; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>; |
| wakeup-source; |
| keep-power-in-suspend; |
| non-removable; |
| vmmc-supply = <®_brcm>; |
| fsl,tuning-step = <2>; |
| status = "okay"; |
| }; |
| |
| &usdhc3 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; |
| assigned-clock-rates = <400000000>; |
| bus-width = <8>; |
| fsl,tuning-step = <2>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog>; |
| |
| imx7d-sdb { |
| pinctrl_brcm_reg: brcmreggrp { |
| fsl,pins = < |
| MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 |
| >; |
| }; |
| |
| pinctrl_ecspi3: ecspi3grp { |
| fsl,pins = < |
| MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 |
| MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 |
| MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 |
| MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 |
| >; |
| }; |
| |
| pinctrl_enet1: enet1grp { |
| fsl,pins = < |
| MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 |
| MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 |
| MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 |
| MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 |
| MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 |
| MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 |
| MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 |
| MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 |
| MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 |
| MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 |
| MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 |
| MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 |
| MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 |
| MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 |
| >; |
| }; |
| |
| pinctrl_enet2: enet2grp { |
| fsl,pins = < |
| MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 |
| MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 |
| MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 |
| MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 |
| MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 |
| MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 |
| MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 |
| MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 |
| MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 |
| MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 |
| MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 |
| MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 |
| >; |
| }; |
| |
| pinctrl_enet2_reg: enet2reggrp { |
| fsl,pins = < |
| MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 |
| >; |
| }; |
| |
| pinctrl_flexcan2: flexcan2grp { |
| fsl,pins = < |
| MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 |
| MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 |
| >; |
| }; |
| |
| pinctrl_flexcan2_reg: flexcan2reggrp { |
| fsl,pins = < |
| MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ |
| >; |
| }; |
| |
| pinctrl_gpio_keys: gpio_keysgrp { |
| fsl,pins = < |
| MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 |
| MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 |
| >; |
| }; |
| |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f |
| MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f |
| MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f |
| >; |
| }; |
| |
| pinctrl_i2c3: i2c3grp { |
| fsl,pins = < |
| MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f |
| MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f |
| >; |
| }; |
| |
| pinctrl_i2c4: i2c4grp { |
| fsl,pins = < |
| MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f |
| MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f |
| >; |
| }; |
| |
| pinctrl_lcdif: lcdifgrp { |
| fsl,pins = < |
| MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 |
| MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 |
| MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 |
| MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 |
| MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 |
| MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 |
| MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 |
| MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 |
| MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 |
| MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 |
| MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 |
| MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 |
| MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 |
| MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 |
| MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 |
| MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 |
| MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 |
| MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 |
| MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 |
| MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 |
| MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 |
| MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 |
| MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 |
| MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 |
| MX7D_PAD_LCD_CLK__LCD_CLK 0x79 |
| MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 |
| MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 |
| MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 |
| MX7D_PAD_LCD_RESET__LCD_RESET 0x79 |
| >; |
| }; |
| |
| pinctrl_spi4: spi4grp { |
| fsl,pins = < |
| MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 |
| MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 |
| MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 |
| >; |
| }; |
| |
| pinctrl_tsc2046_pendown: tsc2046_pendown { |
| fsl,pins = < |
| MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 |
| MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 |
| >; |
| }; |
| |
| pinctrl_uart5: uart5grp { |
| fsl,pins = < |
| MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 |
| MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 |
| MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 |
| MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 |
| >; |
| }; |
| |
| pinctrl_uart6: uart6grp { |
| fsl,pins = < |
| MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 |
| MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 |
| MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 |
| MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX7D_PAD_SD1_CMD__SD1_CMD 0x59 |
| MX7D_PAD_SD1_CLK__SD1_CLK 0x19 |
| MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 |
| MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 |
| MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 |
| MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 |
| MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ |
| MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ |
| MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX7D_PAD_SD2_CMD__SD2_CMD 0x59 |
| MX7D_PAD_SD2_CLK__SD2_CLK 0x19 |
| MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 |
| MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 |
| MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 |
| MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { |
| fsl,pins = < |
| MX7D_PAD_SD2_CMD__SD2_CMD 0x5a |
| MX7D_PAD_SD2_CLK__SD2_CLK 0x1a |
| MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a |
| MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a |
| MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a |
| MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { |
| fsl,pins = < |
| MX7D_PAD_SD2_CMD__SD2_CMD 0x5b |
| MX7D_PAD_SD2_CLK__SD2_CLK 0x1b |
| MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b |
| MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b |
| MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b |
| MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b |
| >; |
| }; |
| |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x59 |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x19 |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 |
| MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 |
| >; |
| }; |
| |
| pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x5a |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x1a |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a |
| MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a |
| >; |
| }; |
| |
| pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x5b |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x1b |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b |
| MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b |
| >; |
| }; |
| }; |
| }; |
| |
| &pwm1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm1>; |
| status = "okay"; |
| }; |
| |
| &iomuxc_lpsr { |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 |
| >; |
| }; |
| |
| pinctrl_pwm1: pwm1grp { |
| fsl,pins = < |
| MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 |
| >; |
| }; |
| |
| pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { |
| fsl,pins = < |
| MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 |
| >; |
| }; |
| }; |
