| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright (C) 2016 Freescale Semiconductor, Inc. |
| * Copyright 2017-2018 NXP |
| * Dong Aisheng <aisheng.dong@nxp.com> |
| */ |
| |
| #include <dt-bindings/clock/imx8-clock.h> |
| #include <dt-bindings/firmware/imx/rsrc.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/input/input.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/pinctrl/pads-imx8qxp.h> |
| |
| / { |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| gpio0 = &lsio_gpio0; |
| gpio1 = &lsio_gpio1; |
| gpio2 = &lsio_gpio2; |
| gpio3 = &lsio_gpio3; |
| gpio4 = &lsio_gpio4; |
| gpio5 = &lsio_gpio5; |
| gpio6 = &lsio_gpio6; |
| gpio7 = &lsio_gpio7; |
| mmc0 = &usdhc1; |
| mmc1 = &usdhc2; |
| mmc2 = &usdhc3; |
| mu1 = &lsio_mu1; |
| serial0 = &adma_lpuart0; |
| serial1 = &adma_lpuart1; |
| serial2 = &adma_lpuart2; |
| serial3 = &adma_lpuart3; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| /* We have 1 clusters with 4 Cortex-A35 cores */ |
| A35_0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a35"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| next-level-cache = <&A35_L2>; |
| clocks = <&clk IMX_A35_CLK>; |
| operating-points-v2 = <&a35_opp_table>; |
| #cooling-cells = <2>; |
| }; |
| |
| A35_1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a35"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| next-level-cache = <&A35_L2>; |
| clocks = <&clk IMX_A35_CLK>; |
| operating-points-v2 = <&a35_opp_table>; |
| #cooling-cells = <2>; |
| }; |
| |
| A35_2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a35"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| next-level-cache = <&A35_L2>; |
| clocks = <&clk IMX_A35_CLK>; |
| operating-points-v2 = <&a35_opp_table>; |
| #cooling-cells = <2>; |
| }; |
| |
| A35_3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a35"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| next-level-cache = <&A35_L2>; |
| clocks = <&clk IMX_A35_CLK>; |
| operating-points-v2 = <&a35_opp_table>; |
| #cooling-cells = <2>; |
| }; |
| |
| A35_L2: l2-cache0 { |
| compatible = "cache"; |
| }; |
| }; |
| |
| a35_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp-900000000 { |
| opp-hz = /bits/ 64 <900000000>; |
| opp-microvolt = <1000000>; |
| clock-latency-ns = <150000>; |
| }; |
| |
| opp-1200000000 { |
| opp-hz = /bits/ 64 <1200000000>; |
| opp-microvolt = <1100000>; |
| clock-latency-ns = <150000>; |
| opp-suspend; |
| }; |
| }; |
| |
| gic: interrupt-controller@51a00000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ |
| <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| dsp_reserved: dsp@92400000 { |
| reg = <0 0x92400000 0 0x2000000>; |
| no-map; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| scu { |
| compatible = "fsl,imx-scu"; |
| mbox-names = "tx0", "tx1", "tx2", "tx3", |
| "rx0", "rx1", "rx2", "rx3", |
| "gip3"; |
| mboxes = <&lsio_mu1 0 0 |
| &lsio_mu1 0 1 |
| &lsio_mu1 0 2 |
| &lsio_mu1 0 3 |
| &lsio_mu1 1 0 |
| &lsio_mu1 1 1 |
| &lsio_mu1 1 2 |
| &lsio_mu1 1 3 |
| &lsio_mu1 3 3>; |
| |
| clk: clock-controller { |
| compatible = "fsl,imx8qxp-clk"; |
| #clock-cells = <1>; |
| clocks = <&xtal32k &xtal24m>; |
| clock-names = "xtal_32KHz", "xtal_24Mhz"; |
| }; |
| |
| iomuxc: pinctrl { |
| compatible = "fsl,imx8qxp-iomuxc"; |
| }; |
| |
| ocotp: imx8qx-ocotp { |
| compatible = "fsl,imx8qxp-scu-ocotp"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| |
| pd: imx8qx-pd { |
| compatible = "fsl,imx8qxp-scu-pd"; |
| #power-domain-cells = <1>; |
| }; |
| |
| scu_key: scu-key { |
| compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; |
| linux,keycodes = <KEY_POWER>; |
| status = "disabled"; |
| }; |
| |
| rtc: rtc { |
| compatible = "fsl,imx8qxp-sc-rtc"; |
| }; |
| |
| watchdog { |
| compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; |
| timeout-sec = <60>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ |
| }; |
| |
| xtal32k: clock-xtal32k { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| clock-output-names = "xtal_32KHz"; |
| }; |
| |
| xtal24m: clock-xtal24m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <24000000>; |
| clock-output-names = "xtal_24MHz"; |
| }; |
| |
| adma_subsys: bus@59000000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x59000000 0x0 0x59000000 0x2000000>; |
| |
| adma_lpcg: clock-controller@59000000 { |
| compatible = "fsl,imx8qxp-lpcg-adma"; |
| reg = <0x59000000 0x2000000>; |
| #clock-cells = <1>; |
| }; |
| |
| adma_dsp: dsp@596e8000 { |
| compatible = "fsl,imx8qxp-dsp"; |
| reg = <0x596e8000 0x88000>; |
| clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, |
| <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, |
| <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; |
| clock-names = "ipg", "ocram", "core"; |
| power-domains = <&pd IMX_SC_R_MU_13A>, |
| <&pd IMX_SC_R_MU_13B>, |
| <&pd IMX_SC_R_DSP>, |
| <&pd IMX_SC_R_DSP_RAM>; |
| mbox-names = "txdb0", "txdb1", |
| "rxdb0", "rxdb1"; |
| mboxes = <&lsio_mu13 2 0>, |
| <&lsio_mu13 2 1>, |
| <&lsio_mu13 3 0>, |
| <&lsio_mu13 3 1>; |
| memory-region = <&dsp_reserved>; |
| status = "disabled"; |
| }; |
| |
| adma_lpuart0: serial@5a060000 { |
| compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; |
| reg = <0x5a060000 0x1000>; |
| interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, |
| <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; |
| clock-names = "ipg", "baud"; |
| power-domains = <&pd IMX_SC_R_UART_0>; |
| status = "disabled"; |
| }; |
| |
| adma_lpuart1: serial@5a070000 { |
| compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; |
| reg = <0x5a070000 0x1000>; |
| interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, |
| <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; |
| clock-names = "ipg", "baud"; |
| power-domains = <&pd IMX_SC_R_UART_1>; |
| status = "disabled"; |
| }; |
| |
| adma_lpuart2: serial@5a080000 { |
| compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; |
| reg = <0x5a080000 0x1000>; |
| interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, |
| <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; |
| clock-names = "ipg", "baud"; |
| power-domains = <&pd IMX_SC_R_UART_2>; |
| status = "disabled"; |
| }; |
| |
| adma_lpuart3: serial@5a090000 { |
| compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; |
| reg = <0x5a090000 0x1000>; |
| interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, |
| <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; |
| clock-names = "ipg", "baud"; |
| power-domains = <&pd IMX_SC_R_UART_3>; |
| status = "disabled"; |
| }; |
| |
| adma_i2c0: i2c@5a800000 { |
| compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x5a800000 0x4000>; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; |
| assigned-clock-rates = <24000000>; |
| power-domains = <&pd IMX_SC_R_I2C_0>; |
| status = "disabled"; |
| }; |
| |
| adma_i2c1: i2c@5a810000 { |
| compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x5a810000 0x4000>; |
| interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; |
| assigned-clock-rates = <24000000>; |
| power-domains = <&pd IMX_SC_R_I2C_1>; |
| status = "disabled"; |
| }; |
| |
| adma_i2c2: i2c@5a820000 { |
| compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x5a820000 0x4000>; |
| interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; |
| assigned-clock-rates = <24000000>; |
| power-domains = <&pd IMX_SC_R_I2C_2>; |
| status = "disabled"; |
| }; |
| |
| adma_i2c3: i2c@5a830000 { |
| compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; |
| reg = <0x5a830000 0x4000>; |
| interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; |
| clock-names = "per"; |
| assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; |
| assigned-clock-rates = <24000000>; |
| power-domains = <&pd IMX_SC_R_I2C_3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| conn_subsys: bus@5b000000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; |
| |
| conn_lpcg: clock-controller@5b200000 { |
| compatible = "fsl,imx8qxp-lpcg-conn"; |
| reg = <0x5b200000 0xb0000>; |
| #clock-cells = <1>; |
| }; |
| |
| usdhc1: mmc@5b010000 { |
| compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x5b010000 0x10000>; |
| clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, |
| <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, |
| <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; |
| clock-names = "ipg", "per", "ahb"; |
| power-domains = <&pd IMX_SC_R_SDHC_0>; |
| status = "disabled"; |
| }; |
| |
| usdhc2: mmc@5b020000 { |
| compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x5b020000 0x10000>; |
| clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, |
| <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, |
| <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; |
| clock-names = "ipg", "per", "ahb"; |
| power-domains = <&pd IMX_SC_R_SDHC_1>; |
| fsl,tuning-start-tap = <20>; |
| fsl,tuning-step= <2>; |
| status = "disabled"; |
| }; |
| |
| usdhc3: mmc@5b030000 { |
| compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x5b030000 0x10000>; |
| clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, |
| <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, |
| <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; |
| clock-names = "ipg", "per", "ahb"; |
| power-domains = <&pd IMX_SC_R_SDHC_2>; |
| status = "disabled"; |
| }; |
| |
| fec1: ethernet@5b040000 { |
| compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; |
| reg = <0x5b040000 0x10000>; |
| interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, |
| <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, |
| <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, |
| <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; |
| clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; |
| fsl,num-tx-queues=<3>; |
| fsl,num-rx-queues=<3>; |
| power-domains = <&pd IMX_SC_R_ENET_0>; |
| status = "disabled"; |
| }; |
| |
| fec2: ethernet@5b050000 { |
| compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; |
| reg = <0x5b050000 0x10000>; |
| interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, |
| <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, |
| <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, |
| <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; |
| clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; |
| fsl,num-tx-queues=<3>; |
| fsl,num-rx-queues=<3>; |
| power-domains = <&pd IMX_SC_R_ENET_1>; |
| status = "disabled"; |
| }; |
| }; |
| |
| ddr_subsyss: bus@5c000000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; |
| |
| ddr-pmu@5c020000 { |
| compatible = "fsl,imx8-ddr-pmu"; |
| reg = <0x5c020000 0x10000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| lsio_subsys: bus@5d000000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; |
| |
| lsio_gpio0: gpio@5d080000 { |
| compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
| reg = <0x5d080000 0x10000>; |
| interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_0>; |
| }; |
| |
| lsio_gpio1: gpio@5d090000 { |
| compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
| reg = <0x5d090000 0x10000>; |
| interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_1>; |
| }; |
| |
| lsio_gpio2: gpio@5d0a0000 { |
| compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
| reg = <0x5d0a0000 0x10000>; |
| interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_2>; |
| }; |
| |
| lsio_gpio3: gpio@5d0b0000 { |
| compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
| reg = <0x5d0b0000 0x10000>; |
| interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_3>; |
| }; |
| |
| lsio_gpio4: gpio@5d0c0000 { |
| compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
| reg = <0x5d0c0000 0x10000>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_4>; |
| }; |
| |
| lsio_gpio5: gpio@5d0d0000 { |
| compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
| reg = <0x5d0d0000 0x10000>; |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_5>; |
| }; |
| |
| lsio_gpio6: gpio@5d0e0000 { |
| compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
| reg = <0x5d0e0000 0x10000>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_6>; |
| }; |
| |
| lsio_gpio7: gpio@5d0f0000 { |
| compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
| reg = <0x5d0f0000 0x10000>; |
| interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| power-domains = <&pd IMX_SC_R_GPIO_7>; |
| }; |
| |
| lsio_mu0: mailbox@5d1b0000 { |
| compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
| reg = <0x5d1b0000 0x10000>; |
| interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| lsio_mu1: mailbox@5d1c0000 { |
| compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
| reg = <0x5d1c0000 0x10000>; |
| interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| }; |
| |
| lsio_mu2: mailbox@5d1d0000 { |
| compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
| reg = <0x5d1d0000 0x10000>; |
| interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| lsio_mu3: mailbox@5d1e0000 { |
| compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
| reg = <0x5d1e0000 0x10000>; |
| interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| lsio_mu4: mailbox@5d1f0000 { |
| compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
| reg = <0x5d1f0000 0x10000>; |
| interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| lsio_mu13: mailbox@5d280000 { |
| compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
| reg = <0x5d280000 0x10000>; |
| interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <2>; |
| power-domains = <&pd IMX_SC_R_MU_13A>; |
| }; |
| |
| lsio_lpcg: clock-controller@5d400000 { |
| compatible = "fsl,imx8qxp-lpcg-lsio"; |
| reg = <0x5d400000 0x400000>; |
| #clock-cells = <1>; |
| }; |
| }; |
| }; |
