| /* |
| * Copyright 2021 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| */ |
| #ifndef _nbio_7_7_0_OFFSET_HEADER |
| #define _nbio_7_7_0_OFFSET_HEADER |
| |
| |
| |
| // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec |
| // base address: 0x0 |
| #define cfgNBCFG_SCRATCH_4 0x0078 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_RC_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_RC_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_RC_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_RC_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_RC_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_RC_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_RC_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_RC_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_RC_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_RC_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_RC_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_RC_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_RC_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT 0x001c |
| #define cfgBIF_CFG_DEV0_RC_SECONDARY_STATUS 0x001e |
| #define cfgBIF_CFG_DEV0_RC_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIF_CFG_DEV0_RC_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIF_CFG_DEV0_RC_PREF_BASE_UPPER 0x0028 |
| #define cfgBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIF_CFG_DEV0_RC_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR 0x0038 |
| #define cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL 0x003e |
| #define cfgBIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_RC_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST 0x0058 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_CAP 0x005a |
| #define cfgBIF_CFG_DEV0_RC_DEVICE_CAP 0x005c |
| #define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL 0x0060 |
| #define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS 0x0062 |
| #define cfgBIF_CFG_DEV0_RC_LINK_CAP 0x0064 |
| #define cfgBIF_CFG_DEV0_RC_LINK_CNTL 0x0068 |
| #define cfgBIF_CFG_DEV0_RC_LINK_STATUS 0x006a |
| #define cfgBIF_CFG_DEV0_RC_SLOT_CAP 0x006c |
| #define cfgBIF_CFG_DEV0_RC_SLOT_CNTL 0x0070 |
| #define cfgBIF_CFG_DEV0_RC_SLOT_STATUS 0x0072 |
| #define cfgBIF_CFG_DEV0_RC_ROOT_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_RC_ROOT_CAP 0x0076 |
| #define cfgBIF_CFG_DEV0_RC_ROOT_STATUS 0x0078 |
| #define cfgBIF_CFG_DEV0_RC_DEVICE_CAP2 0x007c |
| #define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2 0x0080 |
| #define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2 0x0082 |
| #define cfgBIF_CFG_DEV0_RC_LINK_CAP2 0x0084 |
| #define cfgBIF_CFG_DEV0_RC_LINK_CNTL2 0x0088 |
| #define cfgBIF_CFG_DEV0_RC_LINK_STATUS2 0x008a |
| #define cfgBIF_CFG_DEV0_RC_SLOT_CAP2 0x008c |
| #define cfgBIF_CFG_DEV0_RC_SLOT_CNTL2 0x0090 |
| #define cfgBIF_CFG_DEV0_RC_SLOT_STATUS2 0x0092 |
| #define cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA 0x00aa |
| #define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 0x00ae |
| #define cfgBIF_CFG_DEV0_RC_SSID_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_RC_SSID_CAP 0x00c4 |
| #define cfgBIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIF_CFG_DEV0_RC_MSI_MAP_CAP 0x00ca |
| #define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST 0x0400 |
| #define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP 0x0404 |
| #define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS 0x0408 |
| #define cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 |
| #define cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT 0x0414 |
| #define cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT 0x0418 |
| #define cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT 0x041c |
| #define cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 |
| #define cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 |
| #define cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 |
| #define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 |
| #define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 |
| #define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 |
| #define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 |
| #define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 |
| #define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 |
| #define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 |
| #define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 |
| #define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 |
| #define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 |
| #define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT 0x043a |
| #define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT 0x043b |
| #define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT 0x043c |
| #define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT 0x043d |
| #define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT 0x043e |
| #define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT 0x043f |
| #define cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST 0x0450 |
| #define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP 0x0454 |
| #define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS 0x0456 |
| #define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL 0x0458 |
| #define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS 0x045a |
| #define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL 0x045c |
| #define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS 0x045e |
| #define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL 0x0460 |
| #define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS 0x0462 |
| #define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL 0x0464 |
| #define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS 0x0466 |
| #define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL 0x0468 |
| #define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS 0x046a |
| #define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL 0x046c |
| #define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS 0x046e |
| #define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL 0x0470 |
| #define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS 0x0472 |
| #define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL 0x0474 |
| #define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS 0x0476 |
| #define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL 0x0478 |
| #define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS 0x047a |
| #define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL 0x047c |
| #define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS 0x047e |
| #define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL 0x0480 |
| #define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS 0x0482 |
| #define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL 0x0484 |
| #define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS 0x0486 |
| #define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL 0x0488 |
| #define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS 0x048a |
| #define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL 0x048c |
| #define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS 0x048e |
| #define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL 0x0490 |
| #define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS 0x0492 |
| #define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL 0x0494 |
| #define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS 0x0496 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV1_RC_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV1_RC_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV1_RC_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV1_RC_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV1_RC_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV1_RC_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV1_RC_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV1_RC_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV1_RC_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV1_RC_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV1_RC_HEADER 0x000e |
| #define cfgBIF_CFG_DEV1_RC_BIST 0x000f |
| #define cfgBIF_CFG_DEV1_RC_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV1_RC_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIF_CFG_DEV1_RC_IO_BASE_LIMIT 0x001c |
| #define cfgBIF_CFG_DEV1_RC_SECONDARY_STATUS 0x001e |
| #define cfgBIF_CFG_DEV1_RC_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIF_CFG_DEV1_RC_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIF_CFG_DEV1_RC_PREF_BASE_UPPER 0x0028 |
| #define cfgBIF_CFG_DEV1_RC_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIF_CFG_DEV1_RC_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV1_RC_ROM_BASE_ADDR 0x0038 |
| #define cfgBIF_CFG_DEV1_RC_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV1_RC_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL 0x003e |
| #define cfgBIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIF_CFG_DEV1_RC_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV1_RC_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV1_RC_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_CAP_LIST 0x0058 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_CAP 0x005a |
| #define cfgBIF_CFG_DEV1_RC_DEVICE_CAP 0x005c |
| #define cfgBIF_CFG_DEV1_RC_DEVICE_CNTL 0x0060 |
| #define cfgBIF_CFG_DEV1_RC_DEVICE_STATUS 0x0062 |
| #define cfgBIF_CFG_DEV1_RC_LINK_CAP 0x0064 |
| #define cfgBIF_CFG_DEV1_RC_LINK_CNTL 0x0068 |
| #define cfgBIF_CFG_DEV1_RC_LINK_STATUS 0x006a |
| #define cfgBIF_CFG_DEV1_RC_SLOT_CAP 0x006c |
| #define cfgBIF_CFG_DEV1_RC_SLOT_CNTL 0x0070 |
| #define cfgBIF_CFG_DEV1_RC_SLOT_STATUS 0x0072 |
| #define cfgBIF_CFG_DEV1_RC_ROOT_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV1_RC_ROOT_CAP 0x0076 |
| #define cfgBIF_CFG_DEV1_RC_ROOT_STATUS 0x0078 |
| #define cfgBIF_CFG_DEV1_RC_DEVICE_CAP2 0x007c |
| #define cfgBIF_CFG_DEV1_RC_DEVICE_CNTL2 0x0080 |
| #define cfgBIF_CFG_DEV1_RC_DEVICE_STATUS2 0x0082 |
| #define cfgBIF_CFG_DEV1_RC_LINK_CAP2 0x0084 |
| #define cfgBIF_CFG_DEV1_RC_LINK_CNTL2 0x0088 |
| #define cfgBIF_CFG_DEV1_RC_LINK_STATUS2 0x008a |
| #define cfgBIF_CFG_DEV1_RC_SLOT_CAP2 0x008c |
| #define cfgBIF_CFG_DEV1_RC_SLOT_CNTL2 0x0090 |
| #define cfgBIF_CFG_DEV1_RC_SLOT_STATUS2 0x0092 |
| #define cfgBIF_CFG_DEV1_RC_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV1_RC_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV1_RC_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA 0x00aa |
| #define cfgBIF_CFG_DEV1_RC_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64 0x00ae |
| #define cfgBIF_CFG_DEV1_RC_SSID_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV1_RC_SSID_CAP 0x00c4 |
| #define cfgBIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIF_CFG_DEV1_RC_MSI_MAP_CAP 0x00ca |
| #define cfgBIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV1_RC_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST 0x0400 |
| #define cfgBIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP 0x0404 |
| #define cfgBIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS 0x0408 |
| #define cfgBIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 |
| #define cfgBIF_CFG_DEV1_RC_LINK_CAP_16GT 0x0414 |
| #define cfgBIF_CFG_DEV1_RC_LINK_CNTL_16GT 0x0418 |
| #define cfgBIF_CFG_DEV1_RC_LINK_STATUS_16GT 0x041c |
| #define cfgBIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 |
| #define cfgBIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 |
| #define cfgBIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 |
| #define cfgBIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 |
| #define cfgBIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 |
| #define cfgBIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 |
| #define cfgBIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 |
| #define cfgBIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 |
| #define cfgBIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 |
| #define cfgBIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 |
| #define cfgBIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 |
| #define cfgBIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 |
| #define cfgBIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 |
| #define cfgBIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT 0x043a |
| #define cfgBIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT 0x043b |
| #define cfgBIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT 0x043c |
| #define cfgBIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT 0x043d |
| #define cfgBIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT 0x043e |
| #define cfgBIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT 0x043f |
| #define cfgBIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST 0x0450 |
| #define cfgBIF_CFG_DEV1_RC_MARGINING_PORT_CAP 0x0454 |
| #define cfgBIF_CFG_DEV1_RC_MARGINING_PORT_STATUS 0x0456 |
| #define cfgBIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL 0x0458 |
| #define cfgBIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS 0x045a |
| #define cfgBIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL 0x045c |
| #define cfgBIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS 0x045e |
| #define cfgBIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL 0x0460 |
| #define cfgBIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS 0x0462 |
| #define cfgBIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL 0x0464 |
| #define cfgBIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS 0x0466 |
| #define cfgBIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL 0x0468 |
| #define cfgBIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS 0x046a |
| #define cfgBIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL 0x046c |
| #define cfgBIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS 0x046e |
| #define cfgBIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL 0x0470 |
| #define cfgBIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS 0x0472 |
| #define cfgBIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL 0x0474 |
| #define cfgBIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS 0x0476 |
| #define cfgBIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL 0x0478 |
| #define cfgBIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS 0x047a |
| #define cfgBIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL 0x047c |
| #define cfgBIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS 0x047e |
| #define cfgBIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL 0x0480 |
| #define cfgBIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS 0x0482 |
| #define cfgBIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL 0x0484 |
| #define cfgBIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS 0x0486 |
| #define cfgBIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL 0x0488 |
| #define cfgBIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS 0x048a |
| #define cfgBIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL 0x048c |
| #define cfgBIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS 0x048e |
| #define cfgBIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL 0x0490 |
| #define cfgBIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS 0x0492 |
| #define cfgBIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL 0x0494 |
| #define cfgBIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS 0x0496 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV2_RC_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIF_CFG_DEV2_RC_IO_BASE_LIMIT 0x001c |
| #define cfgBIF_CFG_DEV2_RC_SECONDARY_STATUS 0x001e |
| #define cfgBIF_CFG_DEV2_RC_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIF_CFG_DEV2_RC_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIF_CFG_DEV2_RC_PREF_BASE_UPPER 0x0028 |
| #define cfgBIF_CFG_DEV2_RC_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIF_CFG_DEV2_RC_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIF_CFG_DEV2_RC_IRQ_BRIDGE_CNTL 0x003e |
| #define cfgBIF_CFG_DEV2_RC_SLOT_CAP 0x006c |
| #define cfgBIF_CFG_DEV2_RC_SLOT_CNTL 0x0070 |
| #define cfgBIF_CFG_DEV2_RC_SLOT_STATUS 0x0072 |
| #define cfgBIF_CFG_DEV2_RC_SLOT_CAP2 0x008c |
| #define cfgBIF_CFG_DEV2_RC_SLOT_CNTL2 0x0090 |
| #define cfgBIF_CFG_DEV2_RC_SLOT_STATUS2 0x0092 |
| #define cfgBIF_CFG_DEV2_RC_SSID_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV2_RC_SSID_CAP 0x00c4 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x0028 |
| #define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x00aa |
| #define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x00ae |
| #define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST 0x02b0 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP 0x02b4 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL 0x02b6 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL 0x02c4 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS 0x02c6 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x02d0 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x02d4 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x02d6 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CAP 0x02f4 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 0x0300 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 0x0304 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x0320 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x0324 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x032e |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP 0x0334 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL 0x0338 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS 0x033a |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS 0x033c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS 0x033e |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS 0x0340 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE 0x0346 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID 0x034a |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x0400 |
| #define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x0404 |
| #define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x0408 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 |
| #define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x0414 |
| #define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x0418 |
| #define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x041c |
| #define cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 |
| #define cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 |
| #define cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x0450 |
| #define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x0454 |
| #define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x0456 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x0458 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x045a |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x045c |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x045e |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x0460 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x0462 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x0464 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x0466 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x0468 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x046a |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x046c |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x046e |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x0470 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x0472 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x0474 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x0476 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x0478 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x047a |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x047c |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x047e |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x0480 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x0482 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x0484 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x0486 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x0488 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x048a |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x048c |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x048e |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x0490 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x0492 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x0494 |
| #define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x0496 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec |
| #define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 |
| #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0580 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0584 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0588 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x058c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0590 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0594 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0598 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x059c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x05a0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x05a4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x05a8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x05ac |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x05b0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x05b4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x05b8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x05bc |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x05c0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x05c4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x05c8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x05cc |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x05d0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x05d4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x05d8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x05dc |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x05e0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x05e4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x05e8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x05ec |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x05f0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x05f4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x05f8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x05fc |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x0600 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0604 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0608 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x060c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x0610 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0614 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0618 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x061c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x0620 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x0624 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x0628 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x062c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x0630 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0640 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0644 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0648 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x064c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0650 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0654 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0658 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x065c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0660 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x0670 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x0674 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x0678 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x067c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x0680 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x0684 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x0688 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x068c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x0690 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x06a0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x06a4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x06a8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x06ac |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x06b0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x06b4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x06b8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x06bc |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x06c0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x06d0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x06d4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x06d8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x06dc |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x06e0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x06e4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x06e8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x06ec |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x06f0 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF1_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF1_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF1_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF1_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF1_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF1_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF1_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF1_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF1_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF1_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF1_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x0028 |
| #define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF1_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF1_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF1_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF1_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF1_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x00aa |
| #define cfgBIF_CFG_DEV0_EPF1_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x00ae |
| #define cfgBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF1_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST 0x02b0 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_ATS_CAP 0x02b4 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL 0x02b6 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL 0x02c4 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS 0x02c6 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x02d0 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x02d4 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x02d6 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_CAP 0x02f4 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0 0x0300 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1 0x0304 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST 0x0320 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP 0x0324 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x032e |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST 0x0330 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP 0x0334 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL 0x0338 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS 0x033a |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS 0x033c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS 0x033e |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS 0x0340 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE 0x0346 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID 0x034a |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST 0x0400 |
| #define cfgBIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP 0x0404 |
| #define cfgBIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS 0x0408 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 |
| #define cfgBIF_CFG_DEV0_EPF1_LINK_CAP_16GT 0x0414 |
| #define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL_16GT 0x0418 |
| #define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS_16GT 0x041c |
| #define cfgBIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 |
| #define cfgBIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 |
| #define cfgBIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT 0x043a |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT 0x043b |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT 0x043c |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT 0x043d |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT 0x043e |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT 0x043f |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST 0x0450 |
| #define cfgBIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP 0x0454 |
| #define cfgBIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS 0x0456 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL 0x0458 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS 0x045a |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL 0x045c |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS 0x045e |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL 0x0460 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS 0x0462 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL 0x0464 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS 0x0466 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL 0x0468 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS 0x046a |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL 0x046c |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS 0x046e |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL 0x0470 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS 0x0472 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL 0x0474 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS 0x0476 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL 0x0478 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS 0x047a |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL 0x047c |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS 0x047e |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL 0x0480 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS 0x0482 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL 0x0484 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS 0x0486 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL 0x0488 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS 0x048a |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL 0x048c |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS 0x048e |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL 0x0490 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS 0x0492 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL 0x0494 |
| #define cfgBIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS 0x0496 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP 0x04cc |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP 0x04dc |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP 0x04ec |
| #define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF2_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF2_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF2_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF2_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF2_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF2_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF2_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF2_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF2_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF2_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF2_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF2_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR 0x0028 |
| #define cfgBIF_CFG_DEV0_EPF2_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF2_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF2_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF2_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF2_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF2_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF2_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF2_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF2_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF2_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV0_EPF2_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV0_EPF2_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF2_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF2_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF2_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF2_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF2_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF2_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF2_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF2_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF2_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF2_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF2_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF2_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF2_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF2_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA 0x00aa |
| #define cfgBIF_CFG_DEV0_EPF2_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64 0x00ae |
| #define cfgBIF_CFG_DEV0_EPF2_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF2_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF2_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF2_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF2_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF2_SATA_CAP_0 0x00d0 |
| #define cfgBIF_CFG_DEV0_EPF2_SATA_CAP_1 0x00d4 |
| #define cfgBIF_CFG_DEV0_EPF2_SATA_IDP_INDEX 0x00d8 |
| #define cfgBIF_CFG_DEV0_EPF2_SATA_IDP_DATA 0x00dc |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST 0x02d0 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP 0x02d4 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL 0x02d6 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF3_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF3_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF3_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF3_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF3_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF3_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF3_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF3_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF3_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF3_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF3_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF3_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR 0x0028 |
| #define cfgBIF_CFG_DEV0_EPF3_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF3_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF3_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF3_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF3_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF3_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF3_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF3_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF3_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF3_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV0_EPF3_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV0_EPF3_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF3_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF3_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF3_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF3_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF3_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF3_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF3_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF3_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF3_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF3_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF3_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF3_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF3_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF3_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA 0x00aa |
| #define cfgBIF_CFG_DEV0_EPF3_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64 0x00ae |
| #define cfgBIF_CFG_DEV0_EPF3_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF3_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF3_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF3_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF3_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF3_SATA_CAP_0 0x00d0 |
| #define cfgBIF_CFG_DEV0_EPF3_SATA_CAP_1 0x00d4 |
| #define cfgBIF_CFG_DEV0_EPF3_SATA_IDP_INDEX 0x00d8 |
| #define cfgBIF_CFG_DEV0_EPF3_SATA_IDP_DATA 0x00dc |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST 0x02d0 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP 0x02d4 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL 0x02d6 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF4_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF4_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF4_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF4_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF4_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF4_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF4_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF4_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF4_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF4_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF4_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF4_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF4_CARDBUS_CIS_PTR 0x0028 |
| #define cfgBIF_CFG_DEV0_EPF4_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF4_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF4_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF4_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF4_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF4_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF4_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF4_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF4_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF4_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF4_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV0_EPF4_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV0_EPF4_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF4_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF4_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF4_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF4_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF4_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF4_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF4_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF4_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF4_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF4_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF4_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF4_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF4_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF4_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF4_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA 0x00aa |
| #define cfgBIF_CFG_DEV0_EPF4_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64 0x00ae |
| #define cfgBIF_CFG_DEV0_EPF4_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF4_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF4_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF4_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF4_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF4_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST 0x02d0 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_PASID_CAP 0x02d4 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL 0x02d6 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF5_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF5_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF5_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF5_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF5_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF5_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF5_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF5_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF5_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF5_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF5_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF5_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF5_CARDBUS_CIS_PTR 0x0028 |
| #define cfgBIF_CFG_DEV0_EPF5_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF5_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF5_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF5_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF5_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF5_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF5_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF5_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF5_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF5_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF5_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV0_EPF5_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV0_EPF5_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF5_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF5_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF5_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF5_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF5_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF5_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF5_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF5_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF5_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF5_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF5_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF5_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF5_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF5_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF5_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA 0x00aa |
| #define cfgBIF_CFG_DEV0_EPF5_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64 0x00ae |
| #define cfgBIF_CFG_DEV0_EPF5_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF5_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF5_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF5_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF5_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF5_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST 0x02d0 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_PASID_CAP 0x02d4 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL 0x02d6 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF6_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF6_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF6_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF6_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF6_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF6_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF6_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF6_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF6_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF6_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF6_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF6_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF6_CARDBUS_CIS_PTR 0x0028 |
| #define cfgBIF_CFG_DEV0_EPF6_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF6_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF6_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF6_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF6_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF6_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF6_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF6_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF6_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF6_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF6_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV0_EPF6_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV0_EPF6_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF6_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF6_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF6_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF6_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF6_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF6_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF6_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF6_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF6_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF6_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF6_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF6_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF6_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF6_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF6_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA 0x00aa |
| #define cfgBIF_CFG_DEV0_EPF6_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64 0x00ae |
| #define cfgBIF_CFG_DEV0_EPF6_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF6_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF6_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF6_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF6_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF6_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST 0x02d0 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_PASID_CAP 0x02d4 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL 0x02d6 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_pcie0_bifplr0_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR0_VENDOR_ID 0x0000 |
| #define cfgBIFPLR0_DEVICE_ID 0x0002 |
| #define cfgBIFPLR0_COMMAND 0x0004 |
| #define cfgBIFPLR0_STATUS 0x0006 |
| #define cfgBIFPLR0_REVISION_ID 0x0008 |
| #define cfgBIFPLR0_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR0_SUB_CLASS 0x000a |
| #define cfgBIFPLR0_BASE_CLASS 0x000b |
| #define cfgBIFPLR0_CACHE_LINE 0x000c |
| #define cfgBIFPLR0_LATENCY 0x000d |
| #define cfgBIFPLR0_HEADER 0x000e |
| #define cfgBIFPLR0_BIST 0x000f |
| #define cfgBIFPLR0_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR0_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR0_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR0_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR0_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR0_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR0_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR0_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR0_CAP_PTR 0x0034 |
| #define cfgBIFPLR0_ROM_BASE_ADDR 0x0038 |
| #define cfgBIFPLR0_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR0_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR0_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR0_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIFPLR0_ADAPTER_ID_W 0x004c |
| #define cfgBIFPLR0_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR0_PMI_CAP 0x0052 |
| #define cfgBIFPLR0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR0_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR0_PCIE_CAP 0x005a |
| #define cfgBIFPLR0_DEVICE_CAP 0x005c |
| #define cfgBIFPLR0_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR0_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR0_LINK_CAP 0x0064 |
| #define cfgBIFPLR0_LINK_CNTL 0x0068 |
| #define cfgBIFPLR0_LINK_STATUS 0x006a |
| #define cfgBIFPLR0_SLOT_CAP 0x006c |
| #define cfgBIFPLR0_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR0_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR0_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR0_ROOT_CAP 0x0076 |
| #define cfgBIFPLR0_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR0_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR0_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR0_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR0_LINK_CAP2 0x0084 |
| #define cfgBIFPLR0_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR0_LINK_STATUS2 0x008a |
| #define cfgBIFPLR0_SLOT_CAP2 0x008c |
| #define cfgBIFPLR0_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR0_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR0_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR0_SSID_CAP 0x00c4 |
| #define cfgBIFPLR0_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR0_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR0_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR0_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR0_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR0_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR0_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR0_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR0_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR0_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR0_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR0_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR0_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR0_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR0_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR0_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR0_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR0_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR0_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR0_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR0_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR0_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR0_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR0_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR0_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR0_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR0_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR0_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR0_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR0_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR0_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR0_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR0_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR0_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR0_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR0_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR0_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR0_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR0_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR0_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR0_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR0_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR0_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR0_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR0_PCIE_ESM_CAP_7 0x03ec |
| #define cfgBIFPLR0_PCIE_DLF_ENH_CAP_LIST 0x0400 |
| #define cfgBIFPLR0_DATA_LINK_FEATURE_CAP 0x0404 |
| #define cfgBIFPLR0_DATA_LINK_FEATURE_STATUS 0x0408 |
| #define cfgBIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 |
| #define cfgBIFPLR0_LINK_CAP_16GT 0x0414 |
| #define cfgBIFPLR0_LINK_CNTL_16GT 0x0418 |
| #define cfgBIFPLR0_LINK_STATUS_16GT 0x041c |
| #define cfgBIFPLR0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 |
| #define cfgBIFPLR0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 |
| #define cfgBIFPLR0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 |
| #define cfgBIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 |
| #define cfgBIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 |
| #define cfgBIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 |
| #define cfgBIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 |
| #define cfgBIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 |
| #define cfgBIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 |
| #define cfgBIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 |
| #define cfgBIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 |
| #define cfgBIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 |
| #define cfgBIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 |
| #define cfgBIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a |
| #define cfgBIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b |
| #define cfgBIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c |
| #define cfgBIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d |
| #define cfgBIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e |
| #define cfgBIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f |
| #define cfgBIFPLR0_PCIE_MARGINING_ENH_CAP_LIST 0x0440 |
| #define cfgBIFPLR0_MARGINING_PORT_CAP 0x0444 |
| #define cfgBIFPLR0_MARGINING_PORT_STATUS 0x0446 |
| #define cfgBIFPLR0_LANE_0_MARGINING_LANE_CNTL 0x0448 |
| #define cfgBIFPLR0_LANE_0_MARGINING_LANE_STATUS 0x044a |
| #define cfgBIFPLR0_LANE_1_MARGINING_LANE_CNTL 0x044c |
| #define cfgBIFPLR0_LANE_1_MARGINING_LANE_STATUS 0x044e |
| #define cfgBIFPLR0_LANE_2_MARGINING_LANE_CNTL 0x0450 |
| #define cfgBIFPLR0_LANE_2_MARGINING_LANE_STATUS 0x0452 |
| #define cfgBIFPLR0_LANE_3_MARGINING_LANE_CNTL 0x0454 |
| #define cfgBIFPLR0_LANE_3_MARGINING_LANE_STATUS 0x0456 |
| #define cfgBIFPLR0_LANE_4_MARGINING_LANE_CNTL 0x0458 |
| #define cfgBIFPLR0_LANE_4_MARGINING_LANE_STATUS 0x045a |
| #define cfgBIFPLR0_LANE_5_MARGINING_LANE_CNTL 0x045c |
| #define cfgBIFPLR0_LANE_5_MARGINING_LANE_STATUS 0x045e |
| #define cfgBIFPLR0_LANE_6_MARGINING_LANE_CNTL 0x0460 |
| #define cfgBIFPLR0_LANE_6_MARGINING_LANE_STATUS 0x0462 |
| #define cfgBIFPLR0_LANE_7_MARGINING_LANE_CNTL 0x0464 |
| #define cfgBIFPLR0_LANE_7_MARGINING_LANE_STATUS 0x0466 |
| #define cfgBIFPLR0_LANE_8_MARGINING_LANE_CNTL 0x0468 |
| #define cfgBIFPLR0_LANE_8_MARGINING_LANE_STATUS 0x046a |
| #define cfgBIFPLR0_LANE_9_MARGINING_LANE_CNTL 0x046c |
| #define cfgBIFPLR0_LANE_9_MARGINING_LANE_STATUS 0x046e |
| #define cfgBIFPLR0_LANE_10_MARGINING_LANE_CNTL 0x0470 |
| #define cfgBIFPLR0_LANE_10_MARGINING_LANE_STATUS 0x0472 |
| #define cfgBIFPLR0_LANE_11_MARGINING_LANE_CNTL 0x0474 |
| #define cfgBIFPLR0_LANE_11_MARGINING_LANE_STATUS 0x0476 |
| #define cfgBIFPLR0_LANE_12_MARGINING_LANE_CNTL 0x0478 |
| #define cfgBIFPLR0_LANE_12_MARGINING_LANE_STATUS 0x047a |
| #define cfgBIFPLR0_LANE_13_MARGINING_LANE_CNTL 0x047c |
| #define cfgBIFPLR0_LANE_13_MARGINING_LANE_STATUS 0x047e |
| #define cfgBIFPLR0_LANE_14_MARGINING_LANE_CNTL 0x0480 |
| #define cfgBIFPLR0_LANE_14_MARGINING_LANE_STATUS 0x0482 |
| #define cfgBIFPLR0_LANE_15_MARGINING_LANE_CNTL 0x0484 |
| #define cfgBIFPLR0_LANE_15_MARGINING_LANE_STATUS 0x0486 |
| #define cfgBIFPLR0_PCIE_CCIX_CAP_LIST 0x0488 |
| #define cfgBIFPLR0_PCIE_CCIX_HEADER_1 0x048c |
| #define cfgBIFPLR0_PCIE_CCIX_HEADER_2 0x0490 |
| #define cfgBIFPLR0_PCIE_CCIX_CAP 0x0492 |
| #define cfgBIFPLR0_PCIE_CCIX_ESM_REQD_CAP 0x0494 |
| #define cfgBIFPLR0_PCIE_CCIX_ESM_OPTL_CAP 0x0498 |
| #define cfgBIFPLR0_PCIE_CCIX_ESM_STATUS 0x049c |
| #define cfgBIFPLR0_PCIE_CCIX_ESM_CNTL 0x04a0 |
| #define cfgBIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x04a4 |
| #define cfgBIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x04a5 |
| #define cfgBIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x04a6 |
| #define cfgBIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x04a7 |
| #define cfgBIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x04a8 |
| #define cfgBIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x04a9 |
| #define cfgBIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x04aa |
| #define cfgBIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x04ab |
| #define cfgBIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x04ac |
| #define cfgBIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x04ad |
| #define cfgBIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x04ae |
| #define cfgBIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x04af |
| #define cfgBIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x04b0 |
| #define cfgBIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x04b1 |
| #define cfgBIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x04b2 |
| #define cfgBIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x04b3 |
| #define cfgBIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x04b4 |
| #define cfgBIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x04b5 |
| #define cfgBIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x04b6 |
| #define cfgBIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x04b7 |
| #define cfgBIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x04b8 |
| #define cfgBIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x04b9 |
| #define cfgBIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x04ba |
| #define cfgBIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x04bb |
| #define cfgBIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x04bc |
| #define cfgBIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x04bd |
| #define cfgBIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x04be |
| #define cfgBIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x04bf |
| #define cfgBIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x04c0 |
| #define cfgBIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x04c1 |
| #define cfgBIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x04c2 |
| #define cfgBIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x04c3 |
| #define cfgBIFPLR0_PCIE_CCIX_TRANS_CAP 0x04c4 |
| #define cfgBIFPLR0_PCIE_CCIX_TRANS_CNTL 0x04c8 |
| #define cfgBIFPLR0_LINK_CAP_32GT 0x0504 |
| #define cfgBIFPLR0_LINK_CNTL_32GT 0x0508 |
| #define cfgBIFPLR0_LINK_STATUS_32GT 0x050c |
| |
| |
| // addressBlock: nbio_pcie0_bifplr1_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR1_VENDOR_ID 0x0000 |
| #define cfgBIFPLR1_DEVICE_ID 0x0002 |
| #define cfgBIFPLR1_COMMAND 0x0004 |
| #define cfgBIFPLR1_STATUS 0x0006 |
| #define cfgBIFPLR1_REVISION_ID 0x0008 |
| #define cfgBIFPLR1_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR1_SUB_CLASS 0x000a |
| #define cfgBIFPLR1_BASE_CLASS 0x000b |
| #define cfgBIFPLR1_CACHE_LINE 0x000c |
| #define cfgBIFPLR1_LATENCY 0x000d |
| #define cfgBIFPLR1_HEADER 0x000e |
| #define cfgBIFPLR1_BIST 0x000f |
| #define cfgBIFPLR1_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR1_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR1_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR1_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR1_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR1_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR1_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR1_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR1_CAP_PTR 0x0034 |
| #define cfgBIFPLR1_ROM_BASE_ADDR 0x0038 |
| #define cfgBIFPLR1_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR1_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR1_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR1_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIFPLR1_ADAPTER_ID_W 0x004c |
| #define cfgBIFPLR1_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR1_PMI_CAP 0x0052 |
| #define cfgBIFPLR1_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR1_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR1_PCIE_CAP 0x005a |
| #define cfgBIFPLR1_DEVICE_CAP 0x005c |
| #define cfgBIFPLR1_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR1_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR1_LINK_CAP 0x0064 |
| #define cfgBIFPLR1_LINK_CNTL 0x0068 |
| #define cfgBIFPLR1_LINK_STATUS 0x006a |
| #define cfgBIFPLR1_SLOT_CAP 0x006c |
| #define cfgBIFPLR1_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR1_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR1_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR1_ROOT_CAP 0x0076 |
| #define cfgBIFPLR1_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR1_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR1_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR1_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR1_LINK_CAP2 0x0084 |
| #define cfgBIFPLR1_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR1_LINK_STATUS2 0x008a |
| #define cfgBIFPLR1_SLOT_CAP2 0x008c |
| #define cfgBIFPLR1_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR1_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR1_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR1_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR1_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR1_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR1_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR1_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR1_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR1_SSID_CAP 0x00c4 |
| #define cfgBIFPLR1_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR1_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR1_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR1_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR1_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR1_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR1_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR1_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR1_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR1_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR1_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR1_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR1_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR1_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR1_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR1_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR1_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR1_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR1_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR1_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR1_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR1_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR1_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR1_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR1_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR1_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR1_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR1_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR1_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR1_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR1_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR1_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR1_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR1_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR1_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR1_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR1_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR1_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR1_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR1_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR1_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR1_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR1_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR1_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR1_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR1_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR1_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR1_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR1_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR1_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR1_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR1_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR1_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR1_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR1_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR1_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR1_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR1_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR1_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR1_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR1_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR1_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR1_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR1_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR1_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR1_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR1_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR1_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR1_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR1_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR1_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR1_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR1_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR1_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR1_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR1_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR1_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR1_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR1_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR1_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR1_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR1_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR1_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR1_PCIE_ESM_CAP_7 0x03ec |
| #define cfgBIFPLR1_PCIE_DLF_ENH_CAP_LIST 0x0400 |
| #define cfgBIFPLR1_DATA_LINK_FEATURE_CAP 0x0404 |
| #define cfgBIFPLR1_DATA_LINK_FEATURE_STATUS 0x0408 |
| #define cfgBIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 |
| #define cfgBIFPLR1_LINK_CAP_16GT 0x0414 |
| #define cfgBIFPLR1_LINK_CNTL_16GT 0x0418 |
| #define cfgBIFPLR1_LINK_STATUS_16GT 0x041c |
| #define cfgBIFPLR1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 |
| #define cfgBIFPLR1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 |
| #define cfgBIFPLR1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 |
| #define cfgBIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 |
| #define cfgBIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 |
| #define cfgBIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 |
| #define cfgBIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 |
| #define cfgBIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 |
| #define cfgBIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 |
| #define cfgBIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 |
| #define cfgBIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 |
| #define cfgBIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 |
| #define cfgBIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 |
| #define cfgBIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT 0x043a |
| #define cfgBIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT 0x043b |
| #define cfgBIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT 0x043c |
| #define cfgBIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT 0x043d |
| #define cfgBIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT 0x043e |
| #define cfgBIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT 0x043f |
| #define cfgBIFPLR1_PCIE_MARGINING_ENH_CAP_LIST 0x0440 |
| #define cfgBIFPLR1_MARGINING_PORT_CAP 0x0444 |
| #define cfgBIFPLR1_MARGINING_PORT_STATUS 0x0446 |
| #define cfgBIFPLR1_LANE_0_MARGINING_LANE_CNTL 0x0448 |
| #define cfgBIFPLR1_LANE_0_MARGINING_LANE_STATUS 0x044a |
| #define cfgBIFPLR1_LANE_1_MARGINING_LANE_CNTL 0x044c |
| #define cfgBIFPLR1_LANE_1_MARGINING_LANE_STATUS 0x044e |
| #define cfgBIFPLR1_LANE_2_MARGINING_LANE_CNTL 0x0450 |
| #define cfgBIFPLR1_LANE_2_MARGINING_LANE_STATUS 0x0452 |
| #define cfgBIFPLR1_LANE_3_MARGINING_LANE_CNTL 0x0454 |
| #define cfgBIFPLR1_LANE_3_MARGINING_LANE_STATUS 0x0456 |
| #define cfgBIFPLR1_LANE_4_MARGINING_LANE_CNTL 0x0458 |
| #define cfgBIFPLR1_LANE_4_MARGINING_LANE_STATUS 0x045a |
| #define cfgBIFPLR1_LANE_5_MARGINING_LANE_CNTL 0x045c |
| #define cfgBIFPLR1_LANE_5_MARGINING_LANE_STATUS 0x045e |
| #define cfgBIFPLR1_LANE_6_MARGINING_LANE_CNTL 0x0460 |
| #define cfgBIFPLR1_LANE_6_MARGINING_LANE_STATUS 0x0462 |
| #define cfgBIFPLR1_LANE_7_MARGINING_LANE_CNTL 0x0464 |
| #define cfgBIFPLR1_LANE_7_MARGINING_LANE_STATUS 0x0466 |
| #define cfgBIFPLR1_LANE_8_MARGINING_LANE_CNTL 0x0468 |
| #define cfgBIFPLR1_LANE_8_MARGINING_LANE_STATUS 0x046a |
| #define cfgBIFPLR1_LANE_9_MARGINING_LANE_CNTL 0x046c |
| #define cfgBIFPLR1_LANE_9_MARGINING_LANE_STATUS 0x046e |
| #define cfgBIFPLR1_LANE_10_MARGINING_LANE_CNTL 0x0470 |
| #define cfgBIFPLR1_LANE_10_MARGINING_LANE_STATUS 0x0472 |
| #define cfgBIFPLR1_LANE_11_MARGINING_LANE_CNTL 0x0474 |
| #define cfgBIFPLR1_LANE_11_MARGINING_LANE_STATUS 0x0476 |
| #define cfgBIFPLR1_LANE_12_MARGINING_LANE_CNTL 0x0478 |
| #define cfgBIFPLR1_LANE_12_MARGINING_LANE_STATUS 0x047a |
| #define cfgBIFPLR1_LANE_13_MARGINING_LANE_CNTL 0x047c |
| #define cfgBIFPLR1_LANE_13_MARGINING_LANE_STATUS 0x047e |
| #define cfgBIFPLR1_LANE_14_MARGINING_LANE_CNTL 0x0480 |
| #define cfgBIFPLR1_LANE_14_MARGINING_LANE_STATUS 0x0482 |
| #define cfgBIFPLR1_LANE_15_MARGINING_LANE_CNTL 0x0484 |
| #define cfgBIFPLR1_LANE_15_MARGINING_LANE_STATUS 0x0486 |
| #define cfgBIFPLR1_PCIE_CCIX_CAP_LIST 0x0488 |
| #define cfgBIFPLR1_PCIE_CCIX_HEADER_1 0x048c |
| #define cfgBIFPLR1_PCIE_CCIX_HEADER_2 0x0490 |
| #define cfgBIFPLR1_PCIE_CCIX_CAP 0x0492 |
| #define cfgBIFPLR1_PCIE_CCIX_ESM_REQD_CAP 0x0494 |
| #define cfgBIFPLR1_PCIE_CCIX_ESM_OPTL_CAP 0x0498 |
| #define cfgBIFPLR1_PCIE_CCIX_ESM_STATUS 0x049c |
| #define cfgBIFPLR1_PCIE_CCIX_ESM_CNTL 0x04a0 |
| #define cfgBIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x04a4 |
| #define cfgBIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x04a5 |
| #define cfgBIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x04a6 |
| #define cfgBIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x04a7 |
| #define cfgBIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x04a8 |
| #define cfgBIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x04a9 |
| #define cfgBIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x04aa |
| #define cfgBIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x04ab |
| #define cfgBIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x04ac |
| #define cfgBIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x04ad |
| #define cfgBIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x04ae |
| #define cfgBIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x04af |
| #define cfgBIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x04b0 |
| #define cfgBIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x04b1 |
| #define cfgBIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x04b2 |
| #define cfgBIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x04b3 |
| #define cfgBIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x04b4 |
| #define cfgBIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x04b5 |
| #define cfgBIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x04b6 |
| #define cfgBIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x04b7 |
| #define cfgBIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x04b8 |
| #define cfgBIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x04b9 |
| #define cfgBIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x04ba |
| #define cfgBIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x04bb |
| #define cfgBIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x04bc |
| #define cfgBIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x04bd |
| #define cfgBIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x04be |
| #define cfgBIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x04bf |
| #define cfgBIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x04c0 |
| #define cfgBIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x04c1 |
| #define cfgBIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x04c2 |
| #define cfgBIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x04c3 |
| #define cfgBIFPLR1_PCIE_CCIX_TRANS_CAP 0x04c4 |
| #define cfgBIFPLR1_PCIE_CCIX_TRANS_CNTL 0x04c8 |
| #define cfgBIFPLR1_LINK_CAP_32GT 0x0504 |
| #define cfgBIFPLR1_LINK_CNTL_32GT 0x0508 |
| #define cfgBIFPLR1_LINK_STATUS_32GT 0x050c |
| |
| |
| // addressBlock: nbio_pcie0_bifplr2_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR2_VENDOR_ID 0x0000 |
| #define cfgBIFPLR2_DEVICE_ID 0x0002 |
| #define cfgBIFPLR2_COMMAND 0x0004 |
| #define cfgBIFPLR2_STATUS 0x0006 |
| #define cfgBIFPLR2_REVISION_ID 0x0008 |
| #define cfgBIFPLR2_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR2_SUB_CLASS 0x000a |
| #define cfgBIFPLR2_BASE_CLASS 0x000b |
| #define cfgBIFPLR2_CACHE_LINE 0x000c |
| #define cfgBIFPLR2_LATENCY 0x000d |
| #define cfgBIFPLR2_HEADER 0x000e |
| #define cfgBIFPLR2_BIST 0x000f |
| #define cfgBIFPLR2_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR2_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR2_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR2_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR2_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR2_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR2_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR2_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR2_CAP_PTR 0x0034 |
| #define cfgBIFPLR2_ROM_BASE_ADDR 0x0038 |
| #define cfgBIFPLR2_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR2_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR2_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR2_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIFPLR2_ADAPTER_ID_W 0x004c |
| #define cfgBIFPLR2_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR2_PMI_CAP 0x0052 |
| #define cfgBIFPLR2_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR2_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR2_PCIE_CAP 0x005a |
| #define cfgBIFPLR2_DEVICE_CAP 0x005c |
| #define cfgBIFPLR2_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR2_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR2_LINK_CAP 0x0064 |
| #define cfgBIFPLR2_LINK_CNTL 0x0068 |
| #define cfgBIFPLR2_LINK_STATUS 0x006a |
| #define cfgBIFPLR2_SLOT_CAP 0x006c |
| #define cfgBIFPLR2_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR2_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR2_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR2_ROOT_CAP 0x0076 |
| #define cfgBIFPLR2_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR2_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR2_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR2_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR2_LINK_CAP2 0x0084 |
| #define cfgBIFPLR2_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR2_LINK_STATUS2 0x008a |
| #define cfgBIFPLR2_SLOT_CAP2 0x008c |
| #define cfgBIFPLR2_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR2_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR2_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR2_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR2_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR2_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR2_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR2_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR2_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR2_SSID_CAP 0x00c4 |
| #define cfgBIFPLR2_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR2_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR2_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR2_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR2_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR2_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR2_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR2_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR2_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR2_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR2_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR2_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR2_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR2_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR2_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR2_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR2_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR2_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR2_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR2_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR2_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR2_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR2_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR2_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR2_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR2_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR2_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR2_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR2_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR2_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR2_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR2_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR2_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR2_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR2_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR2_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR2_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR2_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR2_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR2_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR2_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR2_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR2_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR2_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR2_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR2_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR2_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR2_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR2_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR2_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR2_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR2_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR2_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR2_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR2_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR2_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR2_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR2_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR2_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR2_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR2_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR2_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR2_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR2_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR2_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR2_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR2_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR2_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR2_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR2_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR2_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR2_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR2_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR2_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR2_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR2_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR2_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR2_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR2_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR2_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR2_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR2_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR2_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR2_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR2_PCIE_ESM_CAP_7 0x03ec |
| #define cfgBIFPLR2_PCIE_DLF_ENH_CAP_LIST 0x0400 |
| #define cfgBIFPLR2_DATA_LINK_FEATURE_CAP 0x0404 |
| #define cfgBIFPLR2_DATA_LINK_FEATURE_STATUS 0x0408 |
| #define cfgBIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 |
| #define cfgBIFPLR2_LINK_CAP_16GT 0x0414 |
| #define cfgBIFPLR2_LINK_CNTL_16GT 0x0418 |
| #define cfgBIFPLR2_LINK_STATUS_16GT 0x041c |
| #define cfgBIFPLR2_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 |
| #define cfgBIFPLR2_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 |
| #define cfgBIFPLR2_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 |
| #define cfgBIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 |
| #define cfgBIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 |
| #define cfgBIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 |
| #define cfgBIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 |
| #define cfgBIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 |
| #define cfgBIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 |
| #define cfgBIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 |
| #define cfgBIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 |
| #define cfgBIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 |
| #define cfgBIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 |
| #define cfgBIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT 0x043a |
| #define cfgBIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT 0x043b |
| #define cfgBIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT 0x043c |
| #define cfgBIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT 0x043d |
| #define cfgBIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT 0x043e |
| #define cfgBIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT 0x043f |
| #define cfgBIFPLR2_PCIE_MARGINING_ENH_CAP_LIST 0x0440 |
| #define cfgBIFPLR2_MARGINING_PORT_CAP 0x0444 |
| #define cfgBIFPLR2_MARGINING_PORT_STATUS 0x0446 |
| #define cfgBIFPLR2_LANE_0_MARGINING_LANE_CNTL 0x0448 |
| #define cfgBIFPLR2_LANE_0_MARGINING_LANE_STATUS 0x044a |
| #define cfgBIFPLR2_LANE_1_MARGINING_LANE_CNTL 0x044c |
| #define cfgBIFPLR2_LANE_1_MARGINING_LANE_STATUS 0x044e |
| #define cfgBIFPLR2_LANE_2_MARGINING_LANE_CNTL 0x0450 |
| #define cfgBIFPLR2_LANE_2_MARGINING_LANE_STATUS 0x0452 |
| #define cfgBIFPLR2_LANE_3_MARGINING_LANE_CNTL 0x0454 |
| #define cfgBIFPLR2_LANE_3_MARGINING_LANE_STATUS 0x0456 |
| #define cfgBIFPLR2_LANE_4_MARGINING_LANE_CNTL 0x0458 |
| #define cfgBIFPLR2_LANE_4_MARGINING_LANE_STATUS 0x045a |
| #define cfgBIFPLR2_LANE_5_MARGINING_LANE_CNTL 0x045c |
| #define cfgBIFPLR2_LANE_5_MARGINING_LANE_STATUS 0x045e |
| #define cfgBIFPLR2_LANE_6_MARGINING_LANE_CNTL 0x0460 |
| #define cfgBIFPLR2_LANE_6_MARGINING_LANE_STATUS 0x0462 |
| #define cfgBIFPLR2_LANE_7_MARGINING_LANE_CNTL 0x0464 |
| #define cfgBIFPLR2_LANE_7_MARGINING_LANE_STATUS 0x0466 |
| #define cfgBIFPLR2_LANE_8_MARGINING_LANE_CNTL 0x0468 |
| #define cfgBIFPLR2_LANE_8_MARGINING_LANE_STATUS 0x046a |
| #define cfgBIFPLR2_LANE_9_MARGINING_LANE_CNTL 0x046c |
| #define cfgBIFPLR2_LANE_9_MARGINING_LANE_STATUS 0x046e |
| #define cfgBIFPLR2_LANE_10_MARGINING_LANE_CNTL 0x0470 |
| #define cfgBIFPLR2_LANE_10_MARGINING_LANE_STATUS 0x0472 |
| #define cfgBIFPLR2_LANE_11_MARGINING_LANE_CNTL 0x0474 |
| #define cfgBIFPLR2_LANE_11_MARGINING_LANE_STATUS 0x0476 |
| #define cfgBIFPLR2_LANE_12_MARGINING_LANE_CNTL 0x0478 |
| #define cfgBIFPLR2_LANE_12_MARGINING_LANE_STATUS 0x047a |
| #define cfgBIFPLR2_LANE_13_MARGINING_LANE_CNTL 0x047c |
| #define cfgBIFPLR2_LANE_13_MARGINING_LANE_STATUS 0x047e |
| #define cfgBIFPLR2_LANE_14_MARGINING_LANE_CNTL 0x0480 |
| #define cfgBIFPLR2_LANE_14_MARGINING_LANE_STATUS 0x0482 |
| #define cfgBIFPLR2_LANE_15_MARGINING_LANE_CNTL 0x0484 |
| #define cfgBIFPLR2_LANE_15_MARGINING_LANE_STATUS 0x0486 |
| #define cfgBIFPLR2_PCIE_CCIX_CAP_LIST 0x0488 |
| #define cfgBIFPLR2_PCIE_CCIX_HEADER_1 0x048c |
| #define cfgBIFPLR2_PCIE_CCIX_HEADER_2 0x0490 |
| #define cfgBIFPLR2_PCIE_CCIX_CAP 0x0492 |
| #define cfgBIFPLR2_PCIE_CCIX_ESM_REQD_CAP 0x0494 |
| #define cfgBIFPLR2_PCIE_CCIX_ESM_OPTL_CAP 0x0498 |
| #define cfgBIFPLR2_PCIE_CCIX_ESM_STATUS 0x049c |
| #define cfgBIFPLR2_PCIE_CCIX_ESM_CNTL 0x04a0 |
| #define cfgBIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x04a4 |
| #define cfgBIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x04a5 |
| #define cfgBIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x04a6 |
| #define cfgBIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x04a7 |
| #define cfgBIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x04a8 |
| #define cfgBIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x04a9 |
| #define cfgBIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x04aa |
| #define cfgBIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x04ab |
| #define cfgBIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x04ac |
| #define cfgBIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x04ad |
| #define cfgBIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x04ae |
| #define cfgBIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x04af |
| #define cfgBIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x04b0 |
| #define cfgBIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x04b1 |
| #define cfgBIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x04b2 |
| #define cfgBIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x04b3 |
| #define cfgBIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x04b4 |
| #define cfgBIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x04b5 |
| #define cfgBIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x04b6 |
| #define cfgBIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x04b7 |
| #define cfgBIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x04b8 |
| #define cfgBIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x04b9 |
| #define cfgBIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x04ba |
| #define cfgBIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x04bb |
| #define cfgBIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x04bc |
| #define cfgBIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x04bd |
| #define cfgBIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x04be |
| #define cfgBIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x04bf |
| #define cfgBIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x04c0 |
| #define cfgBIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x04c1 |
| #define cfgBIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x04c2 |
| #define cfgBIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x04c3 |
| #define cfgBIFPLR2_PCIE_CCIX_TRANS_CAP 0x04c4 |
| #define cfgBIFPLR2_PCIE_CCIX_TRANS_CNTL 0x04c8 |
| #define cfgBIFPLR2_LINK_CAP_32GT 0x0504 |
| #define cfgBIFPLR2_LINK_CNTL_32GT 0x0508 |
| #define cfgBIFPLR2_LINK_STATUS_32GT 0x050c |
| |
| |
| // addressBlock: nbio_pcie0_bifplr3_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR3_VENDOR_ID 0x0000 |
| #define cfgBIFPLR3_DEVICE_ID 0x0002 |
| #define cfgBIFPLR3_COMMAND 0x0004 |
| #define cfgBIFPLR3_STATUS 0x0006 |
| #define cfgBIFPLR3_REVISION_ID 0x0008 |
| #define cfgBIFPLR3_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR3_SUB_CLASS 0x000a |
| #define cfgBIFPLR3_BASE_CLASS 0x000b |
| #define cfgBIFPLR3_CACHE_LINE 0x000c |
| #define cfgBIFPLR3_LATENCY 0x000d |
| #define cfgBIFPLR3_HEADER 0x000e |
| #define cfgBIFPLR3_BIST 0x000f |
| #define cfgBIFPLR3_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR3_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR3_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR3_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR3_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR3_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR3_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR3_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR3_CAP_PTR 0x0034 |
| #define cfgBIFPLR3_ROM_BASE_ADDR 0x0038 |
| #define cfgBIFPLR3_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR3_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR3_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR3_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIFPLR3_ADAPTER_ID_W 0x004c |
| #define cfgBIFPLR3_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR3_PMI_CAP 0x0052 |
| #define cfgBIFPLR3_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR3_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR3_PCIE_CAP 0x005a |
| #define cfgBIFPLR3_DEVICE_CAP 0x005c |
| #define cfgBIFPLR3_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR3_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR3_LINK_CAP 0x0064 |
| #define cfgBIFPLR3_LINK_CNTL 0x0068 |
| #define cfgBIFPLR3_LINK_STATUS 0x006a |
| #define cfgBIFPLR3_SLOT_CAP 0x006c |
| #define cfgBIFPLR3_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR3_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR3_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR3_ROOT_CAP 0x0076 |
| #define cfgBIFPLR3_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR3_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR3_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR3_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR3_LINK_CAP2 0x0084 |
| #define cfgBIFPLR3_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR3_LINK_STATUS2 0x008a |
| #define cfgBIFPLR3_SLOT_CAP2 0x008c |
| #define cfgBIFPLR3_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR3_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR3_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR3_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR3_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR3_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR3_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR3_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR3_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR3_SSID_CAP 0x00c4 |
| #define cfgBIFPLR3_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR3_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR3_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR3_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR3_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR3_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR3_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR3_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR3_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR3_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR3_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR3_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR3_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR3_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR3_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR3_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR3_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR3_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR3_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR3_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR3_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR3_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR3_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR3_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR3_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR3_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR3_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR3_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR3_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR3_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR3_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR3_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR3_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR3_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR3_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR3_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR3_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR3_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR3_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR3_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR3_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR3_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR3_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR3_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR3_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR3_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR3_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR3_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR3_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR3_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR3_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR3_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR3_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR3_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR3_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR3_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR3_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR3_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR3_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR3_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR3_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR3_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR3_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR3_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR3_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR3_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR3_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR3_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR3_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR3_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR3_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR3_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR3_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR3_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR3_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR3_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR3_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR3_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR3_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR3_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR3_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR3_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR3_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR3_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR3_PCIE_ESM_CAP_7 0x03ec |
| #define cfgBIFPLR3_PCIE_DLF_ENH_CAP_LIST 0x0400 |
| #define cfgBIFPLR3_DATA_LINK_FEATURE_CAP 0x0404 |
| #define cfgBIFPLR3_DATA_LINK_FEATURE_STATUS 0x0408 |
| #define cfgBIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 |
| #define cfgBIFPLR3_LINK_CAP_16GT 0x0414 |
| #define cfgBIFPLR3_LINK_CNTL_16GT 0x0418 |
| #define cfgBIFPLR3_LINK_STATUS_16GT 0x041c |
| #define cfgBIFPLR3_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 |
| #define cfgBIFPLR3_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 |
| #define cfgBIFPLR3_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 |
| #define cfgBIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 |
| #define cfgBIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 |
| #define cfgBIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 |
| #define cfgBIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 |
| #define cfgBIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 |
| #define cfgBIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 |
| #define cfgBIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 |
| #define cfgBIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 |
| #define cfgBIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 |
| #define cfgBIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 |
| #define cfgBIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT 0x043a |
| #define cfgBIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT 0x043b |
| #define cfgBIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT 0x043c |
| #define cfgBIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT 0x043d |
| #define cfgBIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT 0x043e |
| #define cfgBIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT 0x043f |
| #define cfgBIFPLR3_PCIE_MARGINING_ENH_CAP_LIST 0x0440 |
| #define cfgBIFPLR3_MARGINING_PORT_CAP 0x0444 |
| #define cfgBIFPLR3_MARGINING_PORT_STATUS 0x0446 |
| #define cfgBIFPLR3_LANE_0_MARGINING_LANE_CNTL 0x0448 |
| #define cfgBIFPLR3_LANE_0_MARGINING_LANE_STATUS 0x044a |
| #define cfgBIFPLR3_LANE_1_MARGINING_LANE_CNTL 0x044c |
| #define cfgBIFPLR3_LANE_1_MARGINING_LANE_STATUS 0x044e |
| #define cfgBIFPLR3_LANE_2_MARGINING_LANE_CNTL 0x0450 |
| #define cfgBIFPLR3_LANE_2_MARGINING_LANE_STATUS 0x0452 |
| #define cfgBIFPLR3_LANE_3_MARGINING_LANE_CNTL 0x0454 |
| #define cfgBIFPLR3_LANE_3_MARGINING_LANE_STATUS 0x0456 |
| #define cfgBIFPLR3_LANE_4_MARGINING_LANE_CNTL 0x0458 |
| #define cfgBIFPLR3_LANE_4_MARGINING_LANE_STATUS 0x045a |
| #define cfgBIFPLR3_LANE_5_MARGINING_LANE_CNTL 0x045c |
| #define cfgBIFPLR3_LANE_5_MARGINING_LANE_STATUS 0x045e |
| #define cfgBIFPLR3_LANE_6_MARGINING_LANE_CNTL 0x0460 |
| #define cfgBIFPLR3_LANE_6_MARGINING_LANE_STATUS 0x0462 |
| #define cfgBIFPLR3_LANE_7_MARGINING_LANE_CNTL 0x0464 |
| #define cfgBIFPLR3_LANE_7_MARGINING_LANE_STATUS 0x0466 |
| #define cfgBIFPLR3_LANE_8_MARGINING_LANE_CNTL 0x0468 |
| #define cfgBIFPLR3_LANE_8_MARGINING_LANE_STATUS 0x046a |
| #define cfgBIFPLR3_LANE_9_MARGINING_LANE_CNTL 0x046c |
| #define cfgBIFPLR3_LANE_9_MARGINING_LANE_STATUS 0x046e |
| #define cfgBIFPLR3_LANE_10_MARGINING_LANE_CNTL 0x0470 |
| #define cfgBIFPLR3_LANE_10_MARGINING_LANE_STATUS 0x0472 |
| #define cfgBIFPLR3_LANE_11_MARGINING_LANE_CNTL 0x0474 |
| #define cfgBIFPLR3_LANE_11_MARGINING_LANE_STATUS 0x0476 |
| #define cfgBIFPLR3_LANE_12_MARGINING_LANE_CNTL 0x0478 |
| #define cfgBIFPLR3_LANE_12_MARGINING_LANE_STATUS 0x047a |
| #define cfgBIFPLR3_LANE_13_MARGINING_LANE_CNTL 0x047c |
| #define cfgBIFPLR3_LANE_13_MARGINING_LANE_STATUS 0x047e |
| #define cfgBIFPLR3_LANE_14_MARGINING_LANE_CNTL 0x0480 |
| #define cfgBIFPLR3_LANE_14_MARGINING_LANE_STATUS 0x0482 |
| #define cfgBIFPLR3_LANE_15_MARGINING_LANE_CNTL 0x0484 |
| #define cfgBIFPLR3_LANE_15_MARGINING_LANE_STATUS 0x0486 |
| #define cfgBIFPLR3_PCIE_CCIX_CAP_LIST 0x0488 |
| #define cfgBIFPLR3_PCIE_CCIX_HEADER_1 0x048c |
| #define cfgBIFPLR3_PCIE_CCIX_HEADER_2 0x0490 |
| #define cfgBIFPLR3_PCIE_CCIX_CAP 0x0492 |
| #define cfgBIFPLR3_PCIE_CCIX_ESM_REQD_CAP 0x0494 |
| #define cfgBIFPLR3_PCIE_CCIX_ESM_OPTL_CAP 0x0498 |
| #define cfgBIFPLR3_PCIE_CCIX_ESM_STATUS 0x049c |
| #define cfgBIFPLR3_PCIE_CCIX_ESM_CNTL 0x04a0 |
| #define cfgBIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x04a4 |
| #define cfgBIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x04a5 |
| #define cfgBIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x04a6 |
| #define cfgBIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x04a7 |
| #define cfgBIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x04a8 |
| #define cfgBIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x04a9 |
| #define cfgBIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x04aa |
| #define cfgBIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x04ab |
| #define cfgBIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x04ac |
| #define cfgBIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x04ad |
| #define cfgBIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x04ae |
| #define cfgBIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x04af |
| #define cfgBIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x04b0 |
| #define cfgBIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x04b1 |
| #define cfgBIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x04b2 |
| #define cfgBIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x04b3 |
| #define cfgBIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x04b4 |
| #define cfgBIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x04b5 |
| #define cfgBIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x04b6 |
| #define cfgBIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x04b7 |
| #define cfgBIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x04b8 |
| #define cfgBIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x04b9 |
| #define cfgBIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x04ba |
| #define cfgBIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x04bb |
| #define cfgBIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x04bc |
| #define cfgBIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x04bd |
| #define cfgBIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x04be |
| #define cfgBIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x04bf |
| #define cfgBIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x04c0 |
| #define cfgBIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x04c1 |
| #define cfgBIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x04c2 |
| #define cfgBIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x04c3 |
| #define cfgBIFPLR3_PCIE_CCIX_TRANS_CAP 0x04c4 |
| #define cfgBIFPLR3_PCIE_CCIX_TRANS_CNTL 0x04c8 |
| #define cfgBIFPLR3_LINK_CAP_32GT 0x0504 |
| #define cfgBIFPLR3_LINK_CNTL_32GT 0x0508 |
| #define cfgBIFPLR3_LINK_STATUS_32GT 0x050c |
| |
| |
| // addressBlock: nbio_pcie0_bifplr4_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR4_VENDOR_ID 0x0000 |
| #define cfgBIFPLR4_DEVICE_ID 0x0002 |
| #define cfgBIFPLR4_COMMAND 0x0004 |
| #define cfgBIFPLR4_STATUS 0x0006 |
| #define cfgBIFPLR4_REVISION_ID 0x0008 |
| #define cfgBIFPLR4_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR4_SUB_CLASS 0x000a |
| #define cfgBIFPLR4_BASE_CLASS 0x000b |
| #define cfgBIFPLR4_CACHE_LINE 0x000c |
| #define cfgBIFPLR4_LATENCY 0x000d |
| #define cfgBIFPLR4_HEADER 0x000e |
| #define cfgBIFPLR4_BIST 0x000f |
| #define cfgBIFPLR4_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR4_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR4_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR4_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR4_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR4_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR4_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR4_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR4_CAP_PTR 0x0034 |
| #define cfgBIFPLR4_ROM_BASE_ADDR 0x0038 |
| #define cfgBIFPLR4_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR4_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR4_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR4_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIFPLR4_ADAPTER_ID_W 0x004c |
| #define cfgBIFPLR4_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR4_PMI_CAP 0x0052 |
| #define cfgBIFPLR4_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR4_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR4_PCIE_CAP 0x005a |
| #define cfgBIFPLR4_DEVICE_CAP 0x005c |
| #define cfgBIFPLR4_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR4_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR4_LINK_CAP 0x0064 |
| #define cfgBIFPLR4_LINK_CNTL 0x0068 |
| #define cfgBIFPLR4_LINK_STATUS 0x006a |
| #define cfgBIFPLR4_SLOT_CAP 0x006c |
| #define cfgBIFPLR4_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR4_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR4_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR4_ROOT_CAP 0x0076 |
| #define cfgBIFPLR4_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR4_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR4_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR4_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR4_LINK_CAP2 0x0084 |
| #define cfgBIFPLR4_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR4_LINK_STATUS2 0x008a |
| #define cfgBIFPLR4_SLOT_CAP2 0x008c |
| #define cfgBIFPLR4_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR4_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR4_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR4_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR4_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR4_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR4_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR4_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR4_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR4_SSID_CAP 0x00c4 |
| #define cfgBIFPLR4_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR4_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR4_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR4_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR4_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR4_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR4_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR4_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR4_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR4_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR4_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR4_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR4_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR4_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR4_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR4_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR4_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR4_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR4_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR4_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR4_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR4_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR4_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR4_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR4_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR4_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR4_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR4_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR4_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR4_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR4_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR4_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR4_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR4_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR4_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR4_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR4_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR4_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR4_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR4_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR4_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR4_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR4_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR4_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR4_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR4_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR4_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR4_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR4_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR4_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR4_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR4_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR4_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR4_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR4_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR4_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR4_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR4_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR4_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR4_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR4_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR4_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR4_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR4_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR4_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR4_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR4_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR4_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR4_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR4_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR4_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR4_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR4_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR4_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR4_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR4_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR4_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR4_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR4_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR4_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR4_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR4_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR4_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR4_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR4_PCIE_ESM_CAP_7 0x03ec |
| #define cfgBIFPLR4_PCIE_DLF_ENH_CAP_LIST 0x0400 |
| #define cfgBIFPLR4_DATA_LINK_FEATURE_CAP 0x0404 |
| #define cfgBIFPLR4_DATA_LINK_FEATURE_STATUS 0x0408 |
| #define cfgBIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 |
| #define cfgBIFPLR4_LINK_CAP_16GT 0x0414 |
| #define cfgBIFPLR4_LINK_CNTL_16GT 0x0418 |
| #define cfgBIFPLR4_LINK_STATUS_16GT 0x041c |
| #define cfgBIFPLR4_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 |
| #define cfgBIFPLR4_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 |
| #define cfgBIFPLR4_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 |
| #define cfgBIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 |
| #define cfgBIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 |
| #define cfgBIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 |
| #define cfgBIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 |
| #define cfgBIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 |
| #define cfgBIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 |
| #define cfgBIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 |
| #define cfgBIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 |
| #define cfgBIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 |
| #define cfgBIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 |
| #define cfgBIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT 0x043a |
| #define cfgBIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT 0x043b |
| #define cfgBIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT 0x043c |
| #define cfgBIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT 0x043d |
| #define cfgBIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT 0x043e |
| #define cfgBIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT 0x043f |
| #define cfgBIFPLR4_PCIE_MARGINING_ENH_CAP_LIST 0x0440 |
| #define cfgBIFPLR4_MARGINING_PORT_CAP 0x0444 |
| #define cfgBIFPLR4_MARGINING_PORT_STATUS 0x0446 |
| #define cfgBIFPLR4_LANE_0_MARGINING_LANE_CNTL 0x0448 |
| #define cfgBIFPLR4_LANE_0_MARGINING_LANE_STATUS 0x044a |
| #define cfgBIFPLR4_LANE_1_MARGINING_LANE_CNTL 0x044c |
| #define cfgBIFPLR4_LANE_1_MARGINING_LANE_STATUS 0x044e |
| #define cfgBIFPLR4_LANE_2_MARGINING_LANE_CNTL 0x0450 |
| #define cfgBIFPLR4_LANE_2_MARGINING_LANE_STATUS 0x0452 |
| #define cfgBIFPLR4_LANE_3_MARGINING_LANE_CNTL 0x0454 |
| #define cfgBIFPLR4_LANE_3_MARGINING_LANE_STATUS 0x0456 |
| #define cfgBIFPLR4_LANE_4_MARGINING_LANE_CNTL 0x0458 |
| #define cfgBIFPLR4_LANE_4_MARGINING_LANE_STATUS 0x045a |
| #define cfgBIFPLR4_LANE_5_MARGINING_LANE_CNTL 0x045c |
| #define cfgBIFPLR4_LANE_5_MARGINING_LANE_STATUS 0x045e |
| #define cfgBIFPLR4_LANE_6_MARGINING_LANE_CNTL 0x0460 |
| #define cfgBIFPLR4_LANE_6_MARGINING_LANE_STATUS 0x0462 |
| #define cfgBIFPLR4_LANE_7_MARGINING_LANE_CNTL 0x0464 |
| #define cfgBIFPLR4_LANE_7_MARGINING_LANE_STATUS 0x0466 |
| #define cfgBIFPLR4_LANE_8_MARGINING_LANE_CNTL 0x0468 |
| #define cfgBIFPLR4_LANE_8_MARGINING_LANE_STATUS 0x046a |
| #define cfgBIFPLR4_LANE_9_MARGINING_LANE_CNTL 0x046c |
| #define cfgBIFPLR4_LANE_9_MARGINING_LANE_STATUS 0x046e |
| #define cfgBIFPLR4_LANE_10_MARGINING_LANE_CNTL 0x0470 |
| #define cfgBIFPLR4_LANE_10_MARGINING_LANE_STATUS 0x0472 |
| #define cfgBIFPLR4_LANE_11_MARGINING_LANE_CNTL 0x0474 |
| #define cfgBIFPLR4_LANE_11_MARGINING_LANE_STATUS 0x0476 |
| #define cfgBIFPLR4_LANE_12_MARGINING_LANE_CNTL 0x0478 |
| #define cfgBIFPLR4_LANE_12_MARGINING_LANE_STATUS 0x047a |
| #define cfgBIFPLR4_LANE_13_MARGINING_LANE_CNTL 0x047c |
| #define cfgBIFPLR4_LANE_13_MARGINING_LANE_STATUS 0x047e |
| #define cfgBIFPLR4_LANE_14_MARGINING_LANE_CNTL 0x0480 |
| #define cfgBIFPLR4_LANE_14_MARGINING_LANE_STATUS 0x0482 |
| #define cfgBIFPLR4_LANE_15_MARGINING_LANE_CNTL 0x0484 |
| #define cfgBIFPLR4_LANE_15_MARGINING_LANE_STATUS 0x0486 |
| #define cfgBIFPLR4_PCIE_CCIX_CAP_LIST 0x0488 |
| #define cfgBIFPLR4_PCIE_CCIX_HEADER_1 0x048c |
| #define cfgBIFPLR4_PCIE_CCIX_HEADER_2 0x0490 |
| #define cfgBIFPLR4_PCIE_CCIX_CAP 0x0492 |
| #define cfgBIFPLR4_PCIE_CCIX_ESM_REQD_CAP 0x0494 |
| #define cfgBIFPLR4_PCIE_CCIX_ESM_OPTL_CAP 0x0498 |
| #define cfgBIFPLR4_PCIE_CCIX_ESM_STATUS 0x049c |
| #define cfgBIFPLR4_PCIE_CCIX_ESM_CNTL 0x04a0 |
| #define cfgBIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x04a4 |
| #define cfgBIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x04a5 |
| #define cfgBIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x04a6 |
| #define cfgBIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x04a7 |
| #define cfgBIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x04a8 |
| #define cfgBIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x04a9 |
| #define cfgBIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x04aa |
| #define cfgBIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x04ab |
| #define cfgBIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x04ac |
| #define cfgBIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x04ad |
| #define cfgBIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x04ae |
| #define cfgBIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x04af |
| #define cfgBIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x04b0 |
| #define cfgBIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x04b1 |
| #define cfgBIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x04b2 |
| #define cfgBIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x04b3 |
| #define cfgBIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x04b4 |
| #define cfgBIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x04b5 |
| #define cfgBIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x04b6 |
| #define cfgBIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x04b7 |
| #define cfgBIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x04b8 |
| #define cfgBIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x04b9 |
| #define cfgBIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x04ba |
| #define cfgBIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x04bb |
| #define cfgBIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x04bc |
| #define cfgBIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x04bd |
| #define cfgBIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x04be |
| #define cfgBIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x04bf |
| #define cfgBIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x04c0 |
| #define cfgBIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x04c1 |
| #define cfgBIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x04c2 |
| #define cfgBIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x04c3 |
| #define cfgBIFPLR4_PCIE_CCIX_TRANS_CAP 0x04c4 |
| #define cfgBIFPLR4_PCIE_CCIX_TRANS_CNTL 0x04c8 |
| #define cfgBIFPLR4_LINK_CAP_32GT 0x0504 |
| #define cfgBIFPLR4_LINK_CNTL_32GT 0x0508 |
| #define cfgBIFPLR4_LINK_STATUS_32GT 0x050c |
| |
| |
| // addressBlock: nbio_pcie1_bifplr5_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR5_VENDOR_ID 0x0000 |
| #define cfgBIFPLR5_DEVICE_ID 0x0002 |
| #define cfgBIFPLR5_COMMAND 0x0004 |
| #define cfgBIFPLR5_STATUS 0x0006 |
| #define cfgBIFPLR5_REVISION_ID 0x0008 |
| #define cfgBIFPLR5_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR5_SUB_CLASS 0x000a |
| #define cfgBIFPLR5_BASE_CLASS 0x000b |
| #define cfgBIFPLR5_CACHE_LINE 0x000c |
| #define cfgBIFPLR5_LATENCY 0x000d |
| #define cfgBIFPLR5_HEADER 0x000e |
| #define cfgBIFPLR5_BIST 0x000f |
| #define cfgBIFPLR5_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR5_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR5_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR5_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR5_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR5_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR5_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR5_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR5_CAP_PTR 0x0034 |
| #define cfgBIFPLR5_ROM_BASE_ADDR 0x0038 |
| #define cfgBIFPLR5_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR5_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR5_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR5_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIFPLR5_ADAPTER_ID_W 0x004c |
| #define cfgBIFPLR5_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR5_PMI_CAP 0x0052 |
| #define cfgBIFPLR5_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR5_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR5_PCIE_CAP 0x005a |
| #define cfgBIFPLR5_DEVICE_CAP 0x005c |
| #define cfgBIFPLR5_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR5_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR5_LINK_CAP 0x0064 |
| #define cfgBIFPLR5_LINK_CNTL 0x0068 |
| #define cfgBIFPLR5_LINK_STATUS 0x006a |
| #define cfgBIFPLR5_SLOT_CAP 0x006c |
| #define cfgBIFPLR5_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR5_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR5_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR5_ROOT_CAP 0x0076 |
| #define cfgBIFPLR5_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR5_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR5_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR5_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR5_LINK_CAP2 0x0084 |
| #define cfgBIFPLR5_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR5_LINK_STATUS2 0x008a |
| #define cfgBIFPLR5_SLOT_CAP2 0x008c |
| #define cfgBIFPLR5_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR5_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR5_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR5_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR5_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR5_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR5_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR5_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR5_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR5_SSID_CAP 0x00c4 |
| #define cfgBIFPLR5_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR5_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR5_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR5_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR5_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR5_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR5_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR5_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR5_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR5_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR5_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR5_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR5_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR5_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR5_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR5_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR5_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR5_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR5_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR5_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR5_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR5_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR5_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR5_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR5_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR5_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR5_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR5_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR5_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR5_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR5_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR5_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR5_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR5_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR5_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR5_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR5_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR5_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR5_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR5_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR5_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR5_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR5_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR5_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR5_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR5_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR5_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR5_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR5_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR5_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR5_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR5_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR5_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR5_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR5_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR5_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR5_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR5_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR5_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR5_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR5_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR5_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR5_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR5_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR5_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR5_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR5_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR5_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR5_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR5_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR5_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR5_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR5_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR5_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR5_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR5_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR5_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR5_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR5_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR5_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR5_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR5_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR5_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR5_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR5_PCIE_ESM_CAP_7 0x03ec |
| #define cfgBIFPLR5_PCIE_DLF_ENH_CAP_LIST 0x0400 |
| #define cfgBIFPLR5_DATA_LINK_FEATURE_CAP 0x0404 |
| #define cfgBIFPLR5_DATA_LINK_FEATURE_STATUS 0x0408 |
| #define cfgBIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 |
| #define cfgBIFPLR5_LINK_CAP_16GT 0x0414 |
| #define cfgBIFPLR5_LINK_CNTL_16GT 0x0418 |
| #define cfgBIFPLR5_LINK_STATUS_16GT 0x041c |
| #define cfgBIFPLR5_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 |
| #define cfgBIFPLR5_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 |
| #define cfgBIFPLR5_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 |
| #define cfgBIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 |
| #define cfgBIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 |
| #define cfgBIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 |
| #define cfgBIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 |
| #define cfgBIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 |
| #define cfgBIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 |
| #define cfgBIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 |
| #define cfgBIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 |
| #define cfgBIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 |
| #define cfgBIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 |
| #define cfgBIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT 0x043a |
| #define cfgBIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT 0x043b |
| #define cfgBIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT 0x043c |
| #define cfgBIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT 0x043d |
| #define cfgBIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT 0x043e |
| #define cfgBIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT 0x043f |
| #define cfgBIFPLR5_PCIE_MARGINING_ENH_CAP_LIST 0x0440 |
| #define cfgBIFPLR5_MARGINING_PORT_CAP 0x0444 |
| #define cfgBIFPLR5_MARGINING_PORT_STATUS 0x0446 |
| #define cfgBIFPLR5_LANE_0_MARGINING_LANE_CNTL 0x0448 |
| #define cfgBIFPLR5_LANE_0_MARGINING_LANE_STATUS 0x044a |
| #define cfgBIFPLR5_LANE_1_MARGINING_LANE_CNTL 0x044c |
| #define cfgBIFPLR5_LANE_1_MARGINING_LANE_STATUS 0x044e |
| #define cfgBIFPLR5_LANE_2_MARGINING_LANE_CNTL 0x0450 |
| #define cfgBIFPLR5_LANE_2_MARGINING_LANE_STATUS 0x0452 |
| #define cfgBIFPLR5_LANE_3_MARGINING_LANE_CNTL 0x0454 |
| #define cfgBIFPLR5_LANE_3_MARGINING_LANE_STATUS 0x0456 |
| #define cfgBIFPLR5_LANE_4_MARGINING_LANE_CNTL 0x0458 |
| #define cfgBIFPLR5_LANE_4_MARGINING_LANE_STATUS 0x045a |
| #define cfgBIFPLR5_LANE_5_MARGINING_LANE_CNTL 0x045c |
| #define cfgBIFPLR5_LANE_5_MARGINING_LANE_STATUS 0x045e |
| #define cfgBIFPLR5_LANE_6_MARGINING_LANE_CNTL 0x0460 |
| #define cfgBIFPLR5_LANE_6_MARGINING_LANE_STATUS 0x0462 |
| #define cfgBIFPLR5_LANE_7_MARGINING_LANE_CNTL 0x0464 |
| #define cfgBIFPLR5_LANE_7_MARGINING_LANE_STATUS 0x0466 |
| #define cfgBIFPLR5_LANE_8_MARGINING_LANE_CNTL 0x0468 |
| #define cfgBIFPLR5_LANE_8_MARGINING_LANE_STATUS 0x046a |
| #define cfgBIFPLR5_LANE_9_MARGINING_LANE_CNTL 0x046c |
| #define cfgBIFPLR5_LANE_9_MARGINING_LANE_STATUS 0x046e |
| #define cfgBIFPLR5_LANE_10_MARGINING_LANE_CNTL 0x0470 |
| #define cfgBIFPLR5_LANE_10_MARGINING_LANE_STATUS 0x0472 |
| #define cfgBIFPLR5_LANE_11_MARGINING_LANE_CNTL 0x0474 |
| #define cfgBIFPLR5_LANE_11_MARGINING_LANE_STATUS 0x0476 |
| #define cfgBIFPLR5_LANE_12_MARGINING_LANE_CNTL 0x0478 |
| #define cfgBIFPLR5_LANE_12_MARGINING_LANE_STATUS 0x047a |
| #define cfgBIFPLR5_LANE_13_MARGINING_LANE_CNTL 0x047c |
| #define cfgBIFPLR5_LANE_13_MARGINING_LANE_STATUS 0x047e |
| #define cfgBIFPLR5_LANE_14_MARGINING_LANE_CNTL 0x0480 |
| #define cfgBIFPLR5_LANE_14_MARGINING_LANE_STATUS 0x0482 |
| #define cfgBIFPLR5_LANE_15_MARGINING_LANE_CNTL 0x0484 |
| #define cfgBIFPLR5_LANE_15_MARGINING_LANE_STATUS 0x0486 |
| #define cfgBIFPLR5_PCIE_CCIX_CAP_LIST 0x0488 |
| #define cfgBIFPLR5_PCIE_CCIX_HEADER_1 0x048c |
| #define cfgBIFPLR5_PCIE_CCIX_HEADER_2 0x0490 |
| #define cfgBIFPLR5_PCIE_CCIX_CAP 0x0492 |
| #define cfgBIFPLR5_PCIE_CCIX_ESM_REQD_CAP 0x0494 |
| #define cfgBIFPLR5_PCIE_CCIX_ESM_OPTL_CAP 0x0498 |
| #define cfgBIFPLR5_PCIE_CCIX_ESM_STATUS 0x049c |
| #define cfgBIFPLR5_PCIE_CCIX_ESM_CNTL 0x04a0 |
| #define cfgBIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x04a4 |
| #define cfgBIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x04a5 |
| #define cfgBIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x04a6 |
| #define cfgBIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x04a7 |
| #define cfgBIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x04a8 |
| #define cfgBIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x04a9 |
| #define cfgBIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x04aa |
| #define cfgBIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x04ab |
| #define cfgBIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x04ac |
| #define cfgBIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x04ad |
| #define cfgBIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x04ae |
| #define cfgBIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x04af |
| #define cfgBIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x04b0 |
| #define cfgBIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x04b1 |
| #define cfgBIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x04b2 |
| #define cfgBIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x04b3 |
| #define cfgBIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x04b4 |
| #define cfgBIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x04b5 |
| #define cfgBIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x04b6 |
| #define cfgBIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x04b7 |
| #define cfgBIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x04b8 |
| #define cfgBIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x04b9 |
| #define cfgBIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x04ba |
| #define cfgBIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x04bb |
| #define cfgBIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x04bc |
| #define cfgBIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x04bd |
| #define cfgBIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x04be |
| #define cfgBIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x04bf |
| #define cfgBIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x04c0 |
| #define cfgBIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x04c1 |
| #define cfgBIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x04c2 |
| #define cfgBIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x04c3 |
| #define cfgBIFPLR5_PCIE_CCIX_TRANS_CAP 0x04c4 |
| #define cfgBIFPLR5_PCIE_CCIX_TRANS_CNTL 0x04c8 |
| #define cfgBIFPLR5_LINK_CAP_32GT 0x0504 |
| #define cfgBIFPLR5_LINK_CNTL_32GT 0x0508 |
| #define cfgBIFPLR5_LINK_STATUS_32GT 0x050c |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1 |
| // base address: 0x0 |
| #define regBIF_BX_PF0_MM_INDEX 0x0000 |
| #define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0 |
| #define regBIF_BX_PF0_MM_DATA 0x0001 |
| #define regBIF_BX_PF0_MM_DATA_BASE_IDX 0 |
| #define regBIF_BX_PF0_MM_INDEX_HI 0x0006 |
| #define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0 |
| #define regBIF_BX_PF0_RSMU_INDEX 0x0000 |
| #define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1 |
| #define regBIF_BX_PF0_RSMU_DATA 0x0001 |
| #define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_SYSDEC:1 |
| // base address: 0x0 |
| #define regBIF_BX0_PCIE_INDEX 0x000c |
| #define regBIF_BX0_PCIE_INDEX_BASE_IDX 0 |
| #define regBIF_BX0_PCIE_DATA 0x000d |
| #define regBIF_BX0_PCIE_DATA_BASE_IDX 0 |
| #define regBIF_BX0_PCIE_INDEX2 0x000e |
| #define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0 |
| #define regBIF_BX0_PCIE_DATA2 0x000f |
| #define regBIF_BX0_PCIE_DATA2_BASE_IDX 0 |
| #define regBIF_BX0_SBIOS_SCRATCH_0 0x0034 |
| #define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1 |
| #define regBIF_BX0_SBIOS_SCRATCH_1 0x0035 |
| #define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1 |
| #define regBIF_BX0_SBIOS_SCRATCH_2 0x0036 |
| #define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1 |
| #define regBIF_BX0_SBIOS_SCRATCH_3 0x0037 |
| #define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_0 0x0038 |
| #define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_1 0x0039 |
| #define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_2 0x003a |
| #define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_3 0x003b |
| #define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_4 0x003c |
| #define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_5 0x003d |
| #define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_6 0x003e |
| #define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_7 0x003f |
| #define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_8 0x0040 |
| #define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_9 0x0041 |
| #define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_10 0x0042 |
| #define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_11 0x0043 |
| #define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_12 0x0044 |
| #define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_13 0x0045 |
| #define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_14 0x0046 |
| #define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1 |
| #define regBIF_BX0_BIOS_SCRATCH_15 0x0047 |
| #define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1 |
| #define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c |
| #define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1 |
| #define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d |
| #define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1 |
| #define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e |
| #define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b |
| #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c |
| #define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e |
| #define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 |
| #define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f |
| #define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
| // base address: 0x0 |
| #define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000 |
| #define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001 |
| #define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_BIF_STRAP2 0x0002 |
| #define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_BIF_STRAP3 0x0003 |
| #define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_BIF_STRAP4 0x0004 |
| #define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_BIF_STRAP5 0x0005 |
| #define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_BIF_STRAP6 0x0006 |
| #define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x0007 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x0008 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x0009 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x000a |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x000b |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x000c |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x000d |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x000e |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x000f |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x0010 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x0011 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x0012 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x0013 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x0014 |
| #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x0015 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x0016 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x0017 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x0018 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x0019 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x001a |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x001b |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x001c |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x001d |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x001e |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x001f |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0020 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0022 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x0023 |
| #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x0024 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x002f |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0030 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x0031 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x0032 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x0033 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x0034 |
| #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1:1 |
| // base address: 0x0 |
| #define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x0036 |
| #define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x0038 |
| #define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x0039 |
| #define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x003a |
| #define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x003b |
| #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x003c |
| #define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x003d |
| #define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x003f |
| #define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x0040 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x0040 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x0040 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x0040 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x0041 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x0041 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x0041 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x0041 |
| #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x0042 |
| #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x0043 |
| #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x0045 |
| #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0046 |
| #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x0046 |
| #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0046 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0047 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0047 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0047 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0047 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0048 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0048 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0048 |
| #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x0048 |
| #define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x0049 |
| #define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x004b |
| #define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x004c |
| #define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x004d |
| #define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x004e |
| #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2 |
| #define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x004f |
| #define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1:1 |
| // base address: 0x0 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0050 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0051 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x0053 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x0054 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x0055 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x0056 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x0057 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0058 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0059 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2 |
| #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x005a |
| #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1:1 |
| // base address: 0x0 |
| #define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x005c |
| #define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2 |
| #define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x005d |
| #define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2 |
| #define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x005e |
| #define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2 |
| #define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x005f |
| #define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2 |
| #define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0060 |
| #define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2 |
| #define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0061 |
| #define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1 |
| // base address: 0x0 |
| #define regRCC_DEV0_EPF0_0_RCC_ERR_LOG 0x0085 |
| #define regRCC_DEV0_EPF0_0_RCC_ERR_LOG_BASE_IDX 2 |
| #define regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN 0x00c0 |
| #define regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_BASE_IDX 2 |
| #define regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE 0x00c3 |
| #define regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 |
| #define regRCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED 0x00c4 |
| #define regRCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_BASE_IDX 2 |
| #define regRCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 |
| #define regRCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1:1 |
| // base address: 0x0 |
| #define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086 |
| #define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087 |
| #define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_RESET_EN 0x0088 |
| #define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089 |
| #define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a |
| #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b |
| #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c |
| #define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d |
| #define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e |
| #define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f |
| #define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f |
| #define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be |
| #define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf |
| #define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1 |
| #define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2 |
| #define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6 |
| #define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7 |
| #define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8 |
| #define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9 |
| #define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca |
| #define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb |
| #define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc |
| #define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd |
| #define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce |
| #define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf |
| #define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0 |
| #define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1 |
| #define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2 |
| #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3 |
| #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4 |
| #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5 |
| #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6 |
| #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7 |
| #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8 |
| #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9 |
| #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da |
| #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db |
| #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd |
| #define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de |
| #define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df |
| #define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0 |
| #define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2 |
| #define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1 |
| #define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_BIFDEC1:1 |
| // base address: 0x0 |
| #define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2 |
| #define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2 |
| #define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4 |
| #define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2 |
| #define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6 |
| #define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BUS_CNTL 0x00e7 |
| #define regBIF_BX0_BUS_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BIF_SCRATCH0 0x00e8 |
| #define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2 |
| #define regBIF_BX0_BIF_SCRATCH1 0x00e9 |
| #define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2 |
| #define regBIF_BX0_BX_RESET_EN 0x00ed |
| #define regBIF_BX0_BX_RESET_EN_BASE_IDX 2 |
| #define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee |
| #define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BX_RESET_CNTL 0x00f0 |
| #define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_INTERRUPT_CNTL 0x00f1 |
| #define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_INTERRUPT_CNTL2 0x00f2 |
| #define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2 |
| #define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8 |
| #define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb |
| #define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2 |
| #define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd |
| #define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe |
| #define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BIF_FB_EN 0x0100 |
| #define regBIF_BX0_BIF_FB_EN_BASE_IDX 2 |
| #define regBIF_BX0_BIF_INTR_CNTL 0x0101 |
| #define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109 |
| #define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2 |
| #define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a |
| #define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 |
| #define regBIF_BX0_BACO_CNTL 0x010b |
| #define regBIF_BX0_BACO_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BIF_BACO_EXIT_TIME0 0x010c |
| #define regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX 2 |
| #define regBIF_BX0_BIF_BACO_EXIT_TIMER1 0x010d |
| #define regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX 2 |
| #define regBIF_BX0_BIF_BACO_EXIT_TIMER2 0x010e |
| #define regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX 2 |
| #define regBIF_BX0_BIF_BACO_EXIT_TIMER3 0x010f |
| #define regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX 2 |
| #define regBIF_BX0_BIF_BACO_EXIT_TIMER4 0x0110 |
| #define regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX 2 |
| #define regBIF_BX0_MEM_TYPE_CNTL 0x0111 |
| #define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL 0x0113 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_0 0x0114 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_1 0x0115 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_2 0x0116 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_3 0x0117 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_4 0x0118 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_5 0x0119 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_6 0x011a |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_7 0x011b |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_8 0x011c |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_9 0x011d |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_10 0x011e |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_11 0x011f |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_12 0x0120 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_13 0x0121 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_14 0x0122 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX 2 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_15 0x0123 |
| #define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX 2 |
| #define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d |
| #define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e |
| #define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BIF_RB_CNTL 0x012f |
| #define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BIF_RB_BASE 0x0130 |
| #define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2 |
| #define regBIF_BX0_BIF_RB_RPTR 0x0131 |
| #define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2 |
| #define regBIF_BX0_BIF_RB_WPTR 0x0132 |
| #define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2 |
| #define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133 |
| #define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2 |
| #define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134 |
| #define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2 |
| #define regBIF_BX0_MAILBOX_INDEX 0x0135 |
| #define regBIF_BX0_MAILBOX_INDEX_BASE_IDX 2 |
| #define regBIF_BX0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145 |
| #define regBIF_BX0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2 |
| #define regBIF_BX0_BIF_PERSTB_PAD_CNTL 0x0148 |
| #define regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BIF_PX_EN_PAD_CNTL 0x0149 |
| #define regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL 0x014a |
| #define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BIF_CLKREQB_PAD_CNTL 0x014b |
| #define regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX 2 |
| #define regBIF_BX0_BIF_PWRBRK_PAD_CNTL 0x014c |
| #define regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1:1 |
| // base address: 0x0 |
| #define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb |
| #define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 |
| #define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec |
| #define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 |
| #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 |
| #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 |
| #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 |
| #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 |
| #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 |
| #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 |
| #define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 |
| #define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 |
| #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 |
| #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 |
| #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 |
| #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 |
| #define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa |
| #define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 |
| #define regBIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ 0x0104 |
| #define regBIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ_BASE_IDX 2 |
| #define regBIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ 0x0105 |
| #define regBIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ_BASE_IDX 2 |
| #define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 |
| #define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 |
| #define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 |
| #define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 |
| #define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 |
| #define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 |
| #define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 |
| #define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d |
| #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 |
| #define regBIF_BX_PF0_MAILBOX_CONTROL 0x013e |
| #define regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2 |
| #define regBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f |
| #define regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2 |
| #define regBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140 |
| #define regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 |
| // base address: 0x0 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO 0x0400 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI 0x0401 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA 0x0402 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL 0x0403 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO 0x0404 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI 0x0405 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA 0x0406 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL 0x0407 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO 0x0408 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI 0x0409 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA 0x040a |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL 0x040b |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO 0x040c |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI 0x040d |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA 0x040e |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL 0x040f |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_PBA 0x0800 |
| #define regRCC_DEV0_EPF0_0_GFXMSIX_PBA_BASE_IDX 3 |
| |
| |
| // addressBlock: nbio_nbif0_gdc_GDCDEC |
| // base address: 0x1400000 |
| #define regGDC0_NGDC_SDP_PORT_CTRL 0x4f0ae2 |
| #define regGDC0_NGDC_SDP_PORT_CTRL_BASE_IDX 3 |
| #define regGDC0_NGDC_MGCG_CTRL 0x4f0aea |
| #define regGDC0_NGDC_MGCG_CTRL_BASE_IDX 3 |
| #define regGDC0_NGDC_RESERVED_0 0x4f0aeb |
| #define regGDC0_NGDC_RESERVED_0_BASE_IDX 3 |
| #define regGDC0_NGDC_RESERVED_1 0x4f0aec |
| #define regGDC0_NGDC_RESERVED_1_BASE_IDX 3 |
| #define regGDC0_NGDC_SDP_PORT_CTRL_SOCCLK 0x4f0aed |
| #define regGDC0_NGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 3 |
| #define regGDC0_NGDC_SDP_PORT_CTRL1_SOCCLK 0x4f0aee |
| #define regGDC0_NGDC_SDP_PORT_CTRL1_SOCCLK_BASE_IDX 3 |
| #define regGDC0_NBIF_GFX_DOORBELL_STATUS 0x4f0aef |
| #define regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3 |
| #define regGDC0_BIF_SDMA0_DOORBELL_RANGE 0x4f0af0 |
| #define regGDC0_BIF_SDMA0_DOORBELL_RANGE_BASE_IDX 3 |
| #define regGDC0_BIF_SDMA1_DOORBELL_RANGE 0x4f0af1 |
| #define regGDC0_BIF_SDMA1_DOORBELL_RANGE_BASE_IDX 3 |
| #define regGDC0_BIF_IH_DOORBELL_RANGE 0x4f0af2 |
| #define regGDC0_BIF_IH_DOORBELL_RANGE_BASE_IDX 3 |
| #define regGDC0_BIF_VCN0_DOORBELL_RANGE 0x4f0af3 |
| #define regGDC0_BIF_VCN0_DOORBELL_RANGE_BASE_IDX 3 |
| #define regGDC0_BIF_RLC_DOORBELL_RANGE 0x4f0af5 |
| #define regGDC0_BIF_RLC_DOORBELL_RANGE_BASE_IDX 3 |
| #define regGDC0_BIF_CSDMA_DOORBELL_RANGE 0x4f0afb |
| #define regGDC0_BIF_CSDMA_DOORBELL_RANGE_BASE_IDX 3 |
| #define regGDC0_ATDMA_MISC_CNTL 0x4f0afd |
| #define regGDC0_ATDMA_MISC_CNTL_BASE_IDX 3 |
| #define regGDC0_BIF_DOORBELL_FENCE_CNTL 0x4f0afe |
| #define regGDC0_BIF_DOORBELL_FENCE_CNTL_BASE_IDX 3 |
| #define regGDC0_S2A_MISC_CNTL 0x4f0aff |
| #define regGDC0_S2A_MISC_CNTL_BASE_IDX 3 |
| #define regGDC0_NGDC_PG_MISC_CTRL 0x4f0b18 |
| #define regGDC0_NGDC_PG_MISC_CTRL_BASE_IDX 3 |
| #define regGDC0_NGDC_PGMST_CTRL 0x4f0b19 |
| #define regGDC0_NGDC_PGMST_CTRL_BASE_IDX 3 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp |
| // base address: 0x10100000 |
| #define regBIF_CFG_DEV0_RC0_VENDOR_ID 0x0000 |
| #define regBIF_CFG_DEV0_RC0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_ID 0x0000 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_COMMAND 0x0001 |
| #define regBIF_CFG_DEV0_RC0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_STATUS 0x0001 |
| #define regBIF_CFG_DEV0_RC0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_REVISION_ID 0x0002 |
| #define regBIF_CFG_DEV0_RC0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PROG_INTERFACE 0x0002 |
| #define regBIF_CFG_DEV0_RC0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_SUB_CLASS 0x0002 |
| #define regBIF_CFG_DEV0_RC0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_BASE_CLASS 0x0002 |
| #define regBIF_CFG_DEV0_RC0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_CACHE_LINE 0x0003 |
| #define regBIF_CFG_DEV0_RC0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LATENCY 0x0003 |
| #define regBIF_CFG_DEV0_RC0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_HEADER 0x0003 |
| #define regBIF_CFG_DEV0_RC0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_BIST 0x0003 |
| #define regBIF_CFG_DEV0_RC0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_BASE_ADDR_1 0x0004 |
| #define regBIF_CFG_DEV0_RC0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_BASE_ADDR_2 0x0005 |
| #define regBIF_CFG_DEV0_RC0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0x0006 |
| #define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0x0007 |
| #define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0x0007 |
| #define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0x0008 |
| #define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0x0009 |
| #define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0x000a |
| #define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0x000b |
| #define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0x000c |
| #define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_CAP_PTR 0x000d |
| #define regBIF_CFG_DEV0_RC0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR 0x000e |
| #define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0x000f |
| #define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0x000f |
| #define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL 0x000f |
| #define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL 0x0010 |
| #define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0x0014 |
| #define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PMI_CAP 0x0014 |
| #define regBIF_CFG_DEV0_RC0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0x0015 |
| #define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0x0016 |
| #define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_CAP 0x0016 |
| #define regBIF_CFG_DEV0_RC0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_CAP 0x0017 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_CNTL 0x0018 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_STATUS 0x0018 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LINK_CAP 0x0019 |
| #define regBIF_CFG_DEV0_RC0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LINK_CNTL 0x001a |
| #define regBIF_CFG_DEV0_RC0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LINK_STATUS 0x001a |
| #define regBIF_CFG_DEV0_RC0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_SLOT_CAP 0x001b |
| #define regBIF_CFG_DEV0_RC0_SLOT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_SLOT_CNTL 0x001c |
| #define regBIF_CFG_DEV0_RC0_SLOT_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_SLOT_STATUS 0x001c |
| #define regBIF_CFG_DEV0_RC0_SLOT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_ROOT_CNTL 0x001d |
| #define regBIF_CFG_DEV0_RC0_ROOT_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_ROOT_CAP 0x001d |
| #define regBIF_CFG_DEV0_RC0_ROOT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_ROOT_STATUS 0x001e |
| #define regBIF_CFG_DEV0_RC0_ROOT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_CAP2 0x001f |
| #define regBIF_CFG_DEV0_RC0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0x0020 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0x0020 |
| #define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LINK_CAP2 0x0021 |
| #define regBIF_CFG_DEV0_RC0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LINK_CNTL2 0x0022 |
| #define regBIF_CFG_DEV0_RC0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LINK_STATUS2 0x0022 |
| #define regBIF_CFG_DEV0_RC0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_SLOT_CAP2 0x0023 |
| #define regBIF_CFG_DEV0_RC0_SLOT_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_SLOT_CNTL2 0x0024 |
| #define regBIF_CFG_DEV0_RC0_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_SLOT_STATUS2 0x0024 |
| #define regBIF_CFG_DEV0_RC0_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0x0028 |
| #define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0x0028 |
| #define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0x0029 |
| #define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0x002a |
| #define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0x002a |
| #define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA 0x002a |
| #define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0x002b |
| #define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 0x002b |
| #define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0x0030 |
| #define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_SSID_CAP 0x0031 |
| #define regBIF_CFG_DEV0_RC0_SSID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST 0x0032 |
| #define regBIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MSI_MAP_CAP 0x0032 |
| #define regBIF_CFG_DEV0_RC0_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0040 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0041 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0x0042 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0x0043 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0x0044 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0x0045 |
| #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0x0046 |
| #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0x0047 |
| #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0x0047 |
| #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0x0048 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0x0049 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0x004a |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0x004b |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0x004c |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0x004d |
| #define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0050 |
| #define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0051 |
| #define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0052 |
| #define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0054 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0x0055 |
| #define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0x0056 |
| #define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0x0057 |
| #define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0x0058 |
| #define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0x0059 |
| #define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0x005a |
| #define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0x005b |
| #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0x005c |
| #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0x005d |
| #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0x005e |
| #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD 0x005f |
| #define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS 0x0060 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID 0x0061 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0x0062 |
| #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0x0063 |
| #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0x0064 |
| #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0x0065 |
| #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x009c |
| #define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0x009d |
| #define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0x009e |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x009f |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x009f |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x00a0 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x00a0 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x00a1 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x00a1 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x00a2 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x00a2 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x00a3 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x00a3 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x00a4 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x00a4 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x00a5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x00a5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x00a6 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x00a6 |
| #define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0x00a8 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0x00a9 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0x00a9 |
| #define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST 0x0100 |
| #define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP 0x0101 |
| #define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS 0x0102 |
| #define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0104 |
| #define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT 0x0105 |
| #define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT 0x0106 |
| #define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT 0x0107 |
| #define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0108 |
| #define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0109 |
| #define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x010a |
| #define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0x010c |
| #define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0x010c |
| #define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0x010c |
| #define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0x010c |
| #define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0x010d |
| #define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0x010d |
| #define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0x010d |
| #define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0x010d |
| #define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0x010e |
| #define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0x010e |
| #define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0x010e |
| #define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0x010e |
| #define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0x010f |
| #define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0x010f |
| #define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0x010f |
| #define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0x010f |
| #define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST 0x0114 |
| #define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP 0x0115 |
| #define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS 0x0115 |
| #define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL 0x0116 |
| #define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS 0x0116 |
| #define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL 0x0117 |
| #define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS 0x0117 |
| #define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL 0x0118 |
| #define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS 0x0118 |
| #define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL 0x0119 |
| #define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS 0x0119 |
| #define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL 0x011a |
| #define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS 0x011a |
| #define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL 0x011b |
| #define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS 0x011b |
| #define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL 0x011c |
| #define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS 0x011c |
| #define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL 0x011d |
| #define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS 0x011d |
| #define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL 0x011e |
| #define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS 0x011e |
| #define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL 0x011f |
| #define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS 0x011f |
| #define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL 0x0120 |
| #define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS 0x0120 |
| #define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL 0x0121 |
| #define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS 0x0121 |
| #define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL 0x0122 |
| #define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS 0x0122 |
| #define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL 0x0123 |
| #define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS 0x0123 |
| #define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL 0x0124 |
| #define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS 0x0124 |
| #define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL 0x0125 |
| #define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS 0x0125 |
| #define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp |
| // base address: 0x10101000 |
| #define regBIF_CFG_DEV1_RC0_VENDOR_ID 0x0400 |
| #define regBIF_CFG_DEV1_RC0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_ID 0x0400 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_COMMAND 0x0401 |
| #define regBIF_CFG_DEV1_RC0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_STATUS 0x0401 |
| #define regBIF_CFG_DEV1_RC0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_REVISION_ID 0x0402 |
| #define regBIF_CFG_DEV1_RC0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PROG_INTERFACE 0x0402 |
| #define regBIF_CFG_DEV1_RC0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_SUB_CLASS 0x0402 |
| #define regBIF_CFG_DEV1_RC0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_BASE_CLASS 0x0402 |
| #define regBIF_CFG_DEV1_RC0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_CACHE_LINE 0x0403 |
| #define regBIF_CFG_DEV1_RC0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LATENCY 0x0403 |
| #define regBIF_CFG_DEV1_RC0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_HEADER 0x0403 |
| #define regBIF_CFG_DEV1_RC0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_BIST 0x0403 |
| #define regBIF_CFG_DEV1_RC0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_BASE_ADDR_1 0x0404 |
| #define regBIF_CFG_DEV1_RC0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_BASE_ADDR_2 0x0405 |
| #define regBIF_CFG_DEV1_RC0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY 0x0406 |
| #define regBIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_IO_BASE_LIMIT 0x0407 |
| #define regBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_SECONDARY_STATUS 0x0407 |
| #define regBIF_CFG_DEV1_RC0_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MEM_BASE_LIMIT 0x0408 |
| #define regBIF_CFG_DEV1_RC0_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PREF_BASE_LIMIT 0x0409 |
| #define regBIF_CFG_DEV1_RC0_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PREF_BASE_UPPER 0x040a |
| #define regBIF_CFG_DEV1_RC0_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER 0x040b |
| #define regBIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI 0x040c |
| #define regBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_CAP_PTR 0x040d |
| #define regBIF_CFG_DEV1_RC0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_ROM_BASE_ADDR 0x040e |
| #define regBIF_CFG_DEV1_RC0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_INTERRUPT_LINE 0x040f |
| #define regBIF_CFG_DEV1_RC0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_INTERRUPT_PIN 0x040f |
| #define regBIF_CFG_DEV1_RC0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL 0x040f |
| #define regBIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL 0x0410 |
| #define regBIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PMI_CAP_LIST 0x0414 |
| #define regBIF_CFG_DEV1_RC0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PMI_CAP 0x0414 |
| #define regBIF_CFG_DEV1_RC0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PMI_STATUS_CNTL 0x0415 |
| #define regBIF_CFG_DEV1_RC0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_CAP_LIST 0x0416 |
| #define regBIF_CFG_DEV1_RC0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_CAP 0x0416 |
| #define regBIF_CFG_DEV1_RC0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_CAP 0x0417 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_CNTL 0x0418 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_STATUS 0x0418 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LINK_CAP 0x0419 |
| #define regBIF_CFG_DEV1_RC0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LINK_CNTL 0x041a |
| #define regBIF_CFG_DEV1_RC0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LINK_STATUS 0x041a |
| #define regBIF_CFG_DEV1_RC0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_SLOT_CAP 0x041b |
| #define regBIF_CFG_DEV1_RC0_SLOT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_SLOT_CNTL 0x041c |
| #define regBIF_CFG_DEV1_RC0_SLOT_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_SLOT_STATUS 0x041c |
| #define regBIF_CFG_DEV1_RC0_SLOT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_ROOT_CNTL 0x041d |
| #define regBIF_CFG_DEV1_RC0_ROOT_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_ROOT_CAP 0x041d |
| #define regBIF_CFG_DEV1_RC0_ROOT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_ROOT_STATUS 0x041e |
| #define regBIF_CFG_DEV1_RC0_ROOT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_CAP2 0x041f |
| #define regBIF_CFG_DEV1_RC0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_CNTL2 0x0420 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_STATUS2 0x0420 |
| #define regBIF_CFG_DEV1_RC0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LINK_CAP2 0x0421 |
| #define regBIF_CFG_DEV1_RC0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LINK_CNTL2 0x0422 |
| #define regBIF_CFG_DEV1_RC0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LINK_STATUS2 0x0422 |
| #define regBIF_CFG_DEV1_RC0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_SLOT_CAP2 0x0423 |
| #define regBIF_CFG_DEV1_RC0_SLOT_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_SLOT_CNTL2 0x0424 |
| #define regBIF_CFG_DEV1_RC0_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_SLOT_STATUS2 0x0424 |
| #define regBIF_CFG_DEV1_RC0_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MSI_CAP_LIST 0x0428 |
| #define regBIF_CFG_DEV1_RC0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MSI_MSG_CNTL 0x0428 |
| #define regBIF_CFG_DEV1_RC0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO 0x0429 |
| #define regBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI 0x042a |
| #define regBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MSI_MSG_DATA 0x042a |
| #define regBIF_CFG_DEV1_RC0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA 0x042a |
| #define regBIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MSI_MSG_DATA_64 0x042b |
| #define regBIF_CFG_DEV1_RC0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64 0x042b |
| #define regBIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_SSID_CAP_LIST 0x0430 |
| #define regBIF_CFG_DEV1_RC0_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_SSID_CAP 0x0431 |
| #define regBIF_CFG_DEV1_RC0_SSID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST 0x0432 |
| #define regBIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MSI_MAP_CAP 0x0432 |
| #define regBIF_CFG_DEV1_RC0_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0440 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0441 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1 0x0442 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2 0x0443 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST 0x0444 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1 0x0445 |
| #define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2 0x0446 |
| #define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL 0x0447 |
| #define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS 0x0447 |
| #define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP 0x0448 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL 0x0449 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS 0x044a |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP 0x044b |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL 0x044c |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS 0x044d |
| #define regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0450 |
| #define regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0451 |
| #define regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0452 |
| #define regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0454 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS 0x0455 |
| #define regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK 0x0456 |
| #define regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY 0x0457 |
| #define regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS 0x0458 |
| #define regBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK 0x0459 |
| #define regBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL 0x045a |
| #define regBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG0 0x045b |
| #define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG1 0x045c |
| #define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG2 0x045d |
| #define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG3 0x045e |
| #define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD 0x045f |
| #define regBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS 0x0460 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID 0x0461 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0 0x0462 |
| #define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1 0x0463 |
| #define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2 0x0464 |
| #define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3 0x0465 |
| #define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x049c |
| #define regBIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3 0x049d |
| #define regBIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS 0x049e |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x049f |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x049f |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x04a0 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x04a0 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x04a1 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x04a1 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x04a2 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x04a2 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x04a3 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x04a3 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x04a4 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x04a4 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x04a5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x04a5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x04a6 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x04a6 |
| #define regBIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST 0x04a8 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ACS_CAP 0x04a9 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ACS_CNTL 0x04a9 |
| #define regBIF_CFG_DEV1_RC0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST 0x0500 |
| #define regBIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP 0x0501 |
| #define regBIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS 0x0502 |
| #define regBIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0504 |
| #define regBIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LINK_CAP_16GT 0x0505 |
| #define regBIF_CFG_DEV1_RC0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LINK_CNTL_16GT 0x0506 |
| #define regBIF_CFG_DEV1_RC0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LINK_STATUS_16GT 0x0507 |
| #define regBIF_CFG_DEV1_RC0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0508 |
| #define regBIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0509 |
| #define regBIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x050a |
| #define regBIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0x050c |
| #define regBIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0x050c |
| #define regBIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0x050c |
| #define regBIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0x050c |
| #define regBIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0x050d |
| #define regBIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0x050d |
| #define regBIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0x050d |
| #define regBIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0x050d |
| #define regBIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0x050e |
| #define regBIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0x050e |
| #define regBIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0x050e |
| #define regBIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0x050e |
| #define regBIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0x050f |
| #define regBIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0x050f |
| #define regBIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0x050f |
| #define regBIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0x050f |
| #define regBIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST 0x0514 |
| #define regBIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MARGINING_PORT_CAP 0x0515 |
| #define regBIF_CFG_DEV1_RC0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS 0x0515 |
| #define regBIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL 0x0516 |
| #define regBIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS 0x0516 |
| #define regBIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL 0x0517 |
| #define regBIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS 0x0517 |
| #define regBIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL 0x0518 |
| #define regBIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS 0x0518 |
| #define regBIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL 0x0519 |
| #define regBIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS 0x0519 |
| #define regBIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL 0x051a |
| #define regBIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS 0x051a |
| #define regBIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL 0x051b |
| #define regBIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS 0x051b |
| #define regBIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL 0x051c |
| #define regBIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS 0x051c |
| #define regBIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL 0x051d |
| #define regBIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS 0x051d |
| #define regBIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL 0x051e |
| #define regBIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS 0x051e |
| #define regBIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL 0x051f |
| #define regBIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS 0x051f |
| #define regBIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL 0x0520 |
| #define regBIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS 0x0520 |
| #define regBIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL 0x0521 |
| #define regBIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS 0x0521 |
| #define regBIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL 0x0522 |
| #define regBIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS 0x0522 |
| #define regBIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL 0x0523 |
| #define regBIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS 0x0523 |
| #define regBIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL 0x0524 |
| #define regBIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS 0x0524 |
| #define regBIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL 0x0525 |
| #define regBIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS 0x0525 |
| #define regBIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp |
| // base address: 0x10102000 |
| #define regBIF_CFG_DEV2_RC0_VENDOR_ID 0x0800 |
| #define regBIF_CFG_DEV2_RC0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_ID 0x0800 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_COMMAND 0x0801 |
| #define regBIF_CFG_DEV2_RC0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_STATUS 0x0801 |
| #define regBIF_CFG_DEV2_RC0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_REVISION_ID 0x0802 |
| #define regBIF_CFG_DEV2_RC0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PROG_INTERFACE 0x0802 |
| #define regBIF_CFG_DEV2_RC0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_SUB_CLASS 0x0802 |
| #define regBIF_CFG_DEV2_RC0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_BASE_CLASS 0x0802 |
| #define regBIF_CFG_DEV2_RC0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_CACHE_LINE 0x0803 |
| #define regBIF_CFG_DEV2_RC0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LATENCY 0x0803 |
| #define regBIF_CFG_DEV2_RC0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_HEADER 0x0803 |
| #define regBIF_CFG_DEV2_RC0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_BIST 0x0803 |
| #define regBIF_CFG_DEV2_RC0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_BASE_ADDR_1 0x0804 |
| #define regBIF_CFG_DEV2_RC0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_BASE_ADDR_2 0x0805 |
| #define regBIF_CFG_DEV2_RC0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY 0x0806 |
| #define regBIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_IO_BASE_LIMIT 0x0807 |
| #define regBIF_CFG_DEV2_RC0_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_SECONDARY_STATUS 0x0807 |
| #define regBIF_CFG_DEV2_RC0_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MEM_BASE_LIMIT 0x0808 |
| #define regBIF_CFG_DEV2_RC0_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PREF_BASE_LIMIT 0x0809 |
| #define regBIF_CFG_DEV2_RC0_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PREF_BASE_UPPER 0x080a |
| #define regBIF_CFG_DEV2_RC0_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER 0x080b |
| #define regBIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI 0x080c |
| #define regBIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_CAP_PTR 0x080d |
| #define regBIF_CFG_DEV2_RC0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_ROM_BASE_ADDR 0x080e |
| #define regBIF_CFG_DEV2_RC0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_INTERRUPT_LINE 0x080f |
| #define regBIF_CFG_DEV2_RC0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_INTERRUPT_PIN 0x080f |
| #define regBIF_CFG_DEV2_RC0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL 0x080f |
| #define regBIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL 0x0810 |
| #define regBIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PMI_CAP_LIST 0x0814 |
| #define regBIF_CFG_DEV2_RC0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PMI_CAP 0x0814 |
| #define regBIF_CFG_DEV2_RC0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PMI_STATUS_CNTL 0x0815 |
| #define regBIF_CFG_DEV2_RC0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_CAP_LIST 0x0816 |
| #define regBIF_CFG_DEV2_RC0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_CAP 0x0816 |
| #define regBIF_CFG_DEV2_RC0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_CAP 0x0817 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_CNTL 0x0818 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_STATUS 0x0818 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LINK_CAP 0x0819 |
| #define regBIF_CFG_DEV2_RC0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LINK_CNTL 0x081a |
| #define regBIF_CFG_DEV2_RC0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LINK_STATUS 0x081a |
| #define regBIF_CFG_DEV2_RC0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_SLOT_CAP 0x081b |
| #define regBIF_CFG_DEV2_RC0_SLOT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_SLOT_CNTL 0x081c |
| #define regBIF_CFG_DEV2_RC0_SLOT_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_SLOT_STATUS 0x081c |
| #define regBIF_CFG_DEV2_RC0_SLOT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_ROOT_CNTL 0x081d |
| #define regBIF_CFG_DEV2_RC0_ROOT_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_ROOT_CAP 0x081d |
| #define regBIF_CFG_DEV2_RC0_ROOT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_ROOT_STATUS 0x081e |
| #define regBIF_CFG_DEV2_RC0_ROOT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_CAP2 0x081f |
| #define regBIF_CFG_DEV2_RC0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_CNTL2 0x0820 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_STATUS2 0x0820 |
| #define regBIF_CFG_DEV2_RC0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LINK_CAP2 0x0821 |
| #define regBIF_CFG_DEV2_RC0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LINK_CNTL2 0x0822 |
| #define regBIF_CFG_DEV2_RC0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LINK_STATUS2 0x0822 |
| #define regBIF_CFG_DEV2_RC0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_SLOT_CAP2 0x0823 |
| #define regBIF_CFG_DEV2_RC0_SLOT_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_SLOT_CNTL2 0x0824 |
| #define regBIF_CFG_DEV2_RC0_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_SLOT_STATUS2 0x0824 |
| #define regBIF_CFG_DEV2_RC0_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MSI_CAP_LIST 0x0828 |
| #define regBIF_CFG_DEV2_RC0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MSI_MSG_CNTL 0x0828 |
| #define regBIF_CFG_DEV2_RC0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO 0x0829 |
| #define regBIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI 0x082a |
| #define regBIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MSI_MSG_DATA 0x082a |
| #define regBIF_CFG_DEV2_RC0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA 0x082a |
| #define regBIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MSI_MSG_DATA_64 0x082b |
| #define regBIF_CFG_DEV2_RC0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64 0x082b |
| #define regBIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_SSID_CAP_LIST 0x0830 |
| #define regBIF_CFG_DEV2_RC0_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_SSID_CAP 0x0831 |
| #define regBIF_CFG_DEV2_RC0_SSID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST 0x0832 |
| #define regBIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MSI_MAP_CAP 0x0832 |
| #define regBIF_CFG_DEV2_RC0_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0840 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0841 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1 0x0842 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2 0x0843 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST 0x0844 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1 0x0845 |
| #define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2 0x0846 |
| #define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL 0x0847 |
| #define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS 0x0847 |
| #define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP 0x0848 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL 0x0849 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS 0x084a |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP 0x084b |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL 0x084c |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS 0x084d |
| #define regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0850 |
| #define regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0851 |
| #define regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0852 |
| #define regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0854 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS 0x0855 |
| #define regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK 0x0856 |
| #define regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY 0x0857 |
| #define regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS 0x0858 |
| #define regBIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK 0x0859 |
| #define regBIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL 0x085a |
| #define regBIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG0 0x085b |
| #define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG1 0x085c |
| #define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG2 0x085d |
| #define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG3 0x085e |
| #define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD 0x085f |
| #define regBIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS 0x0860 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID 0x0861 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0 0x0862 |
| #define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1 0x0863 |
| #define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2 0x0864 |
| #define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3 0x0865 |
| #define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x089c |
| #define regBIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3 0x089d |
| #define regBIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS 0x089e |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x089f |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x089f |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x08a0 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x08a0 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x08a1 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x08a1 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x08a2 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x08a2 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x08a3 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x08a3 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x08a4 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x08a4 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x08a5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x08a5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x08a6 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x08a6 |
| #define regBIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST 0x08a8 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ACS_CAP 0x08a9 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ACS_CNTL 0x08a9 |
| #define regBIF_CFG_DEV2_RC0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST 0x0900 |
| #define regBIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP 0x0901 |
| #define regBIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS 0x0902 |
| #define regBIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0904 |
| #define regBIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LINK_CAP_16GT 0x0905 |
| #define regBIF_CFG_DEV2_RC0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LINK_CNTL_16GT 0x0906 |
| #define regBIF_CFG_DEV2_RC0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LINK_STATUS_16GT 0x0907 |
| #define regBIF_CFG_DEV2_RC0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0908 |
| #define regBIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0909 |
| #define regBIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x090a |
| #define regBIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0x090c |
| #define regBIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0x090c |
| #define regBIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0x090c |
| #define regBIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0x090c |
| #define regBIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0x090d |
| #define regBIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0x090d |
| #define regBIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0x090d |
| #define regBIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0x090d |
| #define regBIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0x090e |
| #define regBIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0x090e |
| #define regBIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0x090e |
| #define regBIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0x090e |
| #define regBIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0x090f |
| #define regBIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0x090f |
| #define regBIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0x090f |
| #define regBIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0x090f |
| #define regBIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST 0x0914 |
| #define regBIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MARGINING_PORT_CAP 0x0915 |
| #define regBIF_CFG_DEV2_RC0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS 0x0915 |
| #define regBIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL 0x0916 |
| #define regBIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS 0x0916 |
| #define regBIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL 0x0917 |
| #define regBIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS 0x0917 |
| #define regBIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL 0x0918 |
| #define regBIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS 0x0918 |
| #define regBIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL 0x0919 |
| #define regBIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS 0x0919 |
| #define regBIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL 0x091a |
| #define regBIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS 0x091a |
| #define regBIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL 0x091b |
| #define regBIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS 0x091b |
| #define regBIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL 0x091c |
| #define regBIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS 0x091c |
| #define regBIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL 0x091d |
| #define regBIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS 0x091d |
| #define regBIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL 0x091e |
| #define regBIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS 0x091e |
| #define regBIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL 0x091f |
| #define regBIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS 0x091f |
| #define regBIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL 0x0920 |
| #define regBIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS 0x0920 |
| #define regBIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL 0x0921 |
| #define regBIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS 0x0921 |
| #define regBIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL 0x0922 |
| #define regBIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS 0x0922 |
| #define regBIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL 0x0923 |
| #define regBIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS 0x0923 |
| #define regBIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL 0x0924 |
| #define regBIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS 0x0924 |
| #define regBIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL 0x0925 |
| #define regBIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS 0x0925 |
| #define regBIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
| // base address: 0x10120000 |
| #define regBIF_BX_PF1_MM_INDEX 0x8000 |
| #define regBIF_BX_PF1_MM_INDEX_BASE_IDX 5 |
| #define regBIF_BX_PF1_MM_DATA 0x8001 |
| #define regBIF_BX_PF1_MM_DATA_BASE_IDX 5 |
| #define regBIF_BX_PF1_MM_INDEX_HI 0x8006 |
| #define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_SYSDEC |
| // base address: 0x10120000 |
| #define regBIF_BX1_PCIE_INDEX 0x800c |
| #define regBIF_BX1_PCIE_INDEX_BASE_IDX 5 |
| #define regBIF_BX1_PCIE_DATA 0x800d |
| #define regBIF_BX1_PCIE_DATA_BASE_IDX 5 |
| #define regBIF_BX1_PCIE_INDEX2 0x800e |
| #define regBIF_BX1_PCIE_INDEX2_BASE_IDX 5 |
| #define regBIF_BX1_PCIE_DATA2 0x800f |
| #define regBIF_BX1_PCIE_DATA2_BASE_IDX 5 |
| #define regBIF_BX1_SBIOS_SCRATCH_0 0x8048 |
| #define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 5 |
| #define regBIF_BX1_SBIOS_SCRATCH_1 0x8049 |
| #define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 5 |
| #define regBIF_BX1_SBIOS_SCRATCH_2 0x804a |
| #define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 5 |
| #define regBIF_BX1_SBIOS_SCRATCH_3 0x804b |
| #define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_0 0x804c |
| #define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_1 0x804d |
| #define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_2 0x804e |
| #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_3 0x804f |
| #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_4 0x8050 |
| #define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_5 0x8051 |
| #define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_6 0x8052 |
| #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_7 0x8053 |
| #define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_8 0x8054 |
| #define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_9 0x8055 |
| #define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_10 0x8056 |
| #define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_11 0x8057 |
| #define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_12 0x8058 |
| #define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_13 0x8059 |
| #define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_14 0x805a |
| #define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 5 |
| #define regBIF_BX1_BIOS_SCRATCH_15 0x805b |
| #define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 5 |
| #define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060 |
| #define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061 |
| #define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062 |
| #define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f |
| #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 5 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093 |
| #define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1:1 |
| // base address: 0x10120000 |
| #define regRCC_STRAP1_RCC_BIF_STRAP0 0x8d20 |
| #define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_BIF_STRAP1 0x8d21 |
| #define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_BIF_STRAP2 0x8d22 |
| #define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_BIF_STRAP3 0x8d23 |
| #define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_BIF_STRAP4 0x8d24 |
| #define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_BIF_STRAP5 0x8d25 |
| #define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_BIF_STRAP6 0x8d26 |
| #define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0x8d27 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0x8d28 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0x8d29 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0x8d2a |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0x8d2b |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0x8d2c |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0x8d2d |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0x8d2e |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0x8d2f |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0x8d30 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0x8d31 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0x8d32 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0x8d33 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0x8d34 |
| #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0x8d35 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0x8d36 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0x8d37 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0x8d38 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0x8d39 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0x8d3a |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0x8d3b |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0x8d3c |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0x8d3d |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0x8d3e |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0x8d3f |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0x8d40 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0x8d42 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0x8d43 |
| #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0x8d44 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0x8d4f |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0x8d50 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0x8d51 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0x8d52 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0x8d53 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0x8d54 |
| #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
| // base address: 0x10120000 |
| #define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0x8d56 |
| #define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0x8d58 |
| #define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0x8d59 |
| #define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0x8d5a |
| #define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0x8d5b |
| #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0x8d5c |
| #define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0x8d5d |
| #define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0x8d5f |
| #define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d60 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d60 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d60 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d60 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d61 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d61 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d61 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d61 |
| #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0x8d62 |
| #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0x8d63 |
| #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0x8d65 |
| #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d66 |
| #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0x8d66 |
| #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d66 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d67 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d67 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d67 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d67 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d68 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d68 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d68 |
| #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0x8d68 |
| #define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0x8d69 |
| #define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0x8d6b |
| #define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0x8d6c |
| #define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0x8d6d |
| #define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0x8d6e |
| #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0x8d6f |
| #define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
| // base address: 0x10120000 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0x8d70 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0x8d71 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0x8d73 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0x8d74 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0x8d75 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0x8d76 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0x8d77 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0x8d78 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0x8d79 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0x8d7a |
| #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
| // base address: 0x10120000 |
| #define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0x8d7c |
| #define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0x8d7d |
| #define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0x8d7e |
| #define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0x8d7f |
| #define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0x8d80 |
| #define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0x8d81 |
| #define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 |
| // base address: 0x10120000 |
| #define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6 |
| #define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7 |
| #define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_RESET_EN 0x8da8 |
| #define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_VDM_SUPPORT 0x8da9 |
| #define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0x8daa |
| #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0x8dab |
| #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac |
| #define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad |
| #define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae |
| #define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf |
| #define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf |
| #define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde |
| #define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf |
| #define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_BUS_CNTL 0x8de1 |
| #define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2 |
| #define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6 |
| #define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7 |
| #define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8 |
| #define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9 |
| #define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea |
| #define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0x8deb |
| #define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec |
| #define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded |
| #define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee |
| #define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def |
| #define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0 |
| #define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1 |
| #define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2 |
| #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3 |
| #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4 |
| #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5 |
| #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6 |
| #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7 |
| #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8 |
| #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9 |
| #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa |
| #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb |
| #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0x8dfd |
| #define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0x8dfe |
| #define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0x8dff |
| #define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0x8e00 |
| #define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0x8e01 |
| #define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 |
| // base address: 0x10120000 |
| #define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02 |
| #define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 5 |
| #define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04 |
| #define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 5 |
| #define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06 |
| #define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BUS_CNTL 0x8e07 |
| #define regBIF_BX1_BUS_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_SCRATCH0 0x8e08 |
| #define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 5 |
| #define regBIF_BX1_BIF_SCRATCH1 0x8e09 |
| #define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 5 |
| #define regBIF_BX1_BX_RESET_EN 0x8e0d |
| #define regBIF_BX1_BX_RESET_EN_BASE_IDX 5 |
| #define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e |
| #define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BX_RESET_CNTL 0x8e10 |
| #define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_INTERRUPT_CNTL 0x8e11 |
| #define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_INTERRUPT_CNTL2 0x8e12 |
| #define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 5 |
| #define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18 |
| #define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b |
| #define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 5 |
| #define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d |
| #define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e |
| #define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_FB_EN 0x8e20 |
| #define regBIF_BX1_BIF_FB_EN_BASE_IDX 5 |
| #define regBIF_BX1_BIF_INTR_CNTL 0x8e21 |
| #define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29 |
| #define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 5 |
| #define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a |
| #define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 5 |
| #define regBIF_BX1_BACO_CNTL 0x8e2b |
| #define regBIF_BX1_BACO_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_BACO_EXIT_TIME0 0x8e2c |
| #define regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX 5 |
| #define regBIF_BX1_BIF_BACO_EXIT_TIMER1 0x8e2d |
| #define regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX 5 |
| #define regBIF_BX1_BIF_BACO_EXIT_TIMER2 0x8e2e |
| #define regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX 5 |
| #define regBIF_BX1_BIF_BACO_EXIT_TIMER3 0x8e2f |
| #define regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX 5 |
| #define regBIF_BX1_BIF_BACO_EXIT_TIMER4 0x8e30 |
| #define regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX 5 |
| #define regBIF_BX1_MEM_TYPE_CNTL 0x8e31 |
| #define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL 0x8e33 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_0 0x8e34 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_1 0x8e35 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_2 0x8e36 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_3 0x8e37 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_4 0x8e38 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_5 0x8e39 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_6 0x8e3a |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_7 0x8e3b |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_8 0x8e3c |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_9 0x8e3d |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_10 0x8e3e |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_11 0x8e3f |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_12 0x8e40 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_13 0x8e41 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_14 0x8e42 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX 5 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_15 0x8e43 |
| #define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX 5 |
| #define regBIF_BX1_VF_REGWR_EN 0x8e44 |
| #define regBIF_BX1_VF_REGWR_EN_BASE_IDX 5 |
| #define regBIF_BX1_VF_DOORBELL_EN 0x8e45 |
| #define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 5 |
| #define regBIF_BX1_VF_FB_EN 0x8e46 |
| #define regBIF_BX1_VF_FB_EN_BASE_IDX 5 |
| #define regBIF_BX1_VF_REGWR_STATUS 0x8e47 |
| #define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 5 |
| #define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48 |
| #define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 5 |
| #define regBIF_BX1_VF_FB_STATUS 0x8e49 |
| #define regBIF_BX1_VF_FB_STATUS_BASE_IDX 5 |
| #define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d |
| #define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e |
| #define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_RB_CNTL 0x8e4f |
| #define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_RB_BASE 0x8e50 |
| #define regBIF_BX1_BIF_RB_BASE_BASE_IDX 5 |
| #define regBIF_BX1_BIF_RB_RPTR 0x8e51 |
| #define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 5 |
| #define regBIF_BX1_BIF_RB_WPTR 0x8e52 |
| #define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 5 |
| #define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53 |
| #define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 5 |
| #define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54 |
| #define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 5 |
| #define regBIF_BX1_MAILBOX_INDEX 0x8e55 |
| #define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 5 |
| #define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE 0x8e63 |
| #define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX 5 |
| #define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE 0x8e64 |
| #define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX 5 |
| #define regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x8e65 |
| #define regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 5 |
| #define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e68 |
| #define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e69 |
| #define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e6a |
| #define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e6b |
| #define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 5 |
| #define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e6c |
| #define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
| // base address: 0x10120000 |
| #define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b |
| #define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 5 |
| #define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c |
| #define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 |
| #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 |
| #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 |
| #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 |
| #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 |
| #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 |
| #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 |
| #define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 |
| #define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 |
| #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 |
| #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 |
| #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 |
| #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 |
| #define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a |
| #define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 |
| #define regBIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ 0x8e24 |
| #define regBIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ_BASE_IDX 5 |
| #define regBIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ 0x8e25 |
| #define regBIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ_BASE_IDX 5 |
| #define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26 |
| #define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 5 |
| #define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27 |
| #define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 5 |
| #define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28 |
| #define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 5 |
| #define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 |
| #define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56 |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57 |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58 |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59 |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d |
| #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 |
| #define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e |
| #define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 5 |
| #define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f |
| #define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 5 |
| #define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60 |
| #define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal |
| // base address: 0x10100000 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0xc400 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0xc401 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0xc402 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0xc403 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0xc404 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0xc405 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0xc406 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0xc407 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0xc408 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0xc409 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0xc40a |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0xc40b |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0xc40c |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0xc40d |
| #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP0 0xc480 |
| #define regRCC_DEV1_PORT_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP1 0xc481 |
| #define regRCC_DEV1_PORT_STRAP1_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP2 0xc482 |
| #define regRCC_DEV1_PORT_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP3 0xc483 |
| #define regRCC_DEV1_PORT_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP4 0xc484 |
| #define regRCC_DEV1_PORT_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP5 0xc485 |
| #define regRCC_DEV1_PORT_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP6 0xc486 |
| #define regRCC_DEV1_PORT_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP7 0xc487 |
| #define regRCC_DEV1_PORT_STRAP7_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP8 0xc488 |
| #define regRCC_DEV1_PORT_STRAP8_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP9 0xc489 |
| #define regRCC_DEV1_PORT_STRAP9_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP10 0xc48a |
| #define regRCC_DEV1_PORT_STRAP10_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP11 0xc48b |
| #define regRCC_DEV1_PORT_STRAP11_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP12 0xc48c |
| #define regRCC_DEV1_PORT_STRAP12_BASE_IDX 5 |
| #define regRCC_DEV1_PORT_STRAP13 0xc48d |
| #define regRCC_DEV1_PORT_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP0 0xc500 |
| #define regRCC_DEV2_PORT_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP1 0xc501 |
| #define regRCC_DEV2_PORT_STRAP1_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP2 0xc502 |
| #define regRCC_DEV2_PORT_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP3 0xc503 |
| #define regRCC_DEV2_PORT_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP4 0xc504 |
| #define regRCC_DEV2_PORT_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP5 0xc505 |
| #define regRCC_DEV2_PORT_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP6 0xc506 |
| #define regRCC_DEV2_PORT_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP7 0xc507 |
| #define regRCC_DEV2_PORT_STRAP7_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP8 0xc508 |
| #define regRCC_DEV2_PORT_STRAP8_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP9 0xc509 |
| #define regRCC_DEV2_PORT_STRAP9_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP10 0xc50a |
| #define regRCC_DEV2_PORT_STRAP10_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP11 0xc50b |
| #define regRCC_DEV2_PORT_STRAP11_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP12 0xc50c |
| #define regRCC_DEV2_PORT_STRAP12_BASE_IDX 5 |
| #define regRCC_DEV2_PORT_STRAP13 0xc50d |
| #define regRCC_DEV2_PORT_STRAP13_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_BIF_STRAP0 0xc600 |
| #define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_BIF_STRAP1 0xc601 |
| #define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_BIF_STRAP2 0xc602 |
| #define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_BIF_STRAP3 0xc603 |
| #define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_BIF_STRAP4 0xc604 |
| #define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_BIF_STRAP5 0xc605 |
| #define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_BIF_STRAP6 0xc606 |
| #define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0xd000 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0xd001 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0xd002 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0xd003 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0xd004 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0xd005 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0xd008 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0xd009 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0xd00d |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0xd00e |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0xd00f |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0xd010 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0xd011 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0xd012 |
| #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0xd080 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0xd082 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0xd083 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0xd084 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0xd085 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0xd086 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0xd087 |
| #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 |
| #define regRCC_DEV0_EPF2_STRAP0 0xd100 |
| #define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV0_EPF2_STRAP2 0xd102 |
| #define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV0_EPF2_STRAP3 0xd103 |
| #define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV0_EPF2_STRAP4 0xd104 |
| #define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV0_EPF2_STRAP5 0xd105 |
| #define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV0_EPF2_STRAP6 0xd106 |
| #define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV0_EPF2_STRAP7 0xd107 |
| #define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 5 |
| #define regRCC_DEV0_EPF2_STRAP10 0xd10a |
| #define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 5 |
| #define regRCC_DEV0_EPF2_STRAP11 0xd10b |
| #define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 5 |
| #define regRCC_DEV0_EPF2_STRAP12 0xd10c |
| #define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 5 |
| #define regRCC_DEV0_EPF2_STRAP13 0xd10d |
| #define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV0_EPF2_STRAP14 0xd10e |
| #define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV0_EPF3_STRAP0 0xd180 |
| #define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV0_EPF3_STRAP2 0xd182 |
| #define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV0_EPF3_STRAP3 0xd183 |
| #define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV0_EPF3_STRAP4 0xd184 |
| #define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV0_EPF3_STRAP5 0xd185 |
| #define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV0_EPF3_STRAP6 0xd186 |
| #define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV0_EPF3_STRAP7 0xd187 |
| #define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 5 |
| #define regRCC_DEV0_EPF3_STRAP10 0xd18a |
| #define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 5 |
| #define regRCC_DEV0_EPF3_STRAP11 0xd18b |
| #define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 5 |
| #define regRCC_DEV0_EPF3_STRAP12 0xd18c |
| #define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 5 |
| #define regRCC_DEV0_EPF3_STRAP13 0xd18d |
| #define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV0_EPF3_STRAP14 0xd18e |
| #define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV0_EPF4_STRAP0 0xd200 |
| #define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV0_EPF4_STRAP2 0xd202 |
| #define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV0_EPF4_STRAP3 0xd203 |
| #define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV0_EPF4_STRAP4 0xd204 |
| #define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV0_EPF4_STRAP5 0xd205 |
| #define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV0_EPF4_STRAP6 0xd206 |
| #define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV0_EPF4_STRAP7 0xd207 |
| #define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 5 |
| #define regRCC_DEV0_EPF4_STRAP13 0xd20d |
| #define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV0_EPF4_STRAP14 0xd20e |
| #define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV0_EPF5_STRAP0 0xd280 |
| #define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV0_EPF5_STRAP2 0xd282 |
| #define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV0_EPF5_STRAP3 0xd283 |
| #define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV0_EPF5_STRAP4 0xd284 |
| #define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV0_EPF5_STRAP5 0xd285 |
| #define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV0_EPF5_STRAP6 0xd286 |
| #define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV0_EPF5_STRAP7 0xd287 |
| #define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 5 |
| #define regRCC_DEV0_EPF5_STRAP13 0xd28d |
| #define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV0_EPF5_STRAP14 0xd28e |
| #define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV0_EPF6_STRAP0 0xd300 |
| #define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV0_EPF6_STRAP2 0xd302 |
| #define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV0_EPF6_STRAP3 0xd303 |
| #define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV0_EPF6_STRAP4 0xd304 |
| #define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV0_EPF6_STRAP5 0xd305 |
| #define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV0_EPF6_STRAP6 0xd306 |
| #define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV0_EPF6_STRAP7 0xd307 |
| #define regRCC_DEV0_EPF6_STRAP7_BASE_IDX 5 |
| #define regRCC_DEV0_EPF6_STRAP13 0xd30d |
| #define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV0_EPF6_STRAP14 0xd30e |
| #define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV0_EPF7_STRAP0 0xd380 |
| #define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV0_EPF7_STRAP2 0xd382 |
| #define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV0_EPF7_STRAP3 0xd383 |
| #define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV0_EPF7_STRAP4 0xd384 |
| #define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV0_EPF7_STRAP5 0xd385 |
| #define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV0_EPF7_STRAP6 0xd386 |
| #define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV0_EPF7_STRAP7 0xd387 |
| #define regRCC_DEV0_EPF7_STRAP7_BASE_IDX 5 |
| #define regRCC_DEV0_EPF7_STRAP13 0xd38d |
| #define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV0_EPF7_STRAP14 0xd38e |
| #define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV1_EPF0_STRAP0 0xd400 |
| #define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV1_EPF0_STRAP2 0xd402 |
| #define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV1_EPF0_STRAP3 0xd403 |
| #define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV1_EPF0_STRAP4 0xd404 |
| #define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV1_EPF0_STRAP5 0xd405 |
| #define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV1_EPF0_STRAP6 0xd406 |
| #define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV1_EPF0_STRAP7 0xd407 |
| #define regRCC_DEV1_EPF0_STRAP7_BASE_IDX 5 |
| #define regRCC_DEV1_EPF0_STRAP13 0xd40d |
| #define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV1_EPF0_STRAP14 0xd40e |
| #define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV1_EPF1_STRAP0 0xd480 |
| #define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV1_EPF1_STRAP2 0xd482 |
| #define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV1_EPF1_STRAP3 0xd483 |
| #define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV1_EPF1_STRAP4 0xd484 |
| #define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV1_EPF1_STRAP5 0xd485 |
| #define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV1_EPF1_STRAP6 0xd486 |
| #define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV1_EPF1_STRAP7 0xd487 |
| #define regRCC_DEV1_EPF1_STRAP7_BASE_IDX 5 |
| #define regRCC_DEV1_EPF2_STRAP0 0xd500 |
| #define regRCC_DEV1_EPF2_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV1_EPF2_STRAP2 0xd502 |
| #define regRCC_DEV1_EPF2_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV1_EPF2_STRAP3 0xd503 |
| #define regRCC_DEV1_EPF2_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV1_EPF2_STRAP4 0xd504 |
| #define regRCC_DEV1_EPF2_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV1_EPF2_STRAP5 0xd505 |
| #define regRCC_DEV1_EPF2_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV1_EPF2_STRAP6 0xd506 |
| #define regRCC_DEV1_EPF2_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV1_EPF2_STRAP13 0xd50d |
| #define regRCC_DEV1_EPF2_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV1_EPF2_STRAP14 0xd50e |
| #define regRCC_DEV1_EPF2_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV1_EPF3_STRAP0 0xd580 |
| #define regRCC_DEV1_EPF3_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV1_EPF3_STRAP2 0xd582 |
| #define regRCC_DEV1_EPF3_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV1_EPF3_STRAP3 0xd583 |
| #define regRCC_DEV1_EPF3_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV1_EPF3_STRAP4 0xd584 |
| #define regRCC_DEV1_EPF3_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV1_EPF3_STRAP5 0xd585 |
| #define regRCC_DEV1_EPF3_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV1_EPF3_STRAP6 0xd586 |
| #define regRCC_DEV1_EPF3_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV1_EPF3_STRAP13 0xd58d |
| #define regRCC_DEV1_EPF3_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV1_EPF3_STRAP14 0xd58e |
| #define regRCC_DEV1_EPF3_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV1_EPF4_STRAP0 0xd600 |
| #define regRCC_DEV1_EPF4_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV1_EPF4_STRAP2 0xd602 |
| #define regRCC_DEV1_EPF4_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV1_EPF4_STRAP3 0xd603 |
| #define regRCC_DEV1_EPF4_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV1_EPF4_STRAP4 0xd604 |
| #define regRCC_DEV1_EPF4_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV1_EPF4_STRAP5 0xd605 |
| #define regRCC_DEV1_EPF4_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV1_EPF4_STRAP6 0xd606 |
| #define regRCC_DEV1_EPF4_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV1_EPF4_STRAP13 0xd60d |
| #define regRCC_DEV1_EPF4_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV1_EPF4_STRAP14 0xd60e |
| #define regRCC_DEV1_EPF4_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV1_EPF5_STRAP0 0xd680 |
| #define regRCC_DEV1_EPF5_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV1_EPF5_STRAP2 0xd682 |
| #define regRCC_DEV1_EPF5_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV1_EPF5_STRAP3 0xd683 |
| #define regRCC_DEV1_EPF5_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV1_EPF5_STRAP4 0xd684 |
| #define regRCC_DEV1_EPF5_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV1_EPF5_STRAP5 0xd685 |
| #define regRCC_DEV1_EPF5_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV1_EPF5_STRAP6 0xd686 |
| #define regRCC_DEV1_EPF5_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV1_EPF5_STRAP13 0xd68d |
| #define regRCC_DEV1_EPF5_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV1_EPF5_STRAP14 0xd68e |
| #define regRCC_DEV1_EPF5_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV2_EPF0_STRAP0 0xd800 |
| #define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV2_EPF0_STRAP2 0xd802 |
| #define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV2_EPF0_STRAP3 0xd803 |
| #define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV2_EPF0_STRAP4 0xd804 |
| #define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV2_EPF0_STRAP5 0xd805 |
| #define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV2_EPF0_STRAP6 0xd806 |
| #define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV2_EPF0_STRAP7 0xd807 |
| #define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 5 |
| #define regRCC_DEV2_EPF0_STRAP13 0xd80d |
| #define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV2_EPF0_STRAP14 0xd80e |
| #define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV2_EPF1_STRAP0 0xd880 |
| #define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV2_EPF1_STRAP2 0xd882 |
| #define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV2_EPF1_STRAP3 0xd883 |
| #define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV2_EPF1_STRAP4 0xd884 |
| #define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV2_EPF1_STRAP5 0xd885 |
| #define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV2_EPF1_STRAP6 0xd886 |
| #define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV2_EPF1_STRAP13 0xd88d |
| #define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV2_EPF1_STRAP14 0xd88e |
| #define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 5 |
| #define regRCC_DEV2_EPF2_STRAP0 0xd900 |
| #define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 5 |
| #define regRCC_DEV2_EPF2_STRAP2 0xd902 |
| #define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 5 |
| #define regRCC_DEV2_EPF2_STRAP3 0xd903 |
| #define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 5 |
| #define regRCC_DEV2_EPF2_STRAP4 0xd904 |
| #define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 5 |
| #define regRCC_DEV2_EPF2_STRAP5 0xd905 |
| #define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 5 |
| #define regRCC_DEV2_EPF2_STRAP6 0xd906 |
| #define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 5 |
| #define regRCC_DEV2_EPF2_STRAP13 0xd90d |
| #define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 5 |
| #define regRCC_DEV2_EPF2_STRAP14 0xd90e |
| #define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC |
| // base address: 0x10131000 |
| #define regRCC_DEV0_2_RCC_VDM_SUPPORT 0xc440 |
| #define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_BUS_CNTL 0xc441 |
| #define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0xc442 |
| #define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0xc443 |
| #define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0xc444 |
| #define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0xc445 |
| #define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0xc446 |
| #define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0xc447 |
| #define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0xc448 |
| #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0xc449 |
| #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC |
| // base address: 0x10131000 |
| #define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0xc44c |
| #define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0xc44e |
| #define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0xc44f |
| #define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0xc450 |
| #define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0xc451 |
| #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0xc452 |
| #define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0xc453 |
| #define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0xc454 |
| #define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0xc455 |
| #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0xc456 |
| #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0xc457 |
| #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458 |
| #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0xc458 |
| #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a |
| #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0xc45c |
| #define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0xc45d |
| #define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0xc45f |
| #define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0xc460 |
| #define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0xc461 |
| #define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0xc462 |
| #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0xc463 |
| #define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC |
| // base address: 0x10131000 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0xc468 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0xc469 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0xc46b |
| #define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0xc46c |
| #define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0xc46d |
| #define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0xc46e |
| #define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0xc46f |
| #define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0xc470 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0xc471 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0xc472 |
| #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC |
| // base address: 0x10131000 |
| #define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0xc475 |
| #define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0xc476 |
| #define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0xc477 |
| #define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0xc478 |
| #define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0xc479 |
| #define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0xc47a |
| #define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev1_RCCPORTDEC |
| // base address: 0x10131200 |
| #define regRCC_DEV1_RCC_VDM_SUPPORT 0xc4c0 |
| #define regRCC_DEV1_RCC_VDM_SUPPORT_BASE_IDX 5 |
| #define regRCC_DEV1_RCC_BUS_CNTL 0xc4c1 |
| #define regRCC_DEV1_RCC_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_DEV1_RCC_FEATURES_CONTROL_MISC 0xc4c2 |
| #define regRCC_DEV1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 |
| #define regRCC_DEV1_RCC_DEV0_LINK_CNTL 0xc4c3 |
| #define regRCC_DEV1_RCC_DEV0_LINK_CNTL_BASE_IDX 5 |
| #define regRCC_DEV1_RCC_CMN_LINK_CNTL 0xc4c4 |
| #define regRCC_DEV1_RCC_CMN_LINK_CNTL_BASE_IDX 5 |
| #define regRCC_DEV1_RCC_EP_REQUESTERID_RESTORE 0xc4c5 |
| #define regRCC_DEV1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 |
| #define regRCC_DEV1_RCC_LTR_LSWITCH_CNTL 0xc4c6 |
| #define regRCC_DEV1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 |
| #define regRCC_DEV1_RCC_MH_ARB_CNTL 0xc4c7 |
| #define regRCC_DEV1_RCC_MH_ARB_CNTL_BASE_IDX 5 |
| #define regRCC_DEV1_RCC_MARGIN_PARAM_CNTL0 0xc4c8 |
| #define regRCC_DEV1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 |
| #define regRCC_DEV1_RCC_MARGIN_PARAM_CNTL1 0xc4c9 |
| #define regRCC_DEV1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_ep_dev1_RCCPORTDEC |
| // base address: 0x10131200 |
| #define regRCC_EP_DEV1_EP_PCIE_SCRATCH 0xc4cc |
| #define regRCC_EP_DEV1_EP_PCIE_SCRATCH_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_CNTL 0xc4ce |
| #define regRCC_EP_DEV1_EP_PCIE_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_INT_CNTL 0xc4cf |
| #define regRCC_EP_DEV1_EP_PCIE_INT_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_INT_STATUS 0xc4d0 |
| #define regRCC_EP_DEV1_EP_PCIE_INT_STATUS_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_RX_CNTL2 0xc4d1 |
| #define regRCC_EP_DEV1_EP_PCIE_RX_CNTL2_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_BUS_CNTL 0xc4d2 |
| #define regRCC_EP_DEV1_EP_PCIE_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_CFG_CNTL 0xc4d3 |
| #define regRCC_EP_DEV1_EP_PCIE_CFG_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL 0xc4d4 |
| #define regRCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_STRAP_MISC 0xc4d5 |
| #define regRCC_EP_DEV1_EP_PCIE_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_STRAP_MISC2 0xc4d6 |
| #define regRCC_EP_DEV1_EP_PCIE_STRAP_MISC2_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_F0_DPA_CAP 0xc4d7 |
| #define regRCC_EP_DEV1_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc4d8 |
| #define regRCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL 0xc4d8 |
| #define regRCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc4d8 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc4d9 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc4d9 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc4d9 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc4d9 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc4da |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc4da |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc4da |
| #define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_PME_CONTROL 0xc4dc |
| #define regRCC_EP_DEV1_EP_PCIE_PME_CONTROL_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIEP_RESERVED 0xc4dd |
| #define regRCC_EP_DEV1_EP_PCIEP_RESERVED_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_TX_CNTL 0xc4df |
| #define regRCC_EP_DEV1_EP_PCIE_TX_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID 0xc4e0 |
| #define regRCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_ERR_CNTL 0xc4e1 |
| #define regRCC_EP_DEV1_EP_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_RX_CNTL 0xc4e2 |
| #define regRCC_EP_DEV1_EP_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL 0xc4e3 |
| #define regRCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwn_dev1_RCCPORTDEC |
| // base address: 0x10131200 |
| #define regRCC_DWN_DEV1_DN_PCIE_RESERVED 0xc4e8 |
| #define regRCC_DWN_DEV1_DN_PCIE_RESERVED_BASE_IDX 5 |
| #define regRCC_DWN_DEV1_DN_PCIE_SCRATCH 0xc4e9 |
| #define regRCC_DWN_DEV1_DN_PCIE_SCRATCH_BASE_IDX 5 |
| #define regRCC_DWN_DEV1_DN_PCIE_CNTL 0xc4eb |
| #define regRCC_DWN_DEV1_DN_PCIE_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL 0xc4ec |
| #define regRCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV1_DN_PCIE_RX_CNTL2 0xc4ed |
| #define regRCC_DWN_DEV1_DN_PCIE_RX_CNTL2_BASE_IDX 5 |
| #define regRCC_DWN_DEV1_DN_PCIE_BUS_CNTL 0xc4ee |
| #define regRCC_DWN_DEV1_DN_PCIE_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV1_DN_PCIE_CFG_CNTL 0xc4ef |
| #define regRCC_DWN_DEV1_DN_PCIE_CFG_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV1_DN_PCIE_STRAP_F0 0xc4f0 |
| #define regRCC_DWN_DEV1_DN_PCIE_STRAP_F0_BASE_IDX 5 |
| #define regRCC_DWN_DEV1_DN_PCIE_STRAP_MISC 0xc4f1 |
| #define regRCC_DWN_DEV1_DN_PCIE_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_DWN_DEV1_DN_PCIE_STRAP_MISC2 0xc4f2 |
| #define regRCC_DWN_DEV1_DN_PCIE_STRAP_MISC2_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwnp_dev1_RCCPORTDEC |
| // base address: 0x10131200 |
| #define regRCC_DWNP_DEV1_PCIE_ERR_CNTL 0xc4f5 |
| #define regRCC_DWNP_DEV1_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV1_PCIE_RX_CNTL 0xc4f6 |
| #define regRCC_DWNP_DEV1_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL 0xc4f7 |
| #define regRCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV1_PCIE_LC_CNTL2 0xc4f8 |
| #define regRCC_DWNP_DEV1_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regRCC_DWNP_DEV1_PCIEP_STRAP_MISC 0xc4f9 |
| #define regRCC_DWNP_DEV1_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP 0xc4fa |
| #define regRCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev2_RCCPORTDEC |
| // base address: 0x10131400 |
| #define regRCC_DEV2_RCC_VDM_SUPPORT 0xc540 |
| #define regRCC_DEV2_RCC_VDM_SUPPORT_BASE_IDX 5 |
| #define regRCC_DEV2_RCC_BUS_CNTL 0xc541 |
| #define regRCC_DEV2_RCC_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_DEV2_RCC_FEATURES_CONTROL_MISC 0xc542 |
| #define regRCC_DEV2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 |
| #define regRCC_DEV2_RCC_DEV0_LINK_CNTL 0xc543 |
| #define regRCC_DEV2_RCC_DEV0_LINK_CNTL_BASE_IDX 5 |
| #define regRCC_DEV2_RCC_CMN_LINK_CNTL 0xc544 |
| #define regRCC_DEV2_RCC_CMN_LINK_CNTL_BASE_IDX 5 |
| #define regRCC_DEV2_RCC_EP_REQUESTERID_RESTORE 0xc545 |
| #define regRCC_DEV2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 |
| #define regRCC_DEV2_RCC_LTR_LSWITCH_CNTL 0xc546 |
| #define regRCC_DEV2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 |
| #define regRCC_DEV2_RCC_MH_ARB_CNTL 0xc547 |
| #define regRCC_DEV2_RCC_MH_ARB_CNTL_BASE_IDX 5 |
| #define regRCC_DEV2_RCC_MARGIN_PARAM_CNTL0 0xc548 |
| #define regRCC_DEV2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 |
| #define regRCC_DEV2_RCC_MARGIN_PARAM_CNTL1 0xc549 |
| #define regRCC_DEV2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_ep_dev2_RCCPORTDEC |
| // base address: 0x10131400 |
| #define regRCC_EP_DEV2_EP_PCIE_SCRATCH 0xc54c |
| #define regRCC_EP_DEV2_EP_PCIE_SCRATCH_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_CNTL 0xc54e |
| #define regRCC_EP_DEV2_EP_PCIE_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_INT_CNTL 0xc54f |
| #define regRCC_EP_DEV2_EP_PCIE_INT_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_INT_STATUS 0xc550 |
| #define regRCC_EP_DEV2_EP_PCIE_INT_STATUS_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_RX_CNTL2 0xc551 |
| #define regRCC_EP_DEV2_EP_PCIE_RX_CNTL2_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_BUS_CNTL 0xc552 |
| #define regRCC_EP_DEV2_EP_PCIE_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_CFG_CNTL 0xc553 |
| #define regRCC_EP_DEV2_EP_PCIE_CFG_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL 0xc554 |
| #define regRCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_STRAP_MISC 0xc555 |
| #define regRCC_EP_DEV2_EP_PCIE_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_STRAP_MISC2 0xc556 |
| #define regRCC_EP_DEV2_EP_PCIE_STRAP_MISC2_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_F0_DPA_CAP 0xc557 |
| #define regRCC_EP_DEV2_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc558 |
| #define regRCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL 0xc558 |
| #define regRCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc558 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc559 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc559 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc559 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc559 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc55a |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc55a |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc55a |
| #define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_PME_CONTROL 0xc55c |
| #define regRCC_EP_DEV2_EP_PCIE_PME_CONTROL_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIEP_RESERVED 0xc55d |
| #define regRCC_EP_DEV2_EP_PCIEP_RESERVED_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_TX_CNTL 0xc55f |
| #define regRCC_EP_DEV2_EP_PCIE_TX_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID 0xc560 |
| #define regRCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_ERR_CNTL 0xc561 |
| #define regRCC_EP_DEV2_EP_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_RX_CNTL 0xc562 |
| #define regRCC_EP_DEV2_EP_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL 0xc563 |
| #define regRCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwn_dev2_RCCPORTDEC |
| // base address: 0x10131400 |
| #define regRCC_DWN_DEV2_DN_PCIE_RESERVED 0xc568 |
| #define regRCC_DWN_DEV2_DN_PCIE_RESERVED_BASE_IDX 5 |
| #define regRCC_DWN_DEV2_DN_PCIE_SCRATCH 0xc569 |
| #define regRCC_DWN_DEV2_DN_PCIE_SCRATCH_BASE_IDX 5 |
| #define regRCC_DWN_DEV2_DN_PCIE_CNTL 0xc56b |
| #define regRCC_DWN_DEV2_DN_PCIE_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL 0xc56c |
| #define regRCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV2_DN_PCIE_RX_CNTL2 0xc56d |
| #define regRCC_DWN_DEV2_DN_PCIE_RX_CNTL2_BASE_IDX 5 |
| #define regRCC_DWN_DEV2_DN_PCIE_BUS_CNTL 0xc56e |
| #define regRCC_DWN_DEV2_DN_PCIE_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV2_DN_PCIE_CFG_CNTL 0xc56f |
| #define regRCC_DWN_DEV2_DN_PCIE_CFG_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV2_DN_PCIE_STRAP_F0 0xc570 |
| #define regRCC_DWN_DEV2_DN_PCIE_STRAP_F0_BASE_IDX 5 |
| #define regRCC_DWN_DEV2_DN_PCIE_STRAP_MISC 0xc571 |
| #define regRCC_DWN_DEV2_DN_PCIE_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_DWN_DEV2_DN_PCIE_STRAP_MISC2 0xc572 |
| #define regRCC_DWN_DEV2_DN_PCIE_STRAP_MISC2_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwnp_dev2_RCCPORTDEC |
| // base address: 0x10131400 |
| #define regRCC_DWNP_DEV2_PCIE_ERR_CNTL 0xc575 |
| #define regRCC_DWNP_DEV2_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV2_PCIE_RX_CNTL 0xc576 |
| #define regRCC_DWNP_DEV2_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL 0xc577 |
| #define regRCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV2_PCIE_LC_CNTL2 0xc578 |
| #define regRCC_DWNP_DEV2_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regRCC_DWNP_DEV2_PCIEP_STRAP_MISC 0xc579 |
| #define regRCC_DWNP_DEV2_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP 0xc57a |
| #define regRCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk |
| // base address: 0x10100000 |
| #define regNBIF_STRAP_BIOS_CNTL 0xcc81 |
| #define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 5 |
| #define regMISC_SCRATCH 0xe800 |
| #define regMISC_SCRATCH_BASE_IDX 5 |
| #define regINTR_LINE_POLARITY 0xe801 |
| #define regINTR_LINE_POLARITY_BASE_IDX 5 |
| #define regINTR_LINE_ENABLE 0xe802 |
| #define regINTR_LINE_ENABLE_BASE_IDX 5 |
| #define regOUTSTANDING_VC_ALLOC 0xe803 |
| #define regOUTSTANDING_VC_ALLOC_BASE_IDX 5 |
| #define regBIFC_MISC_CTRL0 0xe804 |
| #define regBIFC_MISC_CTRL0_BASE_IDX 5 |
| #define regBIFC_MISC_CTRL1 0xe805 |
| #define regBIFC_MISC_CTRL1_BASE_IDX 5 |
| #define regBIFC_BME_ERR_LOG_LB 0xe806 |
| #define regBIFC_BME_ERR_LOG_LB_BASE_IDX 5 |
| #define regBIFC_LC_TIMER_CTRL 0xe807 |
| #define regBIFC_LC_TIMER_CTRL_BASE_IDX 5 |
| #define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808 |
| #define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 5 |
| #define regBIFC_RCCBIH_BME_ERR_LOG1 0xe809 |
| #define regBIFC_RCCBIH_BME_ERR_LOG1_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1 0xe80e |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3 0xe80f |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5 0xe810 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7 0xe811 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1 0xe812 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3 0xe813 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5 0xe814 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7 0xe815 |
| #define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a |
| #define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_CNTL2_DEV1 0xe81b |
| #define regBIFC_DMA_ATTR_CNTL2_DEV1_BASE_IDX 5 |
| #define regBIFC_DMA_ATTR_CNTL2_DEV2 0xe81c |
| #define regBIFC_DMA_ATTR_CNTL2_DEV2_BASE_IDX 5 |
| #define regBME_DUMMY_CNTL_0 0xe825 |
| #define regBME_DUMMY_CNTL_0_BASE_IDX 5 |
| #define regBME_DUMMY_CNTL_1 0xe826 |
| #define regBME_DUMMY_CNTL_1_BASE_IDX 5 |
| #define regBIFC_THT_CNTL 0xe827 |
| #define regBIFC_THT_CNTL_BASE_IDX 5 |
| #define regBIFC_HSTARB_CNTL 0xe828 |
| #define regBIFC_HSTARB_CNTL_BASE_IDX 5 |
| #define regBIFC_GSI_CNTL 0xe829 |
| #define regBIFC_GSI_CNTL_BASE_IDX 5 |
| #define regBIFC_PCIEFUNC_CNTL 0xe82a |
| #define regBIFC_PCIEFUNC_CNTL_BASE_IDX 5 |
| #define regBIFC_PASID_CHECK_DIS 0xe82b |
| #define regBIFC_PASID_CHECK_DIS_BASE_IDX 5 |
| #define regBIFC_SDP_CNTL_0 0xe82c |
| #define regBIFC_SDP_CNTL_0_BASE_IDX 5 |
| #define regBIFC_SDP_CNTL_1 0xe82d |
| #define regBIFC_SDP_CNTL_1_BASE_IDX 5 |
| #define regBIFC_PASID_STS 0xe82e |
| #define regBIFC_PASID_STS_BASE_IDX 5 |
| #define regBIFC_ATHUB_ACT_CNTL 0xe82f |
| #define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 5 |
| #define regBIFC_PERF_CNTL_0 0xe830 |
| #define regBIFC_PERF_CNTL_0_BASE_IDX 5 |
| #define regBIFC_PERF_CNTL_1 0xe831 |
| #define regBIFC_PERF_CNTL_1_BASE_IDX 5 |
| #define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832 |
| #define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 5 |
| #define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833 |
| #define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 5 |
| #define regBIFC_PERF_CNT_DMA_RD_L32BIT 0xe834 |
| #define regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 5 |
| #define regBIFC_PERF_CNT_DMA_WR_L32BIT 0xe835 |
| #define regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 5 |
| #define regNBIF_REGIF_ERRSET_CTRL 0xe836 |
| #define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 5 |
| #define regBIFC_SDP_CNTL_2 0xe837 |
| #define regBIFC_SDP_CNTL_2_BASE_IDX 5 |
| #define regNBIF_PGMST_CTRL 0xe838 |
| #define regNBIF_PGMST_CTRL_BASE_IDX 5 |
| #define regNBIF_PGSLV_CTRL 0xe839 |
| #define regNBIF_PGSLV_CTRL_BASE_IDX 5 |
| #define regNBIF_PG_MISC_CTRL 0xe83a |
| #define regNBIF_PG_MISC_CTRL_BASE_IDX 5 |
| #define regNBIF_HST_MISC_CTRL 0xe83b |
| #define regNBIF_HST_MISC_CTRL_BASE_IDX 5 |
| #define regSMN_MST_EP_CNTL3 0xe83c |
| #define regSMN_MST_EP_CNTL3_BASE_IDX 5 |
| #define regSMN_MST_EP_CNTL4 0xe83d |
| #define regSMN_MST_EP_CNTL4_BASE_IDX 5 |
| #define regSMN_MST_CNTL1 0xe83e |
| #define regSMN_MST_CNTL1_BASE_IDX 5 |
| #define regSMN_MST_EP_CNTL5 0xe83f |
| #define regSMN_MST_EP_CNTL5_BASE_IDX 5 |
| #define regBIF_SELFRING_BUFFER_VID 0xe840 |
| #define regBIF_SELFRING_BUFFER_VID_BASE_IDX 5 |
| #define regBIF_SELFRING_VECTOR_CNTL 0xe841 |
| #define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 5 |
| #define regNBIF_STRAP_WRITE_CTRL 0xe845 |
| #define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 5 |
| #define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846 |
| #define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 5 |
| #define regNBIF_PENDING_MISC_CNTL 0xe847 |
| #define regNBIF_PENDING_MISC_CNTL_BASE_IDX 5 |
| #define regBIF_GMI_WRR_WEIGHT 0xe848 |
| #define regBIF_GMI_WRR_WEIGHT_BASE_IDX 5 |
| #define regBIF_GMI_WRR_WEIGHT2 0xe849 |
| #define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 5 |
| #define regBIF_GMI_WRR_WEIGHT3 0xe84a |
| #define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 5 |
| #define regNBIF_PWRBRK_REQUEST 0xe84c |
| #define regNBIF_PWRBRK_REQUEST_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F2 0xe852 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F2_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F3 0xe853 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F3_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F4 0xe854 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F4_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F5 0xe855 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F5_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F6 0xe856 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F6_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F7 0xe857 |
| #define regBIF_ATOMIC_ERR_LOG_DEV0_F7_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV1_F0 0xe858 |
| #define regBIF_ATOMIC_ERR_LOG_DEV1_F0_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV1_F1 0xe859 |
| #define regBIF_ATOMIC_ERR_LOG_DEV1_F1_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F0 0xe85a |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F0_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F1 0xe85b |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F1_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F2 0xe85c |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F2_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F3 0xe85d |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F3_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F4 0xe85e |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F4_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F5 0xe85f |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F5_BASE_IDX 5 |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F6 0xe860 |
| #define regBIF_ATOMIC_ERR_LOG_DEV2_F6_BASE_IDX 5 |
| #define regBIF_DMA_MP4_ERR_LOG 0xe870 |
| #define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 5 |
| #define regBIF_PASID_ERR_LOG 0xe871 |
| #define regBIF_PASID_ERR_LOG_BASE_IDX 5 |
| #define regBIF_PASID_ERR_CLR 0xe872 |
| #define regBIF_PASID_ERR_CLR_BASE_IDX 5 |
| #define regEP0_INTR_URGENT_CAP 0xe875 |
| #define regEP0_INTR_URGENT_CAP_BASE_IDX 5 |
| #define regEP1_INTR_URGENT_CAP 0xe876 |
| #define regEP1_INTR_URGENT_CAP_BASE_IDX 5 |
| #define regEP2_INTR_URGENT_CAP 0xe877 |
| #define regEP2_INTR_URGENT_CAP_BASE_IDX 5 |
| #define regEP_PEND_BLOCK_MSK 0xe87c |
| #define regEP_PEND_BLOCK_MSK_BASE_IDX 5 |
| #define regNBIF_VWIRE_CTRL 0xe880 |
| #define regNBIF_VWIRE_CTRL_BASE_IDX 5 |
| #define regNBIF_SMN_VWR_VCHG_DIS_CTRL 0xe881 |
| #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX 5 |
| #define regNBIF_SMN_VWR_VCHG_RST_CTRL0 0xe882 |
| #define regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX 5 |
| #define regNBIF_SMN_VWR_VCHG_TRIG 0xe884 |
| #define regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX 5 |
| #define regNBIF_SMN_VWR_WTRIG_CNTL 0xe885 |
| #define regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX 5 |
| #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0xe886 |
| #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX 5 |
| #define regNBIF_MGCG_CTRL_LCLK 0xe887 |
| #define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 5 |
| #define regNBIF_DS_CTRL_LCLK 0xe888 |
| #define regNBIF_DS_CTRL_LCLK_BASE_IDX 5 |
| #define regSMN_MST_CNTL0 0xe889 |
| #define regSMN_MST_CNTL0_BASE_IDX 5 |
| #define regSMN_MST_EP_CNTL1 0xe88a |
| #define regSMN_MST_EP_CNTL1_BASE_IDX 5 |
| #define regSMN_MST_EP_CNTL2 0xe88b |
| #define regSMN_MST_EP_CNTL2_BASE_IDX 5 |
| #define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c |
| #define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 5 |
| #define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d |
| #define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 5 |
| #define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e |
| #define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 5 |
| #define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f |
| #define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 5 |
| #define regBIFC_BME_ERR_LOG_HB 0xe8a0 |
| #define regBIFC_BME_ERR_LOG_HB_BASE_IDX 5 |
| #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_HI 0xe8a4 |
| #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_HI_BASE_IDX 5 |
| #define regNBIF_SMN_VWR_VCHG_RST_CTRL0_HI 0xe8a5 |
| #define regNBIF_SMN_VWR_VCHG_RST_CTRL0_HI_BASE_IDX 5 |
| #define regNBIF_SMN_VWR_WTRIG_CNTL_HI 0xe8a6 |
| #define regNBIF_SMN_VWR_WTRIG_CNTL_HI_BASE_IDX 5 |
| #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_HI 0xe8a7 |
| #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_HI_BASE_IDX 5 |
| #define regNBIF_SMN_VWR_VCHG_TRIG_HI 0xe8a8 |
| #define regNBIF_SMN_VWR_VCHG_TRIG_HI_BASE_IDX 5 |
| #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0 |
| #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 |
| #define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1 |
| #define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 |
| #define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2 |
| #define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 5 |
| #define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3 |
| #define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 5 |
| #define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC 0xe8c4 |
| #define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX 5 |
| #define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC 0xe8c5 |
| #define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX 5 |
| #define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6 |
| #define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 5 |
| #define regBIFC_PCIE_BDF_CNTL0 0xe8d0 |
| #define regBIFC_PCIE_BDF_CNTL0_BASE_IDX 5 |
| #define regBIFC_PCIE_BDF_CNTL1 0xe8d1 |
| #define regBIFC_PCIE_BDF_CNTL1_BASE_IDX 5 |
| #define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2 |
| #define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 5 |
| #define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0 |
| #define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 5 |
| #define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1 |
| #define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 5 |
| #define regBIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2 |
| #define regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 5 |
| #define regBIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3 |
| #define regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk |
| // base address: 0x10100000 |
| #define regHARD_RST_CTRL 0xe000 |
| #define regHARD_RST_CTRL_BASE_IDX 5 |
| #define regSELF_SOFT_RST 0xe002 |
| #define regSELF_SOFT_RST_BASE_IDX 5 |
| #define regBIF_GFX_DRV_VPU_RST 0xe003 |
| #define regBIF_GFX_DRV_VPU_RST_BASE_IDX 5 |
| #define regBIF_RST_MISC_CTRL 0xe004 |
| #define regBIF_RST_MISC_CTRL_BASE_IDX 5 |
| #define regBIF_RST_MISC_CTRL2 0xe005 |
| #define regBIF_RST_MISC_CTRL2_BASE_IDX 5 |
| #define regBIF_RST_MISC_CTRL3 0xe006 |
| #define regBIF_RST_MISC_CTRL3_BASE_IDX 5 |
| #define regDEV0_PF0_FLR_RST_CTRL 0xe008 |
| #define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF1_FLR_RST_CTRL 0xe009 |
| #define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF2_FLR_RST_CTRL 0xe00a |
| #define regDEV0_PF2_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF3_FLR_RST_CTRL 0xe00b |
| #define regDEV0_PF3_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF4_FLR_RST_CTRL 0xe00c |
| #define regDEV0_PF4_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF5_FLR_RST_CTRL 0xe00d |
| #define regDEV0_PF5_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF6_FLR_RST_CTRL 0xe00e |
| #define regDEV0_PF6_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF7_FLR_RST_CTRL 0xe00f |
| #define regDEV0_PF7_FLR_RST_CTRL_BASE_IDX 5 |
| #define regBIF_INST_RESET_INTR_STS 0xe010 |
| #define regBIF_INST_RESET_INTR_STS_BASE_IDX 5 |
| #define regBIF_PF_FLR_INTR_STS 0xe011 |
| #define regBIF_PF_FLR_INTR_STS_BASE_IDX 5 |
| #define regBIF_D3HOTD0_INTR_STS 0xe012 |
| #define regBIF_D3HOTD0_INTR_STS_BASE_IDX 5 |
| #define regBIF_POWER_INTR_STS 0xe014 |
| #define regBIF_POWER_INTR_STS_BASE_IDX 5 |
| #define regBIF_PF_DSTATE_INTR_STS 0xe015 |
| #define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 5 |
| #define regSELF_SOFT_RST_2 0xe016 |
| #define regSELF_SOFT_RST_2_BASE_IDX 5 |
| #define regBIF_INST_RESET_INTR_MASK 0xe020 |
| #define regBIF_INST_RESET_INTR_MASK_BASE_IDX 5 |
| #define regBIF_PF_FLR_INTR_MASK 0xe021 |
| #define regBIF_PF_FLR_INTR_MASK_BASE_IDX 5 |
| #define regBIF_D3HOTD0_INTR_MASK 0xe022 |
| #define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 5 |
| #define regBIF_POWER_INTR_MASK 0xe024 |
| #define regBIF_POWER_INTR_MASK_BASE_IDX 5 |
| #define regBIF_PF_DSTATE_INTR_MASK 0xe025 |
| #define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 5 |
| #define regBIF_PF_FLR_RST 0xe040 |
| #define regBIF_PF_FLR_RST_BASE_IDX 5 |
| #define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050 |
| #define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051 |
| #define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV0_PF2_DSTATE_VALUE 0xe052 |
| #define regBIF_DEV0_PF2_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV0_PF3_DSTATE_VALUE 0xe053 |
| #define regBIF_DEV0_PF3_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV0_PF4_DSTATE_VALUE 0xe054 |
| #define regBIF_DEV0_PF4_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV0_PF5_DSTATE_VALUE 0xe055 |
| #define regBIF_DEV0_PF5_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV0_PF6_DSTATE_VALUE 0xe056 |
| #define regBIF_DEV0_PF6_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV0_PF7_DSTATE_VALUE 0xe057 |
| #define regBIF_DEV0_PF7_DSTATE_VALUE_BASE_IDX 5 |
| #define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe078 |
| #define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe079 |
| #define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF2_D3HOTD0_RST_CTRL 0xe07a |
| #define regDEV0_PF2_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF3_D3HOTD0_RST_CTRL 0xe07b |
| #define regDEV0_PF3_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF4_D3HOTD0_RST_CTRL 0xe07c |
| #define regDEV0_PF4_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF5_D3HOTD0_RST_CTRL 0xe07d |
| #define regDEV0_PF5_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF6_D3HOTD0_RST_CTRL 0xe07e |
| #define regDEV0_PF6_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV0_PF7_D3HOTD0_RST_CTRL 0xe07f |
| #define regDEV0_PF7_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV1_PF0_FLR_RST_CTRL 0xe200 |
| #define regDEV1_PF0_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV1_PF1_FLR_RST_CTRL 0xe201 |
| #define regDEV1_PF1_FLR_RST_CTRL_BASE_IDX 5 |
| #define regBIF_DEV1_PF0_DSTATE_VALUE 0xe208 |
| #define regBIF_DEV1_PF0_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV1_PF1_DSTATE_VALUE 0xe209 |
| #define regBIF_DEV1_PF1_DSTATE_VALUE_BASE_IDX 5 |
| #define regDEV1_PF0_D3HOTD0_RST_CTRL 0xe210 |
| #define regDEV1_PF0_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV1_PF1_D3HOTD0_RST_CTRL 0xe211 |
| #define regDEV1_PF1_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF0_FLR_RST_CTRL 0xe218 |
| #define regDEV2_PF0_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF1_FLR_RST_CTRL 0xe219 |
| #define regDEV2_PF1_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF2_FLR_RST_CTRL 0xe21a |
| #define regDEV2_PF2_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF3_FLR_RST_CTRL 0xe21b |
| #define regDEV2_PF3_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF4_FLR_RST_CTRL 0xe21c |
| #define regDEV2_PF4_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF5_FLR_RST_CTRL 0xe21d |
| #define regDEV2_PF5_FLR_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF6_FLR_RST_CTRL 0xe21e |
| #define regDEV2_PF6_FLR_RST_CTRL_BASE_IDX 5 |
| #define regBIF_DEV2_PF0_DSTATE_VALUE 0xe220 |
| #define regBIF_DEV2_PF0_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV2_PF1_DSTATE_VALUE 0xe221 |
| #define regBIF_DEV2_PF1_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV2_PF2_DSTATE_VALUE 0xe222 |
| #define regBIF_DEV2_PF2_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV2_PF3_DSTATE_VALUE 0xe223 |
| #define regBIF_DEV2_PF3_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV2_PF4_DSTATE_VALUE 0xe224 |
| #define regBIF_DEV2_PF4_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV2_PF5_DSTATE_VALUE 0xe225 |
| #define regBIF_DEV2_PF5_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_DEV2_PF6_DSTATE_VALUE 0xe226 |
| #define regBIF_DEV2_PF6_DSTATE_VALUE_BASE_IDX 5 |
| #define regDEV2_PF0_D3HOTD0_RST_CTRL 0xe228 |
| #define regDEV2_PF0_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF1_D3HOTD0_RST_CTRL 0xe229 |
| #define regDEV2_PF1_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF2_D3HOTD0_RST_CTRL 0xe22a |
| #define regDEV2_PF2_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF3_D3HOTD0_RST_CTRL 0xe22b |
| #define regDEV2_PF3_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF4_D3HOTD0_RST_CTRL 0xe22c |
| #define regDEV2_PF4_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF5_D3HOTD0_RST_CTRL 0xe22d |
| #define regDEV2_PF5_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regDEV2_PF6_D3HOTD0_RST_CTRL 0xe22e |
| #define regDEV2_PF6_D3HOTD0_RST_CTRL_BASE_IDX 5 |
| #define regBIF_PORT0_DSTATE_VALUE 0xe230 |
| #define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_PORT1_DSTATE_VALUE 0xe231 |
| #define regBIF_PORT1_DSTATE_VALUE_BASE_IDX 5 |
| #define regBIF_PORT2_DSTATE_VALUE 0xe232 |
| #define regBIF_PORT2_DSTATE_VALUE_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk |
| // base address: 0x10100000 |
| #define regBIFL_RAS_CENTRAL_CNTL 0xe400 |
| #define regBIFL_RAS_CENTRAL_CNTL_BASE_IDX 5 |
| #define regBIFL_RAS_CENTRAL_STATUS 0xe410 |
| #define regBIFL_RAS_CENTRAL_STATUS_BASE_IDX 5 |
| #define regBIFL_RAS_LEAF0_CTRL 0xe420 |
| #define regBIFL_RAS_LEAF0_CTRL_BASE_IDX 5 |
| #define regBIFL_RAS_LEAF1_CTRL 0xe421 |
| #define regBIFL_RAS_LEAF1_CTRL_BASE_IDX 5 |
| #define regBIFL_RAS_LEAF2_CTRL 0xe422 |
| #define regBIFL_RAS_LEAF2_CTRL_BASE_IDX 5 |
| #define regBIFL_RAS_LEAF0_STATUS 0xe430 |
| #define regBIFL_RAS_LEAF0_STATUS_BASE_IDX 5 |
| #define regBIFL_RAS_LEAF1_STATUS 0xe431 |
| #define regBIFL_RAS_LEAF1_STATUS_BASE_IDX 5 |
| #define regBIFL_RAS_LEAF2_STATUS 0xe432 |
| #define regBIFL_RAS_LEAF2_STATUS_BASE_IDX 5 |
| #define regBIFL_IOHUB_RAS_IH_CNTL 0xe7fe |
| #define regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX 5 |
| #define regBIFL_RAS_VWR_FROM_IOHUB 0xe7ff |
| #define regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_nbif_sion_SIONDEC |
| // base address: 0x10100000 |
| #define regSION_CL0_RdRsp_BurstTarget_REG0 0xe900 |
| #define regSION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX 5 |
| #define regSION_CL0_RdRsp_BurstTarget_REG1 0xe901 |
| #define regSION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX 5 |
| #define regSION_CL0_RdRsp_TimeSlot_REG0 0xe902 |
| #define regSION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX 5 |
| #define regSION_CL0_RdRsp_TimeSlot_REG1 0xe903 |
| #define regSION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX 5 |
| #define regSION_CL0_WrRsp_BurstTarget_REG0 0xe904 |
| #define regSION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX 5 |
| #define regSION_CL0_WrRsp_BurstTarget_REG1 0xe905 |
| #define regSION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX 5 |
| #define regSION_CL0_WrRsp_TimeSlot_REG0 0xe906 |
| #define regSION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX 5 |
| #define regSION_CL0_WrRsp_TimeSlot_REG1 0xe907 |
| #define regSION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX 5 |
| #define regSION_CL0_Req_BurstTarget_REG0 0xe908 |
| #define regSION_CL0_Req_BurstTarget_REG0_BASE_IDX 5 |
| #define regSION_CL0_Req_BurstTarget_REG1 0xe909 |
| #define regSION_CL0_Req_BurstTarget_REG1_BASE_IDX 5 |
| #define regSION_CL0_Req_TimeSlot_REG0 0xe90a |
| #define regSION_CL0_Req_TimeSlot_REG0_BASE_IDX 5 |
| #define regSION_CL0_Req_TimeSlot_REG1 0xe90b |
| #define regSION_CL0_Req_TimeSlot_REG1_BASE_IDX 5 |
| #define regSION_CL0_ReqPoolCredit_Alloc_REG0 0xe90c |
| #define regSION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX 5 |
| #define regSION_CL0_ReqPoolCredit_Alloc_REG1 0xe90d |
| #define regSION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX 5 |
| #define regSION_CL0_DataPoolCredit_Alloc_REG0 0xe90e |
| #define regSION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX 5 |
| #define regSION_CL0_DataPoolCredit_Alloc_REG1 0xe90f |
| #define regSION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX 5 |
| #define regSION_CL0_RdRspPoolCredit_Alloc_REG0 0xe910 |
| #define regSION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX 5 |
| #define regSION_CL0_RdRspPoolCredit_Alloc_REG1 0xe911 |
| #define regSION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX 5 |
| #define regSION_CL0_WrRspPoolCredit_Alloc_REG0 0xe912 |
| #define regSION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX 5 |
| #define regSION_CL0_WrRspPoolCredit_Alloc_REG1 0xe913 |
| #define regSION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX 5 |
| #define regSION_CL1_RdRsp_BurstTarget_REG0 0xe914 |
| #define regSION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX 5 |
| #define regSION_CL1_RdRsp_BurstTarget_REG1 0xe915 |
| #define regSION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX 5 |
| #define regSION_CL1_RdRsp_TimeSlot_REG0 0xe916 |
| #define regSION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX 5 |
| #define regSION_CL1_RdRsp_TimeSlot_REG1 0xe917 |
| #define regSION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX 5 |
| #define regSION_CL1_WrRsp_BurstTarget_REG0 0xe918 |
| #define regSION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX 5 |
| #define regSION_CL1_WrRsp_BurstTarget_REG1 0xe919 |
| #define regSION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX 5 |
| #define regSION_CL1_WrRsp_TimeSlot_REG0 0xe91a |
| #define regSION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX 5 |
| #define regSION_CL1_WrRsp_TimeSlot_REG1 0xe91b |
| #define regSION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX 5 |
| #define regSION_CL1_Req_BurstTarget_REG0 0xe91c |
| #define regSION_CL1_Req_BurstTarget_REG0_BASE_IDX 5 |
| #define regSION_CL1_Req_BurstTarget_REG1 0xe91d |
| #define regSION_CL1_Req_BurstTarget_REG1_BASE_IDX 5 |
| #define regSION_CL1_Req_TimeSlot_REG0 0xe91e |
| #define regSION_CL1_Req_TimeSlot_REG0_BASE_IDX 5 |
| #define regSION_CL1_Req_TimeSlot_REG1 0xe91f |
| #define regSION_CL1_Req_TimeSlot_REG1_BASE_IDX 5 |
| #define regSION_CL1_ReqPoolCredit_Alloc_REG0 0xe920 |
| #define regSION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX 5 |
| #define regSION_CL1_ReqPoolCredit_Alloc_REG1 0xe921 |
| #define regSION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX 5 |
| #define regSION_CL1_DataPoolCredit_Alloc_REG0 0xe922 |
| #define regSION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX 5 |
| #define regSION_CL1_DataPoolCredit_Alloc_REG1 0xe923 |
| #define regSION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX 5 |
| #define regSION_CL1_RdRspPoolCredit_Alloc_REG0 0xe924 |
| #define regSION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX 5 |
| #define regSION_CL1_RdRspPoolCredit_Alloc_REG1 0xe925 |
| #define regSION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX 5 |
| #define regSION_CL1_WrRspPoolCredit_Alloc_REG0 0xe926 |
| #define regSION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX 5 |
| #define regSION_CL1_WrRspPoolCredit_Alloc_REG1 0xe927 |
| #define regSION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX 5 |
| #define regSION_CL2_RdRsp_BurstTarget_REG0 0xe928 |
| #define regSION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX 5 |
| #define regSION_CL2_RdRsp_BurstTarget_REG1 0xe929 |
| #define regSION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX 5 |
| #define regSION_CL2_RdRsp_TimeSlot_REG0 0xe92a |
| #define regSION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX 5 |
| #define regSION_CL2_RdRsp_TimeSlot_REG1 0xe92b |
| #define regSION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX 5 |
| #define regSION_CL2_WrRsp_BurstTarget_REG0 0xe92c |
| #define regSION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX 5 |
| #define regSION_CL2_WrRsp_BurstTarget_REG1 0xe92d |
| #define regSION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX 5 |
| #define regSION_CL2_WrRsp_TimeSlot_REG0 0xe92e |
| #define regSION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX 5 |
| #define regSION_CL2_WrRsp_TimeSlot_REG1 0xe92f |
| #define regSION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX 5 |
| #define regSION_CL2_Req_BurstTarget_REG0 0xe930 |
| #define regSION_CL2_Req_BurstTarget_REG0_BASE_IDX 5 |
| #define regSION_CL2_Req_BurstTarget_REG1 0xe931 |
| #define regSION_CL2_Req_BurstTarget_REG1_BASE_IDX 5 |
| #define regSION_CL2_Req_TimeSlot_REG0 0xe932 |
| #define regSION_CL2_Req_TimeSlot_REG0_BASE_IDX 5 |
| #define regSION_CL2_Req_TimeSlot_REG1 0xe933 |
| #define regSION_CL2_Req_TimeSlot_REG1_BASE_IDX 5 |
| #define regSION_CL2_ReqPoolCredit_Alloc_REG0 0xe934 |
| #define regSION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX 5 |
| #define regSION_CL2_ReqPoolCredit_Alloc_REG1 0xe935 |
| #define regSION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX 5 |
| #define regSION_CL2_DataPoolCredit_Alloc_REG0 0xe936 |
| #define regSION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX 5 |
| #define regSION_CL2_DataPoolCredit_Alloc_REG1 0xe937 |
| #define regSION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX 5 |
| #define regSION_CL2_RdRspPoolCredit_Alloc_REG0 0xe938 |
| #define regSION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX 5 |
| #define regSION_CL2_RdRspPoolCredit_Alloc_REG1 0xe939 |
| #define regSION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX 5 |
| #define regSION_CL2_WrRspPoolCredit_Alloc_REG0 0xe93a |
| #define regSION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX 5 |
| #define regSION_CL2_WrRspPoolCredit_Alloc_REG1 0xe93b |
| #define regSION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX 5 |
| #define regSION_CNTL_REG0 0xe93c |
| #define regSION_CNTL_REG0_BASE_IDX 5 |
| #define regSION_CNTL_REG1 0xe93d |
| #define regSION_CNTL_REG1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
| // base address: 0x10140000 |
| #define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x10000 |
| #define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x10000 |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_COMMAND 0x10001 |
| #define regBIF_CFG_DEV0_EPF0_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_STATUS 0x10001 |
| #define regBIF_CFG_DEV0_EPF0_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x10002 |
| #define regBIF_CFG_DEV0_EPF0_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x10002 |
| #define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x10002 |
| #define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x10002 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x10003 |
| #define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LATENCY 0x10003 |
| #define regBIF_CFG_DEV0_EPF0_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_HEADER 0x10003 |
| #define regBIF_CFG_DEV0_EPF0_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_BIST 0x10003 |
| #define regBIF_CFG_DEV0_EPF0_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x10004 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x10005 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x10006 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x10007 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x10008 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x10009 |
| #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0x1000a |
| #define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x1000b |
| #define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x1000c |
| #define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x1000d |
| #define regBIF_CFG_DEV0_EPF0_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x1000f |
| #define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x1000f |
| #define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x1000f |
| #define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x1000f |
| #define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x10012 |
| #define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x10013 |
| #define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x10014 |
| #define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x10014 |
| #define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x10015 |
| #define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x10019 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x10019 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x1001a |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x1001b |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x1001b |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x1001c |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x1001d |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x1001d |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x10022 |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x10023 |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x10023 |
| #define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x10024 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x10025 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x10025 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x10028 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x10028 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x10029 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x1002a |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x1002a |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA 0x1002a |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x1002b |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x1002b |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 0x1002b |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x1002c |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x1002c |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x1002d |
| #define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x10030 |
| #define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x10030 |
| #define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x10031 |
| #define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x10032 |
| #define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x10042 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x10043 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x10044 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x10045 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x10046 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x10047 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x10047 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x10048 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x10049 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x1004a |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x1004b |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x1004c |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x1004d |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10050 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x10051 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x10052 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10054 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x10055 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x10056 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x10057 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x10058 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x10059 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x1005a |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x1005b |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x1005c |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x1005d |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x1005e |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x10062 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x10063 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x10064 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x10065 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x10080 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x10081 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x10082 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x10083 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x10084 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x10085 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x10086 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x10087 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x10088 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x10089 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x1008a |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x1008b |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x1008c |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10090 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x10091 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x10092 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x10093 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x10094 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x10095 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x10096 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x10097 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x10097 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10098 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10098 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10098 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10098 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10099 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10099 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10099 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10099 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x1009c |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x1009d |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x1009e |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1009f |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1009f |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x100a0 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x100a0 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x100a1 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x100a1 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x100a2 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x100a2 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x100a3 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x100a3 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x100a4 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x100a4 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x100a5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x100a5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x100a6 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x100a6 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x100a8 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x100a9 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x100a9 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x100ac |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x100ad |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x100ad |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x100b0 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x100b1 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x100b1 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x100b2 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x100b3 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x100b4 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x100b5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x100b5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x100bc |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x100bd |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x100bd |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x100be |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x100bf |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x100c0 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x100c1 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x100c2 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x100c3 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x100c4 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x100c5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x100c8 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x100c9 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x100ca |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x100cb |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x100cb |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x100cc |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x100cd |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x100ce |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x100ce |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x100cf |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x100cf |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x100d0 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x100d0 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x100d1 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x100d1 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x100d2 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x100d3 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x100d4 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x100d5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x100d6 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x100d7 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x100d8 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x100d9 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x100da |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x100db |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x10100 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x10101 |
| #define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x10102 |
| #define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x10104 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x10105 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x10106 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x10107 |
| #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10108 |
| #define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10109 |
| #define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1010a |
| #define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x1010c |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x1010c |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x1010c |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x1010c |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x1010d |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x1010d |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x1010d |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x1010d |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x1010e |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x1010e |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x1010e |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x1010e |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x1010f |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x1010f |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x1010f |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x1010f |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x10114 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x10115 |
| #define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x10115 |
| #define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x10116 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x10116 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x10117 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x10117 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x10118 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x10118 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x10119 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x10119 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x1011a |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x1011a |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x1011b |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x1011b |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x1011c |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x1011c |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x1011d |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x1011d |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x1011e |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x1011e |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x1011f |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x1011f |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x10120 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x10120 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x10121 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x10121 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x10122 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x10122 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x10123 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x10123 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x10124 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x10124 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x10125 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x10125 |
| #define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10130 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0x10131 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0x10132 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0x10133 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0x10134 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0x10135 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0x10136 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0x10137 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0x10138 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0x10139 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0x1013a |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0x1013b |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0x1013c |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x10160 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x10161 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x10162 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x10163 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x10164 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x10165 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x10166 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x10167 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x10168 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x10169 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x1016a |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x1016b |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x1016c |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x1016d |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x1016e |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x1016f |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x10170 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x10171 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x10172 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x10173 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x10174 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x10175 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x10176 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x10177 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x10178 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x10179 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x1017a |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x1017b |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x1017c |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x1017d |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x1017e |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x1017f |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x10180 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x10181 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x10182 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x10183 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x10184 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x10185 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x10186 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x10187 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x10188 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x10189 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x1018a |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x1018b |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x1018c |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x10190 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x10191 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x10192 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x10193 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x10194 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x10195 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x10196 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x10197 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x10198 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x1019c |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x1019d |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x1019e |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x1019f |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x101a0 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x101a1 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x101a2 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x101a3 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x101a4 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x101a8 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x101a9 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x101aa |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x101ab |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x101ac |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x101ad |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x101ae |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x101af |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x101b0 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x101b4 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x101b5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x101b6 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x101b7 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x101b8 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x101b9 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x101ba |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x101bb |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x101bc |
| #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
| // base address: 0x10141000 |
| #define regBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x10400 |
| #define regBIF_CFG_DEV0_EPF1_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x10400 |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_COMMAND 0x10401 |
| #define regBIF_CFG_DEV0_EPF1_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_STATUS 0x10401 |
| #define regBIF_CFG_DEV0_EPF1_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x10402 |
| #define regBIF_CFG_DEV0_EPF1_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x10402 |
| #define regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x10402 |
| #define regBIF_CFG_DEV0_EPF1_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x10402 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x10403 |
| #define regBIF_CFG_DEV0_EPF1_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LATENCY 0x10403 |
| #define regBIF_CFG_DEV0_EPF1_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_HEADER 0x10403 |
| #define regBIF_CFG_DEV0_EPF1_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_BIST 0x10403 |
| #define regBIF_CFG_DEV0_EPF1_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x10404 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x10405 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x10406 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x10407 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x10408 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x10409 |
| #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR 0x1040a |
| #define regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x1040b |
| #define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x1040c |
| #define regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x1040d |
| #define regBIF_CFG_DEV0_EPF1_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x1040f |
| #define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x1040f |
| #define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x1040f |
| #define regBIF_CFG_DEV0_EPF1_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x1040f |
| #define regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x10412 |
| #define regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x10413 |
| #define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x10414 |
| #define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x10414 |
| #define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x10415 |
| #define regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x10419 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x10419 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x1041a |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x1041b |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x1041b |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x1041c |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x1041d |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x1041d |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x10422 |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x10423 |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x10423 |
| #define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x10424 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x10425 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x10425 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x10428 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x10428 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x10429 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x1042a |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x1042a |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA 0x1042a |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x1042b |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x1042b |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 0x1042b |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x1042c |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x1042c |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x1042d |
| #define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x10430 |
| #define regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x10430 |
| #define regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x10431 |
| #define regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x10432 |
| #define regBIF_CFG_DEV0_EPF1_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x10441 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x10442 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x10443 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10450 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x10451 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x10452 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10454 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x10455 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x10456 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x10457 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x10458 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x10459 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x1045a |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x1045b |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x1045c |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x1045d |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x1045e |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x10462 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x10463 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x10464 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x10465 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x10480 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x10481 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x10482 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x10483 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x10484 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x10485 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x10486 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x10487 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x10488 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x10489 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x1048a |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x1048b |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x1048c |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10490 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x10491 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x10492 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x10493 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x10494 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x10495 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x10496 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x10497 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x10497 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10498 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10498 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10498 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10498 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10499 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10499 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10499 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10499 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x1049c |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x1049d |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x1049e |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1049f |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1049f |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x104a0 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x104a0 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x104a1 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x104a1 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x104a2 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x104a2 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x104a3 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x104a3 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x104a4 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x104a4 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x104a5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x104a5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x104a6 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x104a6 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x104a8 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x104a9 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x104a9 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x104ac |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x104ad |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x104ad |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x104b0 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x104b1 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x104b1 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x104b2 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x104b3 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x104b4 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x104b5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x104b5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x104bc |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x104bd |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x104bd |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x104be |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x104bf |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x104c0 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x104c1 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x104c2 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x104c3 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x104c4 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x104c5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x104c8 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x104c9 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x104ca |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x104cb |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x104cb |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x104cc |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x104cd |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x104ce |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x104ce |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x104cf |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x104cf |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x104d0 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x104d0 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x104d1 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x104d1 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x104d2 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x104d3 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x104d4 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x104d5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x104d6 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x104d7 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x104d8 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x104d9 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x104da |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x104db |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST 0x10500 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP 0x10501 |
| #define regBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS 0x10502 |
| #define regBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x10504 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT 0x10505 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT 0x10506 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT 0x10507 |
| #define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10508 |
| #define regBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10509 |
| #define regBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1050a |
| #define regBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT 0x1050c |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT 0x1050c |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT 0x1050c |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT 0x1050c |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT 0x1050d |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT 0x1050d |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT 0x1050d |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT 0x1050d |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT 0x1050e |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT 0x1050e |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT 0x1050e |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT 0x1050e |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT 0x1050f |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT 0x1050f |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT 0x1050f |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT 0x1050f |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST 0x10514 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP 0x10515 |
| #define regBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS 0x10515 |
| #define regBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL 0x10516 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS 0x10516 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL 0x10517 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS 0x10517 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL 0x10518 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS 0x10518 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL 0x10519 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS 0x10519 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL 0x1051a |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS 0x1051a |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL 0x1051b |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS 0x1051b |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL 0x1051c |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS 0x1051c |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL 0x1051d |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS 0x1051d |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL 0x1051e |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS 0x1051e |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL 0x1051f |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS 0x1051f |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL 0x10520 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS 0x10520 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL 0x10521 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS 0x10521 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL 0x10522 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS 0x10522 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL 0x10523 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS 0x10523 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL 0x10524 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS 0x10524 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL 0x10525 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS 0x10525 |
| #define regBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x10530 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP 0x10531 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL 0x10532 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP 0x10533 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL 0x10534 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP 0x10535 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL 0x10536 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP 0x10537 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL 0x10538 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP 0x10539 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL 0x1053a |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP 0x1053b |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL 0x1053c |
| #define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
| // base address: 0x10142000 |
| #define regBIF_CFG_DEV0_EPF2_0_VENDOR_ID 0x10800 |
| #define regBIF_CFG_DEV0_EPF2_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_ID 0x10800 |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_COMMAND 0x10801 |
| #define regBIF_CFG_DEV0_EPF2_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_STATUS 0x10801 |
| #define regBIF_CFG_DEV0_EPF2_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_REVISION_ID 0x10802 |
| #define regBIF_CFG_DEV0_EPF2_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE 0x10802 |
| #define regBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_SUB_CLASS 0x10802 |
| #define regBIF_CFG_DEV0_EPF2_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_CLASS 0x10802 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_CACHE_LINE 0x10803 |
| #define regBIF_CFG_DEV0_EPF2_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_LATENCY 0x10803 |
| #define regBIF_CFG_DEV0_EPF2_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_HEADER 0x10803 |
| #define regBIF_CFG_DEV0_EPF2_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_BIST 0x10803 |
| #define regBIF_CFG_DEV0_EPF2_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 0x10804 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 0x10805 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 0x10806 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 0x10807 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 0x10808 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 0x10809 |
| #define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR 0x1080a |
| #define regBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_ADAPTER_ID 0x1080b |
| #define regBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR 0x1080c |
| #define regBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_CAP_PTR 0x1080d |
| #define regBIF_CFG_DEV0_EPF2_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE 0x1080f |
| #define regBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN 0x1080f |
| #define regBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MIN_GRANT 0x1080f |
| #define regBIF_CFG_DEV0_EPF2_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MAX_LATENCY 0x1080f |
| #define regBIF_CFG_DEV0_EPF2_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST 0x10812 |
| #define regBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W 0x10813 |
| #define regBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST 0x10814 |
| #define regBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PMI_CAP 0x10814 |
| #define regBIF_CFG_DEV0_EPF2_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL 0x10815 |
| #define regBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_SBRN 0x10818 |
| #define regBIF_CFG_DEV0_EPF2_0_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_FLADJ 0x10818 |
| #define regBIF_CFG_DEV0_EPF2_0_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD 0x10818 |
| #define regBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST 0x10819 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_CAP 0x10819 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_CAP 0x1081a |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL 0x1081b |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS 0x1081b |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_LINK_CAP 0x1081c |
| #define regBIF_CFG_DEV0_EPF2_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_LINK_CNTL 0x1081d |
| #define regBIF_CFG_DEV0_EPF2_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_LINK_STATUS 0x1081d |
| #define regBIF_CFG_DEV0_EPF2_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 0x10822 |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 0x10823 |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 0x10823 |
| #define regBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_LINK_CAP2 0x10824 |
| #define regBIF_CFG_DEV0_EPF2_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_LINK_CNTL2 0x10825 |
| #define regBIF_CFG_DEV0_EPF2_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_LINK_STATUS2 0x10825 |
| #define regBIF_CFG_DEV0_EPF2_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST 0x10828 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL 0x10828 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO 0x10829 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI 0x1082a |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA 0x1082a |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA 0x1082a |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MASK 0x1082b |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 0x1082b |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64 0x1082b |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MASK_64 0x1082c |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_PENDING 0x1082c |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 0x1082d |
| #define regBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST 0x10830 |
| #define regBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL 0x10830 |
| #define regBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSIX_TABLE 0x10831 |
| #define regBIF_CFG_DEV0_EPF2_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_MSIX_PBA 0x10832 |
| #define regBIF_CFG_DEV0_EPF2_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10840 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x10841 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 0x10842 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 0x10843 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10854 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS 0x10855 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK 0x10856 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0x10857 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS 0x10858 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK 0x10859 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0x1085a |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 0x1085b |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 0x1085c |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 0x1085d |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 0x1085e |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 0x10862 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 0x10863 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 0x10864 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 0x10865 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0x10880 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP 0x10881 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL 0x10882 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP 0x10883 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL 0x10884 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP 0x10885 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL 0x10886 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP 0x10887 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL 0x10888 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP 0x10889 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL 0x1088a |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP 0x1088b |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL 0x1088c |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10890 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0x10891 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA 0x10892 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0x10893 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0x10894 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP 0x10895 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0x10896 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS 0x10897 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL 0x10897 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10898 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10898 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10898 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10898 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10899 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10899 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10899 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10899 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0x108a8 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP 0x108a9 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL 0x108a9 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST 0x108b4 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP 0x108b5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL 0x108b5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0x108ca |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP 0x108cb |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL 0x108cb |
| #define regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
| // base address: 0x10143000 |
| #define regBIF_CFG_DEV0_EPF3_0_VENDOR_ID 0x10c00 |
| #define regBIF_CFG_DEV0_EPF3_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_ID 0x10c00 |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_COMMAND 0x10c01 |
| #define regBIF_CFG_DEV0_EPF3_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_STATUS 0x10c01 |
| #define regBIF_CFG_DEV0_EPF3_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_REVISION_ID 0x10c02 |
| #define regBIF_CFG_DEV0_EPF3_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE 0x10c02 |
| #define regBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_SUB_CLASS 0x10c02 |
| #define regBIF_CFG_DEV0_EPF3_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_CLASS 0x10c02 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_CACHE_LINE 0x10c03 |
| #define regBIF_CFG_DEV0_EPF3_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_LATENCY 0x10c03 |
| #define regBIF_CFG_DEV0_EPF3_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_HEADER 0x10c03 |
| #define regBIF_CFG_DEV0_EPF3_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_BIST 0x10c03 |
| #define regBIF_CFG_DEV0_EPF3_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 0x10c04 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 0x10c05 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 0x10c06 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 0x10c07 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 0x10c08 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 0x10c09 |
| #define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR 0x10c0a |
| #define regBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_ADAPTER_ID 0x10c0b |
| #define regBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR 0x10c0c |
| #define regBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_CAP_PTR 0x10c0d |
| #define regBIF_CFG_DEV0_EPF3_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE 0x10c0f |
| #define regBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN 0x10c0f |
| #define regBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MIN_GRANT 0x10c0f |
| #define regBIF_CFG_DEV0_EPF3_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MAX_LATENCY 0x10c0f |
| #define regBIF_CFG_DEV0_EPF3_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST 0x10c12 |
| #define regBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W 0x10c13 |
| #define regBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST 0x10c14 |
| #define regBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PMI_CAP 0x10c14 |
| #define regBIF_CFG_DEV0_EPF3_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL 0x10c15 |
| #define regBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_SBRN 0x10c18 |
| #define regBIF_CFG_DEV0_EPF3_0_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_FLADJ 0x10c18 |
| #define regBIF_CFG_DEV0_EPF3_0_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD 0x10c18 |
| #define regBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST 0x10c19 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_CAP 0x10c19 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_CAP 0x10c1a |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL 0x10c1b |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS 0x10c1b |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_LINK_CAP 0x10c1c |
| #define regBIF_CFG_DEV0_EPF3_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_LINK_CNTL 0x10c1d |
| #define regBIF_CFG_DEV0_EPF3_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_LINK_STATUS 0x10c1d |
| #define regBIF_CFG_DEV0_EPF3_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 0x10c22 |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 0x10c23 |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 0x10c23 |
| #define regBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_LINK_CAP2 0x10c24 |
| #define regBIF_CFG_DEV0_EPF3_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_LINK_CNTL2 0x10c25 |
| #define regBIF_CFG_DEV0_EPF3_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_LINK_STATUS2 0x10c25 |
| #define regBIF_CFG_DEV0_EPF3_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST 0x10c28 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL 0x10c28 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO 0x10c29 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI 0x10c2a |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA 0x10c2a |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA 0x10c2a |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MASK 0x10c2b |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 0x10c2b |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64 0x10c2b |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MASK_64 0x10c2c |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_PENDING 0x10c2c |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 0x10c2d |
| #define regBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST 0x10c30 |
| #define regBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL 0x10c30 |
| #define regBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSIX_TABLE 0x10c31 |
| #define regBIF_CFG_DEV0_EPF3_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_MSIX_PBA 0x10c32 |
| #define regBIF_CFG_DEV0_EPF3_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10c40 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x10c41 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 0x10c42 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 0x10c43 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10c54 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS 0x10c55 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK 0x10c56 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY 0x10c57 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS 0x10c58 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK 0x10c59 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL 0x10c5a |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 0x10c5b |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 0x10c5c |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 0x10c5d |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 0x10c5e |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 0x10c62 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 0x10c63 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 0x10c64 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 0x10c65 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST 0x10c80 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP 0x10c81 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL 0x10c82 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP 0x10c83 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL 0x10c84 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP 0x10c85 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL 0x10c86 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP 0x10c87 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL 0x10c88 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP 0x10c89 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL 0x10c8a |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP 0x10c8b |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL 0x10c8c |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10c90 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT 0x10c91 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA 0x10c92 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP 0x10c93 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST 0x10c94 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP 0x10c95 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR 0x10c96 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS 0x10c97 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL 0x10c97 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10c98 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10c98 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10c98 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10c98 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10c99 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10c99 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10c99 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10c99 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST 0x10ca8 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP 0x10ca9 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL 0x10ca9 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST 0x10cb4 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP 0x10cb5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL 0x10cb5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST 0x10cca |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP 0x10ccb |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL 0x10ccb |
| #define regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp |
| // base address: 0x10144000 |
| #define regBIF_CFG_DEV0_EPF4_0_VENDOR_ID 0x11000 |
| #define regBIF_CFG_DEV0_EPF4_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_ID 0x11000 |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_COMMAND 0x11001 |
| #define regBIF_CFG_DEV0_EPF4_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_STATUS 0x11001 |
| #define regBIF_CFG_DEV0_EPF4_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_REVISION_ID 0x11002 |
| #define regBIF_CFG_DEV0_EPF4_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PROG_INTERFACE 0x11002 |
| #define regBIF_CFG_DEV0_EPF4_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_SUB_CLASS 0x11002 |
| #define regBIF_CFG_DEV0_EPF4_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_CLASS 0x11002 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_CACHE_LINE 0x11003 |
| #define regBIF_CFG_DEV0_EPF4_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_LATENCY 0x11003 |
| #define regBIF_CFG_DEV0_EPF4_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_HEADER 0x11003 |
| #define regBIF_CFG_DEV0_EPF4_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_BIST 0x11003 |
| #define regBIF_CFG_DEV0_EPF4_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_1 0x11004 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_2 0x11005 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_3 0x11006 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_4 0x11007 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_5 0x11008 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_6 0x11009 |
| #define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_CARDBUS_CIS_PTR 0x1100a |
| #define regBIF_CFG_DEV0_EPF4_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_ADAPTER_ID 0x1100b |
| #define regBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR 0x1100c |
| #define regBIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_CAP_PTR 0x1100d |
| #define regBIF_CFG_DEV0_EPF4_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE 0x1100f |
| #define regBIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN 0x1100f |
| #define regBIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MIN_GRANT 0x1100f |
| #define regBIF_CFG_DEV0_EPF4_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MAX_LATENCY 0x1100f |
| #define regBIF_CFG_DEV0_EPF4_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST 0x11012 |
| #define regBIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W 0x11013 |
| #define regBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST 0x11014 |
| #define regBIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PMI_CAP 0x11014 |
| #define regBIF_CFG_DEV0_EPF4_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL 0x11015 |
| #define regBIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_SBRN 0x11018 |
| #define regBIF_CFG_DEV0_EPF4_0_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_FLADJ 0x11018 |
| #define regBIF_CFG_DEV0_EPF4_0_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_DBESL_DBESLD 0x11018 |
| #define regBIF_CFG_DEV0_EPF4_0_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST 0x11019 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_CAP 0x11019 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_CAP 0x1101a |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL 0x1101b |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS 0x1101b |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_LINK_CAP 0x1101c |
| #define regBIF_CFG_DEV0_EPF4_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_LINK_CNTL 0x1101d |
| #define regBIF_CFG_DEV0_EPF4_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_LINK_STATUS 0x1101d |
| #define regBIF_CFG_DEV0_EPF4_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_CAP2 0x11022 |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2 0x11023 |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2 0x11023 |
| #define regBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_LINK_CAP2 0x11024 |
| #define regBIF_CFG_DEV0_EPF4_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_LINK_CNTL2 0x11025 |
| #define regBIF_CFG_DEV0_EPF4_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_LINK_STATUS2 0x11025 |
| #define regBIF_CFG_DEV0_EPF4_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST 0x11028 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL 0x11028 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO 0x11029 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI 0x1102a |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA 0x1102a |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA 0x1102a |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MASK 0x1102b |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64 0x1102b |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64 0x1102b |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MASK_64 0x1102c |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_PENDING 0x1102c |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_PENDING_64 0x1102d |
| #define regBIF_CFG_DEV0_EPF4_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST 0x11030 |
| #define regBIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL 0x11030 |
| #define regBIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSIX_TABLE 0x11031 |
| #define regBIF_CFG_DEV0_EPF4_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_MSIX_PBA 0x11032 |
| #define regBIF_CFG_DEV0_EPF4_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x11040 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x11041 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1 0x11042 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2 0x11043 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x11054 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS 0x11055 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK 0x11056 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY 0x11057 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS 0x11058 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK 0x11059 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL 0x1105a |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0 0x1105b |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1 0x1105c |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2 0x1105d |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3 0x1105e |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0 0x11062 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1 0x11063 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2 0x11064 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3 0x11065 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST 0x11080 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP 0x11081 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL 0x11082 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP 0x11083 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL 0x11084 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP 0x11085 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL 0x11086 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP 0x11087 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL 0x11088 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP 0x11089 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL 0x1108a |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP 0x1108b |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL 0x1108c |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x11090 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT 0x11091 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA 0x11092 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP 0x11093 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST 0x11094 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP 0x11095 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR 0x11096 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS 0x11097 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL 0x11097 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x11098 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x11098 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x11098 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x11098 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x11099 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x11099 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x11099 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x11099 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST 0x110a8 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP 0x110a9 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL 0x110a9 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST 0x110b4 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP 0x110b5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL 0x110b5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST 0x110ca |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP 0x110cb |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL 0x110cb |
| #define regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp |
| // base address: 0x10145000 |
| #define regBIF_CFG_DEV0_EPF5_0_VENDOR_ID 0x11400 |
| #define regBIF_CFG_DEV0_EPF5_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_ID 0x11400 |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_COMMAND 0x11401 |
| #define regBIF_CFG_DEV0_EPF5_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_STATUS 0x11401 |
| #define regBIF_CFG_DEV0_EPF5_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_REVISION_ID 0x11402 |
| #define regBIF_CFG_DEV0_EPF5_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PROG_INTERFACE 0x11402 |
| #define regBIF_CFG_DEV0_EPF5_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_SUB_CLASS 0x11402 |
| #define regBIF_CFG_DEV0_EPF5_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_CLASS 0x11402 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_CACHE_LINE 0x11403 |
| #define regBIF_CFG_DEV0_EPF5_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_LATENCY 0x11403 |
| #define regBIF_CFG_DEV0_EPF5_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_HEADER 0x11403 |
| #define regBIF_CFG_DEV0_EPF5_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_BIST 0x11403 |
| #define regBIF_CFG_DEV0_EPF5_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_1 0x11404 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_2 0x11405 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_3 0x11406 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_4 0x11407 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_5 0x11408 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_6 0x11409 |
| #define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_CARDBUS_CIS_PTR 0x1140a |
| #define regBIF_CFG_DEV0_EPF5_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_ADAPTER_ID 0x1140b |
| #define regBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR 0x1140c |
| #define regBIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_CAP_PTR 0x1140d |
| #define regBIF_CFG_DEV0_EPF5_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE 0x1140f |
| #define regBIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN 0x1140f |
| #define regBIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MIN_GRANT 0x1140f |
| #define regBIF_CFG_DEV0_EPF5_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MAX_LATENCY 0x1140f |
| #define regBIF_CFG_DEV0_EPF5_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST 0x11412 |
| #define regBIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W 0x11413 |
| #define regBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST 0x11414 |
| #define regBIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PMI_CAP 0x11414 |
| #define regBIF_CFG_DEV0_EPF5_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL 0x11415 |
| #define regBIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_SBRN 0x11418 |
| #define regBIF_CFG_DEV0_EPF5_0_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_FLADJ 0x11418 |
| #define regBIF_CFG_DEV0_EPF5_0_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_DBESL_DBESLD 0x11418 |
| #define regBIF_CFG_DEV0_EPF5_0_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST 0x11419 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_CAP 0x11419 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_CAP 0x1141a |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL 0x1141b |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS 0x1141b |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_LINK_CAP 0x1141c |
| #define regBIF_CFG_DEV0_EPF5_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_LINK_CNTL 0x1141d |
| #define regBIF_CFG_DEV0_EPF5_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_LINK_STATUS 0x1141d |
| #define regBIF_CFG_DEV0_EPF5_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_CAP2 0x11422 |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2 0x11423 |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2 0x11423 |
| #define regBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_LINK_CAP2 0x11424 |
| #define regBIF_CFG_DEV0_EPF5_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_LINK_CNTL2 0x11425 |
| #define regBIF_CFG_DEV0_EPF5_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_LINK_STATUS2 0x11425 |
| #define regBIF_CFG_DEV0_EPF5_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST 0x11428 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL 0x11428 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO 0x11429 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI 0x1142a |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA 0x1142a |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA 0x1142a |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MASK 0x1142b |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64 0x1142b |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64 0x1142b |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MASK_64 0x1142c |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_PENDING 0x1142c |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_PENDING_64 0x1142d |
| #define regBIF_CFG_DEV0_EPF5_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST 0x11430 |
| #define regBIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL 0x11430 |
| #define regBIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSIX_TABLE 0x11431 |
| #define regBIF_CFG_DEV0_EPF5_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_MSIX_PBA 0x11432 |
| #define regBIF_CFG_DEV0_EPF5_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x11440 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x11441 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1 0x11442 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2 0x11443 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x11454 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS 0x11455 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK 0x11456 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY 0x11457 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS 0x11458 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK 0x11459 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL 0x1145a |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0 0x1145b |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1 0x1145c |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2 0x1145d |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3 0x1145e |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0 0x11462 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1 0x11463 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2 0x11464 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3 0x11465 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST 0x11480 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP 0x11481 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL 0x11482 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP 0x11483 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL 0x11484 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP 0x11485 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL 0x11486 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP 0x11487 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL 0x11488 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP 0x11489 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL 0x1148a |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP 0x1148b |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL 0x1148c |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x11490 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT 0x11491 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA 0x11492 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP 0x11493 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST 0x11494 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP 0x11495 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR 0x11496 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS 0x11497 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL 0x11497 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x11498 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x11498 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x11498 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x11498 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x11499 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x11499 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x11499 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x11499 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST 0x114a8 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP 0x114a9 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL 0x114a9 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST 0x114b4 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP 0x114b5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL 0x114b5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST 0x114ca |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP 0x114cb |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL 0x114cb |
| #define regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp |
| // base address: 0x10146000 |
| #define regBIF_CFG_DEV0_EPF6_0_VENDOR_ID 0x11800 |
| #define regBIF_CFG_DEV0_EPF6_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_ID 0x11800 |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_COMMAND 0x11801 |
| #define regBIF_CFG_DEV0_EPF6_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_STATUS 0x11801 |
| #define regBIF_CFG_DEV0_EPF6_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_REVISION_ID 0x11802 |
| #define regBIF_CFG_DEV0_EPF6_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PROG_INTERFACE 0x11802 |
| #define regBIF_CFG_DEV0_EPF6_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_SUB_CLASS 0x11802 |
| #define regBIF_CFG_DEV0_EPF6_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_CLASS 0x11802 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_CACHE_LINE 0x11803 |
| #define regBIF_CFG_DEV0_EPF6_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_LATENCY 0x11803 |
| #define regBIF_CFG_DEV0_EPF6_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_HEADER 0x11803 |
| #define regBIF_CFG_DEV0_EPF6_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_BIST 0x11803 |
| #define regBIF_CFG_DEV0_EPF6_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_1 0x11804 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_2 0x11805 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_3 0x11806 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_4 0x11807 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_5 0x11808 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_6 0x11809 |
| #define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_CARDBUS_CIS_PTR 0x1180a |
| #define regBIF_CFG_DEV0_EPF6_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_ADAPTER_ID 0x1180b |
| #define regBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR 0x1180c |
| #define regBIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_CAP_PTR 0x1180d |
| #define regBIF_CFG_DEV0_EPF6_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE 0x1180f |
| #define regBIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN 0x1180f |
| #define regBIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MIN_GRANT 0x1180f |
| #define regBIF_CFG_DEV0_EPF6_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MAX_LATENCY 0x1180f |
| #define regBIF_CFG_DEV0_EPF6_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST 0x11812 |
| #define regBIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W 0x11813 |
| #define regBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST 0x11814 |
| #define regBIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PMI_CAP 0x11814 |
| #define regBIF_CFG_DEV0_EPF6_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL 0x11815 |
| #define regBIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_SBRN 0x11818 |
| #define regBIF_CFG_DEV0_EPF6_0_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_FLADJ 0x11818 |
| #define regBIF_CFG_DEV0_EPF6_0_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_DBESL_DBESLD 0x11818 |
| #define regBIF_CFG_DEV0_EPF6_0_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST 0x11819 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_CAP 0x11819 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_CAP 0x1181a |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL 0x1181b |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS 0x1181b |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_LINK_CAP 0x1181c |
| #define regBIF_CFG_DEV0_EPF6_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_LINK_CNTL 0x1181d |
| #define regBIF_CFG_DEV0_EPF6_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_LINK_STATUS 0x1181d |
| #define regBIF_CFG_DEV0_EPF6_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_CAP2 0x11822 |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2 0x11823 |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2 0x11823 |
| #define regBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_LINK_CAP2 0x11824 |
| #define regBIF_CFG_DEV0_EPF6_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_LINK_CNTL2 0x11825 |
| #define regBIF_CFG_DEV0_EPF6_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_LINK_STATUS2 0x11825 |
| #define regBIF_CFG_DEV0_EPF6_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST 0x11828 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL 0x11828 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO 0x11829 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI 0x1182a |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA 0x1182a |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA 0x1182a |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MASK 0x1182b |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64 0x1182b |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64 0x1182b |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MASK_64 0x1182c |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_PENDING 0x1182c |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_PENDING_64 0x1182d |
| #define regBIF_CFG_DEV0_EPF6_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST 0x11830 |
| #define regBIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL 0x11830 |
| #define regBIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSIX_TABLE 0x11831 |
| #define regBIF_CFG_DEV0_EPF6_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_MSIX_PBA 0x11832 |
| #define regBIF_CFG_DEV0_EPF6_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x11840 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x11841 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1 0x11842 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2 0x11843 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x11854 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS 0x11855 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK 0x11856 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY 0x11857 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS 0x11858 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK 0x11859 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL 0x1185a |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0 0x1185b |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1 0x1185c |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2 0x1185d |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3 0x1185e |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0 0x11862 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1 0x11863 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2 0x11864 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3 0x11865 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST 0x11880 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP 0x11881 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL 0x11882 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP 0x11883 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL 0x11884 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP 0x11885 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL 0x11886 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP 0x11887 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL 0x11888 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP 0x11889 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL 0x1188a |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP 0x1188b |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL 0x1188c |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x11890 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT 0x11891 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA 0x11892 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP 0x11893 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST 0x11894 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP 0x11895 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR 0x11896 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS 0x11897 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL 0x11897 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x11898 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x11898 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x11898 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x11898 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x11899 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x11899 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x11899 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x11899 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST 0x118a8 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP 0x118a9 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL 0x118a9 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST 0x118b4 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP 0x118b5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL 0x118b5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST 0x118ca |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP 0x118cb |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL 0x118cb |
| #define regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp |
| // base address: 0x10147000 |
| #define regBIF_CFG_DEV0_EPF7_0_VENDOR_ID 0x11c00 |
| #define regBIF_CFG_DEV0_EPF7_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_ID 0x11c00 |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_COMMAND 0x11c01 |
| #define regBIF_CFG_DEV0_EPF7_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_STATUS 0x11c01 |
| #define regBIF_CFG_DEV0_EPF7_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_REVISION_ID 0x11c02 |
| #define regBIF_CFG_DEV0_EPF7_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PROG_INTERFACE 0x11c02 |
| #define regBIF_CFG_DEV0_EPF7_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_SUB_CLASS 0x11c02 |
| #define regBIF_CFG_DEV0_EPF7_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_CLASS 0x11c02 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_CACHE_LINE 0x11c03 |
| #define regBIF_CFG_DEV0_EPF7_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_LATENCY 0x11c03 |
| #define regBIF_CFG_DEV0_EPF7_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_HEADER 0x11c03 |
| #define regBIF_CFG_DEV0_EPF7_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_BIST 0x11c03 |
| #define regBIF_CFG_DEV0_EPF7_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_1 0x11c04 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_2 0x11c05 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_3 0x11c06 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_4 0x11c07 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_5 0x11c08 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_6 0x11c09 |
| #define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_CARDBUS_CIS_PTR 0x11c0a |
| #define regBIF_CFG_DEV0_EPF7_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_ADAPTER_ID 0x11c0b |
| #define regBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR 0x11c0c |
| #define regBIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_CAP_PTR 0x11c0d |
| #define regBIF_CFG_DEV0_EPF7_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE 0x11c0f |
| #define regBIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN 0x11c0f |
| #define regBIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MIN_GRANT 0x11c0f |
| #define regBIF_CFG_DEV0_EPF7_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MAX_LATENCY 0x11c0f |
| #define regBIF_CFG_DEV0_EPF7_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST 0x11c12 |
| #define regBIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W 0x11c13 |
| #define regBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST 0x11c14 |
| #define regBIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PMI_CAP 0x11c14 |
| #define regBIF_CFG_DEV0_EPF7_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL 0x11c15 |
| #define regBIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_SBRN 0x11c18 |
| #define regBIF_CFG_DEV0_EPF7_0_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_FLADJ 0x11c18 |
| #define regBIF_CFG_DEV0_EPF7_0_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_DBESL_DBESLD 0x11c18 |
| #define regBIF_CFG_DEV0_EPF7_0_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST 0x11c19 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_CAP 0x11c19 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_CAP 0x11c1a |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL 0x11c1b |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS 0x11c1b |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_LINK_CAP 0x11c1c |
| #define regBIF_CFG_DEV0_EPF7_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_LINK_CNTL 0x11c1d |
| #define regBIF_CFG_DEV0_EPF7_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_LINK_STATUS 0x11c1d |
| #define regBIF_CFG_DEV0_EPF7_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_CAP2 0x11c22 |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2 0x11c23 |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2 0x11c23 |
| #define regBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_LINK_CAP2 0x11c24 |
| #define regBIF_CFG_DEV0_EPF7_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_LINK_CNTL2 0x11c25 |
| #define regBIF_CFG_DEV0_EPF7_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_LINK_STATUS2 0x11c25 |
| #define regBIF_CFG_DEV0_EPF7_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST 0x11c28 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL 0x11c28 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO 0x11c29 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI 0x11c2a |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA 0x11c2a |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA 0x11c2a |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MASK 0x11c2b |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64 0x11c2b |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64 0x11c2b |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MASK_64 0x11c2c |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_PENDING 0x11c2c |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_PENDING_64 0x11c2d |
| #define regBIF_CFG_DEV0_EPF7_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST 0x11c30 |
| #define regBIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL 0x11c30 |
| #define regBIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSIX_TABLE 0x11c31 |
| #define regBIF_CFG_DEV0_EPF7_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_MSIX_PBA 0x11c32 |
| #define regBIF_CFG_DEV0_EPF7_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x11c40 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x11c41 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1 0x11c42 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2 0x11c43 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x11c54 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS 0x11c55 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK 0x11c56 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY 0x11c57 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS 0x11c58 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK 0x11c59 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL 0x11c5a |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0 0x11c5b |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1 0x11c5c |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2 0x11c5d |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3 0x11c5e |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0 0x11c62 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1 0x11c63 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2 0x11c64 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3 0x11c65 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST 0x11c80 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP 0x11c81 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL 0x11c82 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP 0x11c83 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL 0x11c84 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP 0x11c85 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL 0x11c86 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP 0x11c87 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL 0x11c88 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP 0x11c89 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL 0x11c8a |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP 0x11c8b |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL 0x11c8c |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x11c90 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT 0x11c91 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA 0x11c92 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP 0x11c93 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST 0x11c94 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP 0x11c95 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR 0x11c96 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS 0x11c97 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL 0x11c97 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x11c98 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x11c98 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x11c98 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x11c98 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x11c99 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x11c99 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x11c99 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x11c99 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST 0x11ca8 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP 0x11ca9 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL 0x11ca9 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST 0x11cb4 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP 0x11cb5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL 0x11cb5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST 0x11cca |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP 0x11ccb |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL 0x11ccb |
| #define regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp |
| // base address: 0x10148000 |
| #define regBIF_CFG_DEV1_EPF0_0_VENDOR_ID 0x12000 |
| #define regBIF_CFG_DEV1_EPF0_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_ID 0x12000 |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_COMMAND 0x12001 |
| #define regBIF_CFG_DEV1_EPF0_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_STATUS 0x12001 |
| #define regBIF_CFG_DEV1_EPF0_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_REVISION_ID 0x12002 |
| #define regBIF_CFG_DEV1_EPF0_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PROG_INTERFACE 0x12002 |
| #define regBIF_CFG_DEV1_EPF0_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_SUB_CLASS 0x12002 |
| #define regBIF_CFG_DEV1_EPF0_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_CLASS 0x12002 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_CACHE_LINE 0x12003 |
| #define regBIF_CFG_DEV1_EPF0_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LATENCY 0x12003 |
| #define regBIF_CFG_DEV1_EPF0_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_HEADER 0x12003 |
| #define regBIF_CFG_DEV1_EPF0_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_BIST 0x12003 |
| #define regBIF_CFG_DEV1_EPF0_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_1 0x12004 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_2 0x12005 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_3 0x12006 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_4 0x12007 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_5 0x12008 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_6 0x12009 |
| #define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_CARDBUS_CIS_PTR 0x1200a |
| #define regBIF_CFG_DEV1_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_ADAPTER_ID 0x1200b |
| #define regBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR 0x1200c |
| #define regBIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_CAP_PTR 0x1200d |
| #define regBIF_CFG_DEV1_EPF0_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE 0x1200f |
| #define regBIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN 0x1200f |
| #define regBIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MIN_GRANT 0x1200f |
| #define regBIF_CFG_DEV1_EPF0_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MAX_LATENCY 0x1200f |
| #define regBIF_CFG_DEV1_EPF0_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST 0x12012 |
| #define regBIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W 0x12013 |
| #define regBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST 0x12014 |
| #define regBIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PMI_CAP 0x12014 |
| #define regBIF_CFG_DEV1_EPF0_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL 0x12015 |
| #define regBIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_SBRN 0x12018 |
| #define regBIF_CFG_DEV1_EPF0_0_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_FLADJ 0x12018 |
| #define regBIF_CFG_DEV1_EPF0_0_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_DBESL_DBESLD 0x12018 |
| #define regBIF_CFG_DEV1_EPF0_0_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST 0x12019 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_CAP 0x12019 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_CAP 0x1201a |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL 0x1201b |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS 0x1201b |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_CAP 0x1201c |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_CNTL 0x1201d |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_STATUS 0x1201d |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_CAP2 0x12022 |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2 0x12023 |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2 0x12023 |
| #define regBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_CAP2 0x12024 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_CNTL2 0x12025 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_STATUS2 0x12025 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST 0x12028 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL 0x12028 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO 0x12029 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI 0x1202a |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA 0x1202a |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA 0x1202a |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MASK 0x1202b |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64 0x1202b |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64 0x1202b |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MASK_64 0x1202c |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_PENDING 0x1202c |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_PENDING_64 0x1202d |
| #define regBIF_CFG_DEV1_EPF0_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST 0x12030 |
| #define regBIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL 0x12030 |
| #define regBIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSIX_TABLE 0x12031 |
| #define regBIF_CFG_DEV1_EPF0_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MSIX_PBA 0x12032 |
| #define regBIF_CFG_DEV1_EPF0_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x12040 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x12041 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x12042 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x12043 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x12044 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x12045 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x12046 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL 0x12047 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS 0x12047 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x12048 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x12049 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x1204a |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x1204b |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x1204c |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x1204d |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x12054 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x12055 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK 0x12056 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x12057 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS 0x12058 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK 0x12059 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x1205a |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0 0x1205b |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1 0x1205c |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2 0x1205d |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3 0x1205e |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x12062 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x12063 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x12064 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x12065 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x12080 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP 0x12081 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL 0x12082 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP 0x12083 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL 0x12084 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP 0x12085 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL 0x12086 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP 0x12087 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL 0x12088 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP 0x12089 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL 0x1208a |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP 0x1208b |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL 0x1208c |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x12090 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x12091 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA 0x12092 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP 0x12093 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x12094 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP 0x12095 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x12096 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS 0x12097 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL 0x12097 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x12098 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x12098 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x12098 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x12098 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x12099 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x12099 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x12099 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x12099 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x1209c |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3 0x1209d |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS 0x1209e |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1209f |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1209f |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x120a0 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x120a0 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x120a1 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x120a1 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x120a2 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x120a2 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x120a3 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x120a3 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x120a4 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x120a4 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x120a5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x120a5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x120a6 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x120a6 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x120a8 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP 0x120a9 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL 0x120a9 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x120b4 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP 0x120b5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL 0x120b5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x120c8 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP 0x120c9 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x120ca |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP 0x120cb |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL 0x120cb |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x12100 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP 0x12101 |
| #define regBIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS 0x12102 |
| #define regBIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x12104 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT 0x12105 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT 0x12106 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT 0x12107 |
| #define regBIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x12108 |
| #define regBIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x12109 |
| #define regBIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1210a |
| #define regBIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x1210c |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x1210c |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x1210c |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x1210c |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x1210d |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x1210d |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x1210d |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x1210d |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x1210e |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x1210e |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x1210e |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x1210e |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x1210f |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x1210f |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x1210f |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x1210f |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x12114 |
| #define regBIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP 0x12115 |
| #define regBIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS 0x12115 |
| #define regBIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x12116 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x12116 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x12117 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x12117 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x12118 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x12118 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x12119 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x12119 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x1211a |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x1211a |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x1211b |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x1211b |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x1211c |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x1211c |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x1211d |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x1211d |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x1211e |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x1211e |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x1211f |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x1211f |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x12120 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x12120 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x12121 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x12121 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x12122 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x12122 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x12123 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x12123 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x12124 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x12124 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x12125 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x12125 |
| #define regBIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp |
| // base address: 0x10149000 |
| #define regBIF_CFG_DEV1_EPF1_0_VENDOR_ID 0x12400 |
| #define regBIF_CFG_DEV1_EPF1_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_ID 0x12400 |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_COMMAND 0x12401 |
| #define regBIF_CFG_DEV1_EPF1_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_STATUS 0x12401 |
| #define regBIF_CFG_DEV1_EPF1_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_REVISION_ID 0x12402 |
| #define regBIF_CFG_DEV1_EPF1_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PROG_INTERFACE 0x12402 |
| #define regBIF_CFG_DEV1_EPF1_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_SUB_CLASS 0x12402 |
| #define regBIF_CFG_DEV1_EPF1_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_CLASS 0x12402 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_CACHE_LINE 0x12403 |
| #define regBIF_CFG_DEV1_EPF1_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_LATENCY 0x12403 |
| #define regBIF_CFG_DEV1_EPF1_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_HEADER 0x12403 |
| #define regBIF_CFG_DEV1_EPF1_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_BIST 0x12403 |
| #define regBIF_CFG_DEV1_EPF1_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_1 0x12404 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_2 0x12405 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_3 0x12406 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_4 0x12407 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_5 0x12408 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_6 0x12409 |
| #define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_CARDBUS_CIS_PTR 0x1240a |
| #define regBIF_CFG_DEV1_EPF1_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_ADAPTER_ID 0x1240b |
| #define regBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR 0x1240c |
| #define regBIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_CAP_PTR 0x1240d |
| #define regBIF_CFG_DEV1_EPF1_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE 0x1240f |
| #define regBIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN 0x1240f |
| #define regBIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MIN_GRANT 0x1240f |
| #define regBIF_CFG_DEV1_EPF1_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MAX_LATENCY 0x1240f |
| #define regBIF_CFG_DEV1_EPF1_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST 0x12412 |
| #define regBIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W 0x12413 |
| #define regBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST 0x12414 |
| #define regBIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PMI_CAP 0x12414 |
| #define regBIF_CFG_DEV1_EPF1_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL 0x12415 |
| #define regBIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_SBRN 0x12418 |
| #define regBIF_CFG_DEV1_EPF1_0_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_FLADJ 0x12418 |
| #define regBIF_CFG_DEV1_EPF1_0_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_DBESL_DBESLD 0x12418 |
| #define regBIF_CFG_DEV1_EPF1_0_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST 0x12419 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_CAP 0x12419 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_CAP 0x1241a |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL 0x1241b |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS 0x1241b |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_LINK_CAP 0x1241c |
| #define regBIF_CFG_DEV1_EPF1_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_LINK_CNTL 0x1241d |
| #define regBIF_CFG_DEV1_EPF1_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_LINK_STATUS 0x1241d |
| #define regBIF_CFG_DEV1_EPF1_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_CAP2 0x12422 |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2 0x12423 |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2 0x12423 |
| #define regBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_LINK_CAP2 0x12424 |
| #define regBIF_CFG_DEV1_EPF1_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_LINK_CNTL2 0x12425 |
| #define regBIF_CFG_DEV1_EPF1_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_LINK_STATUS2 0x12425 |
| #define regBIF_CFG_DEV1_EPF1_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST 0x12428 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL 0x12428 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO 0x12429 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI 0x1242a |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA 0x1242a |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA 0x1242a |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MASK 0x1242b |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64 0x1242b |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64 0x1242b |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MASK_64 0x1242c |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_PENDING 0x1242c |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_PENDING_64 0x1242d |
| #define regBIF_CFG_DEV1_EPF1_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST 0x12430 |
| #define regBIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL 0x12430 |
| #define regBIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSIX_TABLE 0x12431 |
| #define regBIF_CFG_DEV1_EPF1_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_MSIX_PBA 0x12432 |
| #define regBIF_CFG_DEV1_EPF1_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x12440 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x12441 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x12442 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x12443 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x12454 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x12455 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK 0x12456 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x12457 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS 0x12458 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK 0x12459 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x1245a |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0 0x1245b |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1 0x1245c |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2 0x1245d |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3 0x1245e |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x12462 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x12463 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x12464 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x12465 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x12480 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP 0x12481 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL 0x12482 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP 0x12483 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL 0x12484 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP 0x12485 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL 0x12486 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP 0x12487 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL 0x12488 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP 0x12489 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL 0x1248a |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP 0x1248b |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL 0x1248c |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x12490 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x12491 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA 0x12492 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP 0x12493 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x12494 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP 0x12495 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x12496 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS 0x12497 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL 0x12497 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x12498 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x12498 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x12498 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x12498 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x12499 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x12499 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x12499 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x12499 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x124a8 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP 0x124a9 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL 0x124a9 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x124b4 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP 0x124b5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL 0x124b5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x124ca |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP 0x124cb |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL 0x124cb |
| #define regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev2_epf0_bifcfgdecp |
| // base address: 0x10150000 |
| #define regBIF_CFG_DEV2_EPF0_0_VENDOR_ID 0x14000 |
| #define regBIF_CFG_DEV2_EPF0_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_ID 0x14000 |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_COMMAND 0x14001 |
| #define regBIF_CFG_DEV2_EPF0_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_STATUS 0x14001 |
| #define regBIF_CFG_DEV2_EPF0_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_REVISION_ID 0x14002 |
| #define regBIF_CFG_DEV2_EPF0_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PROG_INTERFACE 0x14002 |
| #define regBIF_CFG_DEV2_EPF0_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_SUB_CLASS 0x14002 |
| #define regBIF_CFG_DEV2_EPF0_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_CLASS 0x14002 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_CACHE_LINE 0x14003 |
| #define regBIF_CFG_DEV2_EPF0_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LATENCY 0x14003 |
| #define regBIF_CFG_DEV2_EPF0_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_HEADER 0x14003 |
| #define regBIF_CFG_DEV2_EPF0_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_BIST 0x14003 |
| #define regBIF_CFG_DEV2_EPF0_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_1 0x14004 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_2 0x14005 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_3 0x14006 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_4 0x14007 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_5 0x14008 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_6 0x14009 |
| #define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_CARDBUS_CIS_PTR 0x1400a |
| #define regBIF_CFG_DEV2_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_ADAPTER_ID 0x1400b |
| #define regBIF_CFG_DEV2_EPF0_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR 0x1400c |
| #define regBIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_CAP_PTR 0x1400d |
| #define regBIF_CFG_DEV2_EPF0_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE 0x1400f |
| #define regBIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN 0x1400f |
| #define regBIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MIN_GRANT 0x1400f |
| #define regBIF_CFG_DEV2_EPF0_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MAX_LATENCY 0x1400f |
| #define regBIF_CFG_DEV2_EPF0_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST 0x14012 |
| #define regBIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W 0x14013 |
| #define regBIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST 0x14014 |
| #define regBIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PMI_CAP 0x14014 |
| #define regBIF_CFG_DEV2_EPF0_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL 0x14015 |
| #define regBIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST 0x14019 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_CAP 0x14019 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_CAP 0x1401a |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_CNTL 0x1401b |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_STATUS 0x1401b |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_CAP 0x1401c |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_CNTL 0x1401d |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_STATUS 0x1401d |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_CAP2 0x14022 |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2 0x14023 |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2 0x14023 |
| #define regBIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_CAP2 0x14024 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_CNTL2 0x14025 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_STATUS2 0x14025 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST 0x14028 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL 0x14028 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO 0x14029 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI 0x1402a |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA 0x1402a |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA 0x1402a |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MASK 0x1402b |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64 0x1402b |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64 0x1402b |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MASK_64 0x1402c |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_PENDING 0x1402c |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_PENDING_64 0x1402d |
| #define regBIF_CFG_DEV2_EPF0_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST 0x14030 |
| #define regBIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL 0x14030 |
| #define regBIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSIX_TABLE 0x14031 |
| #define regBIF_CFG_DEV2_EPF0_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MSIX_PBA 0x14032 |
| #define regBIF_CFG_DEV2_EPF0_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x14040 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x14041 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x14042 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x14043 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x14044 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x14045 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x14046 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL 0x14047 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS 0x14047 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x14048 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x14049 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x1404a |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x1404b |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x1404c |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x1404d |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x14054 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x14055 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK 0x14056 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x14057 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS 0x14058 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK 0x14059 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x1405a |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0 0x1405b |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1 0x1405c |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2 0x1405d |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3 0x1405e |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x14062 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x14063 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x14064 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x14065 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x14080 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP 0x14081 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL 0x14082 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP 0x14083 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL 0x14084 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP 0x14085 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL 0x14086 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP 0x14087 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL 0x14088 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP 0x14089 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL 0x1408a |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP 0x1408b |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL 0x1408c |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x14090 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x14091 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA 0x14092 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP 0x14093 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x14094 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP 0x14095 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x14096 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS 0x14097 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL 0x14097 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x14098 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x14098 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x14098 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x14098 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x14099 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x14099 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x14099 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x14099 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x1409c |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3 0x1409d |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS 0x1409e |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1409f |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1409f |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x140a0 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x140a0 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x140a1 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x140a1 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x140a2 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x140a2 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x140a3 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x140a3 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x140a4 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x140a4 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x140a5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x140a5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x140a6 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x140a6 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x140a8 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP 0x140a9 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL 0x140a9 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x140b4 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP 0x140b5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL 0x140b5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x140c8 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP 0x140c9 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x140ca |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP 0x140cb |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL 0x140cb |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x14100 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP 0x14101 |
| #define regBIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS 0x14102 |
| #define regBIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x14104 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT 0x14105 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT 0x14106 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT 0x14107 |
| #define regBIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x14108 |
| #define regBIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x14109 |
| #define regBIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1410a |
| #define regBIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x1410c |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x1410c |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x1410c |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x1410c |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x1410d |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x1410d |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x1410d |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x1410d |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x1410e |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x1410e |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x1410e |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x1410e |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x1410f |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x1410f |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x1410f |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x1410f |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x14114 |
| #define regBIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP 0x14115 |
| #define regBIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS 0x14115 |
| #define regBIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x14116 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x14116 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x14117 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x14117 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x14118 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x14118 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x14119 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x14119 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x1411a |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x1411a |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x1411b |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x1411b |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x1411c |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x1411c |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x1411d |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x1411d |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x1411e |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x1411e |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x1411f |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x1411f |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x14120 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x14120 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x14121 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x14121 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x14122 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x14122 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x14123 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x14123 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x14124 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x14124 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x14125 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x14125 |
| #define regBIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev2_epf1_bifcfgdecp |
| // base address: 0x10151000 |
| #define regBIF_CFG_DEV2_EPF1_0_VENDOR_ID 0x14400 |
| #define regBIF_CFG_DEV2_EPF1_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_ID 0x14400 |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_COMMAND 0x14401 |
| #define regBIF_CFG_DEV2_EPF1_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_STATUS 0x14401 |
| #define regBIF_CFG_DEV2_EPF1_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_REVISION_ID 0x14402 |
| #define regBIF_CFG_DEV2_EPF1_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PROG_INTERFACE 0x14402 |
| #define regBIF_CFG_DEV2_EPF1_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_SUB_CLASS 0x14402 |
| #define regBIF_CFG_DEV2_EPF1_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_CLASS 0x14402 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_CACHE_LINE 0x14403 |
| #define regBIF_CFG_DEV2_EPF1_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_LATENCY 0x14403 |
| #define regBIF_CFG_DEV2_EPF1_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_HEADER 0x14403 |
| #define regBIF_CFG_DEV2_EPF1_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_BIST 0x14403 |
| #define regBIF_CFG_DEV2_EPF1_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_1 0x14404 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_2 0x14405 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_3 0x14406 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_4 0x14407 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_5 0x14408 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_6 0x14409 |
| #define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_CARDBUS_CIS_PTR 0x1440a |
| #define regBIF_CFG_DEV2_EPF1_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_ADAPTER_ID 0x1440b |
| #define regBIF_CFG_DEV2_EPF1_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR 0x1440c |
| #define regBIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_CAP_PTR 0x1440d |
| #define regBIF_CFG_DEV2_EPF1_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE 0x1440f |
| #define regBIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN 0x1440f |
| #define regBIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MIN_GRANT 0x1440f |
| #define regBIF_CFG_DEV2_EPF1_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MAX_LATENCY 0x1440f |
| #define regBIF_CFG_DEV2_EPF1_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST 0x14412 |
| #define regBIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W 0x14413 |
| #define regBIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST 0x14414 |
| #define regBIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PMI_CAP 0x14414 |
| #define regBIF_CFG_DEV2_EPF1_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL 0x14415 |
| #define regBIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_SBRN 0x14418 |
| #define regBIF_CFG_DEV2_EPF1_0_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_FLADJ 0x14418 |
| #define regBIF_CFG_DEV2_EPF1_0_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_DBESL_DBESLD 0x14418 |
| #define regBIF_CFG_DEV2_EPF1_0_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST 0x14419 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_CAP 0x14419 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_CAP 0x1441a |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_CNTL 0x1441b |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_STATUS 0x1441b |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_LINK_CAP 0x1441c |
| #define regBIF_CFG_DEV2_EPF1_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_LINK_CNTL 0x1441d |
| #define regBIF_CFG_DEV2_EPF1_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_LINK_STATUS 0x1441d |
| #define regBIF_CFG_DEV2_EPF1_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_CAP2 0x14422 |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2 0x14423 |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2 0x14423 |
| #define regBIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_LINK_CAP2 0x14424 |
| #define regBIF_CFG_DEV2_EPF1_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_LINK_CNTL2 0x14425 |
| #define regBIF_CFG_DEV2_EPF1_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_LINK_STATUS2 0x14425 |
| #define regBIF_CFG_DEV2_EPF1_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST 0x14428 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL 0x14428 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO 0x14429 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI 0x1442a |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA 0x1442a |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA 0x1442a |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MASK 0x1442b |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64 0x1442b |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64 0x1442b |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MASK_64 0x1442c |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_PENDING 0x1442c |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_PENDING_64 0x1442d |
| #define regBIF_CFG_DEV2_EPF1_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST 0x14430 |
| #define regBIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL 0x14430 |
| #define regBIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSIX_TABLE 0x14431 |
| #define regBIF_CFG_DEV2_EPF1_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_MSIX_PBA 0x14432 |
| #define regBIF_CFG_DEV2_EPF1_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x14440 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x14441 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x14442 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x14443 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x14454 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x14455 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK 0x14456 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x14457 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS 0x14458 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK 0x14459 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x1445a |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0 0x1445b |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1 0x1445c |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2 0x1445d |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3 0x1445e |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x14462 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x14463 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x14464 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x14465 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x14480 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP 0x14481 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL 0x14482 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP 0x14483 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL 0x14484 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP 0x14485 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL 0x14486 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP 0x14487 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL 0x14488 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP 0x14489 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL 0x1448a |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP 0x1448b |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL 0x1448c |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x14490 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x14491 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA 0x14492 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP 0x14493 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x14494 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP 0x14495 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x14496 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS 0x14497 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL 0x14497 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x14498 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x14498 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x14498 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x14498 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x14499 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x14499 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x14499 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x14499 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x144a8 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP 0x144a9 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL 0x144a9 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x144b4 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP 0x144b5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL 0x144b5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x144ca |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP 0x144cb |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL 0x144cb |
| #define regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev2_epf2_bifcfgdecp |
| // base address: 0x10152000 |
| #define regBIF_CFG_DEV2_EPF2_0_VENDOR_ID 0x14800 |
| #define regBIF_CFG_DEV2_EPF2_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_ID 0x14800 |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_COMMAND 0x14801 |
| #define regBIF_CFG_DEV2_EPF2_0_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_STATUS 0x14801 |
| #define regBIF_CFG_DEV2_EPF2_0_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_REVISION_ID 0x14802 |
| #define regBIF_CFG_DEV2_EPF2_0_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PROG_INTERFACE 0x14802 |
| #define regBIF_CFG_DEV2_EPF2_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_SUB_CLASS 0x14802 |
| #define regBIF_CFG_DEV2_EPF2_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_CLASS 0x14802 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_CACHE_LINE 0x14803 |
| #define regBIF_CFG_DEV2_EPF2_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_LATENCY 0x14803 |
| #define regBIF_CFG_DEV2_EPF2_0_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_HEADER 0x14803 |
| #define regBIF_CFG_DEV2_EPF2_0_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_BIST 0x14803 |
| #define regBIF_CFG_DEV2_EPF2_0_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_1 0x14804 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_2 0x14805 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_3 0x14806 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_4 0x14807 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_5 0x14808 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_6 0x14809 |
| #define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_CARDBUS_CIS_PTR 0x1480a |
| #define regBIF_CFG_DEV2_EPF2_0_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_ADAPTER_ID 0x1480b |
| #define regBIF_CFG_DEV2_EPF2_0_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR 0x1480c |
| #define regBIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_CAP_PTR 0x1480d |
| #define regBIF_CFG_DEV2_EPF2_0_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE 0x1480f |
| #define regBIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN 0x1480f |
| #define regBIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MIN_GRANT 0x1480f |
| #define regBIF_CFG_DEV2_EPF2_0_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MAX_LATENCY 0x1480f |
| #define regBIF_CFG_DEV2_EPF2_0_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST 0x14812 |
| #define regBIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W 0x14813 |
| #define regBIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST 0x14814 |
| #define regBIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PMI_CAP 0x14814 |
| #define regBIF_CFG_DEV2_EPF2_0_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL 0x14815 |
| #define regBIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_SBRN 0x14818 |
| #define regBIF_CFG_DEV2_EPF2_0_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_FLADJ 0x14818 |
| #define regBIF_CFG_DEV2_EPF2_0_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_DBESL_DBESLD 0x14818 |
| #define regBIF_CFG_DEV2_EPF2_0_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST 0x14819 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_CAP 0x14819 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_CAP 0x1481a |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_CNTL 0x1481b |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_STATUS 0x1481b |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_LINK_CAP 0x1481c |
| #define regBIF_CFG_DEV2_EPF2_0_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_LINK_CNTL 0x1481d |
| #define regBIF_CFG_DEV2_EPF2_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_LINK_STATUS 0x1481d |
| #define regBIF_CFG_DEV2_EPF2_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_CAP2 0x14822 |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2 0x14823 |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2 0x14823 |
| #define regBIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_LINK_CAP2 0x14824 |
| #define regBIF_CFG_DEV2_EPF2_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_LINK_CNTL2 0x14825 |
| #define regBIF_CFG_DEV2_EPF2_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_LINK_STATUS2 0x14825 |
| #define regBIF_CFG_DEV2_EPF2_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST 0x14828 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL 0x14828 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO 0x14829 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI 0x1482a |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA 0x1482a |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA 0x1482a |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MASK 0x1482b |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64 0x1482b |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64 0x1482b |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MASK_64 0x1482c |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_PENDING 0x1482c |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_PENDING_64 0x1482d |
| #define regBIF_CFG_DEV2_EPF2_0_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST 0x14830 |
| #define regBIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL 0x14830 |
| #define regBIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSIX_TABLE 0x14831 |
| #define regBIF_CFG_DEV2_EPF2_0_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_MSIX_PBA 0x14832 |
| #define regBIF_CFG_DEV2_EPF2_0_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x14840 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x14841 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1 0x14842 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2 0x14843 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x14854 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS 0x14855 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK 0x14856 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0x14857 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS 0x14858 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK 0x14859 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0x1485a |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0 0x1485b |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1 0x1485c |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2 0x1485d |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3 0x1485e |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0 0x14862 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1 0x14863 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2 0x14864 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3 0x14865 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0x14880 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP 0x14881 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL 0x14882 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP 0x14883 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL 0x14884 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP 0x14885 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL 0x14886 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP 0x14887 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL 0x14888 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP 0x14889 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL 0x1488a |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP 0x1488b |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL 0x1488c |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x14890 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0x14891 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA 0x14892 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP 0x14893 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0x14894 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP 0x14895 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0x14896 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS 0x14897 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL 0x14897 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x14898 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x14898 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x14898 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x14898 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x14899 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x14899 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x14899 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x14899 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0x148a8 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP 0x148a9 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL 0x148a9 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST 0x148b4 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP 0x148b5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL 0x148b5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0x148ca |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP 0x148cb |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL 0x148cb |
| #define regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifplr0_cfgdecp |
| // base address: 0x11100000 |
| #define regBIFPLR0_0_VENDOR_ID 0x400000 |
| #define regBIFPLR0_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR0_0_DEVICE_ID 0x400000 |
| #define regBIFPLR0_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR0_0_COMMAND 0x400001 |
| #define regBIFPLR0_0_COMMAND_BASE_IDX 5 |
| #define regBIFPLR0_0_STATUS 0x400001 |
| #define regBIFPLR0_0_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_REVISION_ID 0x400002 |
| #define regBIFPLR0_0_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR0_0_PROG_INTERFACE 0x400002 |
| #define regBIFPLR0_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR0_0_SUB_CLASS 0x400002 |
| #define regBIFPLR0_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR0_0_BASE_CLASS 0x400002 |
| #define regBIFPLR0_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR0_0_CACHE_LINE 0x400003 |
| #define regBIFPLR0_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR0_0_LATENCY 0x400003 |
| #define regBIFPLR0_0_LATENCY_BASE_IDX 5 |
| #define regBIFPLR0_0_HEADER 0x400003 |
| #define regBIFPLR0_0_HEADER_BASE_IDX 5 |
| #define regBIFPLR0_0_BIST 0x400003 |
| #define regBIFPLR0_0_BIST_BASE_IDX 5 |
| #define regBIFPLR0_0_SUB_BUS_NUMBER_LATENCY 0x400006 |
| #define regBIFPLR0_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR0_0_IO_BASE_LIMIT 0x400007 |
| #define regBIFPLR0_0_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR0_0_SECONDARY_STATUS 0x400007 |
| #define regBIFPLR0_0_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_MEM_BASE_LIMIT 0x400008 |
| #define regBIFPLR0_0_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR0_0_PREF_BASE_LIMIT 0x400009 |
| #define regBIFPLR0_0_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR0_0_PREF_BASE_UPPER 0x40000a |
| #define regBIFPLR0_0_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR0_0_PREF_LIMIT_UPPER 0x40000b |
| #define regBIFPLR0_0_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR0_0_IO_BASE_LIMIT_HI 0x40000c |
| #define regBIFPLR0_0_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR0_0_CAP_PTR 0x40000d |
| #define regBIFPLR0_0_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR0_0_ROM_BASE_ADDR 0x40000e |
| #define regBIFPLR0_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIFPLR0_0_INTERRUPT_LINE 0x40000f |
| #define regBIFPLR0_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR0_0_INTERRUPT_PIN 0x40000f |
| #define regBIFPLR0_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR0_0_EXT_BRIDGE_CNTL 0x400010 |
| #define regBIFPLR0_0_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_VENDOR_CAP_LIST 0x400012 |
| #define regBIFPLR0_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_ADAPTER_ID_W 0x400013 |
| #define regBIFPLR0_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIFPLR0_0_PMI_CAP_LIST 0x400014 |
| #define regBIFPLR0_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PMI_CAP 0x400014 |
| #define regBIFPLR0_0_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_PMI_STATUS_CNTL 0x400015 |
| #define regBIFPLR0_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CAP_LIST 0x400016 |
| #define regBIFPLR0_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CAP 0x400016 |
| #define regBIFPLR0_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_DEVICE_CAP 0x400017 |
| #define regBIFPLR0_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_DEVICE_CNTL 0x400018 |
| #define regBIFPLR0_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_DEVICE_STATUS 0x400018 |
| #define regBIFPLR0_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LINK_CAP 0x400019 |
| #define regBIFPLR0_0_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_LINK_CNTL 0x40001a |
| #define regBIFPLR0_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LINK_STATUS 0x40001a |
| #define regBIFPLR0_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_SLOT_CAP 0x40001b |
| #define regBIFPLR0_0_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_SLOT_CNTL 0x40001c |
| #define regBIFPLR0_0_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_SLOT_STATUS 0x40001c |
| #define regBIFPLR0_0_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_ROOT_CNTL 0x40001d |
| #define regBIFPLR0_0_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_ROOT_CAP 0x40001d |
| #define regBIFPLR0_0_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_ROOT_STATUS 0x40001e |
| #define regBIFPLR0_0_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_DEVICE_CAP2 0x40001f |
| #define regBIFPLR0_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR0_0_DEVICE_CNTL2 0x400020 |
| #define regBIFPLR0_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_0_DEVICE_STATUS2 0x400020 |
| #define regBIFPLR0_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR0_0_LINK_CAP2 0x400021 |
| #define regBIFPLR0_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR0_0_LINK_CNTL2 0x400022 |
| #define regBIFPLR0_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_0_LINK_STATUS2 0x400022 |
| #define regBIFPLR0_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR0_0_SLOT_CAP2 0x400023 |
| #define regBIFPLR0_0_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR0_0_SLOT_CNTL2 0x400024 |
| #define regBIFPLR0_0_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_0_SLOT_STATUS2 0x400024 |
| #define regBIFPLR0_0_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR0_0_MSI_CAP_LIST 0x400028 |
| #define regBIFPLR0_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_MSI_MSG_CNTL 0x400028 |
| #define regBIFPLR0_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_MSI_MSG_ADDR_LO 0x400029 |
| #define regBIFPLR0_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR0_0_MSI_MSG_ADDR_HI 0x40002a |
| #define regBIFPLR0_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR0_0_MSI_MSG_DATA 0x40002a |
| #define regBIFPLR0_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR0_0_MSI_MSG_DATA_64 0x40002b |
| #define regBIFPLR0_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR0_0_SSID_CAP_LIST 0x400030 |
| #define regBIFPLR0_0_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_SSID_CAP 0x400031 |
| #define regBIFPLR0_0_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_MSI_MAP_CAP_LIST 0x400032 |
| #define regBIFPLR0_0_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_MSI_MAP_CAP 0x400032 |
| #define regBIFPLR0_0_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x400040 |
| #define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR 0x400041 |
| #define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC1 0x400042 |
| #define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC2 0x400043 |
| #define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_VC_ENH_CAP_LIST 0x400044 |
| #define regBIFPLR0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_PORT_VC_CAP_REG1 0x400045 |
| #define regBIFPLR0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_PORT_VC_CAP_REG2 0x400046 |
| #define regBIFPLR0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_PORT_VC_CNTL 0x400047 |
| #define regBIFPLR0_0_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_PORT_VC_STATUS 0x400047 |
| #define regBIFPLR0_0_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_VC0_RESOURCE_CAP 0x400048 |
| #define regBIFPLR0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_VC0_RESOURCE_CNTL 0x400049 |
| #define regBIFPLR0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_VC0_RESOURCE_STATUS 0x40004a |
| #define regBIFPLR0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_VC1_RESOURCE_CAP 0x40004b |
| #define regBIFPLR0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_VC1_RESOURCE_CNTL 0x40004c |
| #define regBIFPLR0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_VC1_RESOURCE_STATUS 0x40004d |
| #define regBIFPLR0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x400050 |
| #define regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1 0x400051 |
| #define regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2 0x400052 |
| #define regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x400054 |
| #define regBIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_UNCORR_ERR_STATUS 0x400055 |
| #define regBIFPLR0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_UNCORR_ERR_MASK 0x400056 |
| #define regBIFPLR0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY 0x400057 |
| #define regBIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CORR_ERR_STATUS 0x400058 |
| #define regBIFPLR0_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CORR_ERR_MASK 0x400059 |
| #define regBIFPLR0_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL 0x40005a |
| #define regBIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_HDR_LOG0 0x40005b |
| #define regBIFPLR0_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_HDR_LOG1 0x40005c |
| #define regBIFPLR0_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_HDR_LOG2 0x40005d |
| #define regBIFPLR0_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_HDR_LOG3 0x40005e |
| #define regBIFPLR0_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ROOT_ERR_CMD 0x40005f |
| #define regBIFPLR0_0_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ROOT_ERR_STATUS 0x400060 |
| #define regBIFPLR0_0_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ERR_SRC_ID 0x400061 |
| #define regBIFPLR0_0_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG0 0x400062 |
| #define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG1 0x400063 |
| #define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG2 0x400064 |
| #define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG3 0x400065 |
| #define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x40009c |
| #define regBIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LINK_CNTL3 0x40009d |
| #define regBIFPLR0_0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_ERROR_STATUS 0x40009e |
| #define regBIFPLR0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x40009f |
| #define regBIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x40009f |
| #define regBIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x4000a0 |
| #define regBIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x4000a0 |
| #define regBIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x4000a1 |
| #define regBIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x4000a1 |
| #define regBIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x4000a2 |
| #define regBIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x4000a2 |
| #define regBIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x4000a3 |
| #define regBIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x4000a3 |
| #define regBIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x4000a4 |
| #define regBIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x4000a4 |
| #define regBIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x4000a5 |
| #define regBIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x4000a5 |
| #define regBIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x4000a6 |
| #define regBIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x4000a6 |
| #define regBIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ACS_ENH_CAP_LIST 0x4000a8 |
| #define regBIFPLR0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ACS_CAP 0x4000a9 |
| #define regBIFPLR0_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ACS_CNTL 0x4000a9 |
| #define regBIFPLR0_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_ENH_CAP_LIST 0x4000bc |
| #define regBIFPLR0_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_CAP 0x4000bd |
| #define regBIFPLR0_0_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_CNTL 0x4000bd |
| #define regBIFPLR0_0_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_ADDR0 0x4000be |
| #define regBIFPLR0_0_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_ADDR1 0x4000bf |
| #define regBIFPLR0_0_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_RCV0 0x4000c0 |
| #define regBIFPLR0_0_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_RCV1 0x4000c1 |
| #define regBIFPLR0_0_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_BLOCK_ALL0 0x4000c2 |
| #define regBIFPLR0_0_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_BLOCK_ALL1 0x4000c3 |
| #define regBIFPLR0_0_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x4000c4 |
| #define regBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x4000c5 |
| #define regBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_OVERLAY_BAR0 0x4000c6 |
| #define regBIFPLR0_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MC_OVERLAY_BAR1 0x4000c7 |
| #define regBIFPLR0_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST 0x4000dc |
| #define regBIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_L1_PM_SUB_CAP 0x4000dd |
| #define regBIFPLR0_0_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_L1_PM_SUB_CNTL 0x4000de |
| #define regBIFPLR0_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_L1_PM_SUB_CNTL2 0x4000df |
| #define regBIFPLR0_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_DPC_ENH_CAP_LIST 0x4000e0 |
| #define regBIFPLR0_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_DPC_CAP_LIST 0x4000e1 |
| #define regBIFPLR0_0_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_DPC_CNTL 0x4000e1 |
| #define regBIFPLR0_0_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_DPC_STATUS 0x4000e2 |
| #define regBIFPLR0_0_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID 0x4000e2 |
| #define regBIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_STATUS 0x4000e3 |
| #define regBIFPLR0_0_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_MASK 0x4000e4 |
| #define regBIFPLR0_0_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_SEVERITY 0x4000e5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_SYSERROR 0x4000e6 |
| #define regBIFPLR0_0_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_EXCEPTION 0x4000e7 |
| #define regBIFPLR0_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG0 0x4000e8 |
| #define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG1 0x4000e9 |
| #define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG2 0x4000ea |
| #define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG3 0x4000eb |
| #define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0 0x4000ed |
| #define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1 0x4000ee |
| #define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2 0x4000ef |
| #define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3 0x4000f0 |
| #define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_LIST 0x4000f1 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ESM_HEADER_1 0x4000f2 |
| #define regBIFPLR0_0_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ESM_HEADER_2 0x4000f3 |
| #define regBIFPLR0_0_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ESM_STATUS 0x4000f3 |
| #define regBIFPLR0_0_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ESM_CTRL 0x4000f4 |
| #define regBIFPLR0_0_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_1 0x4000f5 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_2 0x4000f6 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_3 0x4000f7 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_4 0x4000f8 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_5 0x4000f9 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_6 0x4000fa |
| #define regBIFPLR0_0_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_ESM_CAP_7 0x4000fb |
| #define regBIFPLR0_0_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_DLF_ENH_CAP_LIST 0x400100 |
| #define regBIFPLR0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_DATA_LINK_FEATURE_CAP 0x400101 |
| #define regBIFPLR0_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_DATA_LINK_FEATURE_STATUS 0x400102 |
| #define regBIFPLR0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x400104 |
| #define regBIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_LINK_CAP_16GT 0x400105 |
| #define regBIFPLR0_0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LINK_CNTL_16GT 0x400106 |
| #define regBIFPLR0_0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LINK_STATUS_16GT 0x400107 |
| #define regBIFPLR0_0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x400108 |
| #define regBIFPLR0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x400109 |
| #define regBIFPLR0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x40010a |
| #define regBIFPLR0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x40010c |
| #define regBIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x40010c |
| #define regBIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x40010c |
| #define regBIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x40010c |
| #define regBIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x40010d |
| #define regBIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x40010d |
| #define regBIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x40010d |
| #define regBIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x40010d |
| #define regBIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x40010e |
| #define regBIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x40010e |
| #define regBIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x40010e |
| #define regBIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x40010e |
| #define regBIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x40010f |
| #define regBIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x40010f |
| #define regBIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x40010f |
| #define regBIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x40010f |
| #define regBIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST 0x400110 |
| #define regBIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_MARGINING_PORT_CAP 0x400111 |
| #define regBIFPLR0_0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_MARGINING_PORT_STATUS 0x400111 |
| #define regBIFPLR0_0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_0_MARGINING_LANE_CNTL 0x400112 |
| #define regBIFPLR0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_0_MARGINING_LANE_STATUS 0x400112 |
| #define regBIFPLR0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_1_MARGINING_LANE_CNTL 0x400113 |
| #define regBIFPLR0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_1_MARGINING_LANE_STATUS 0x400113 |
| #define regBIFPLR0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_2_MARGINING_LANE_CNTL 0x400114 |
| #define regBIFPLR0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_2_MARGINING_LANE_STATUS 0x400114 |
| #define regBIFPLR0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_3_MARGINING_LANE_CNTL 0x400115 |
| #define regBIFPLR0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_3_MARGINING_LANE_STATUS 0x400115 |
| #define regBIFPLR0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_4_MARGINING_LANE_CNTL 0x400116 |
| #define regBIFPLR0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_4_MARGINING_LANE_STATUS 0x400116 |
| #define regBIFPLR0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_5_MARGINING_LANE_CNTL 0x400117 |
| #define regBIFPLR0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_5_MARGINING_LANE_STATUS 0x400117 |
| #define regBIFPLR0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_6_MARGINING_LANE_CNTL 0x400118 |
| #define regBIFPLR0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_6_MARGINING_LANE_STATUS 0x400118 |
| #define regBIFPLR0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_7_MARGINING_LANE_CNTL 0x400119 |
| #define regBIFPLR0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_7_MARGINING_LANE_STATUS 0x400119 |
| #define regBIFPLR0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_8_MARGINING_LANE_CNTL 0x40011a |
| #define regBIFPLR0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_8_MARGINING_LANE_STATUS 0x40011a |
| #define regBIFPLR0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_9_MARGINING_LANE_CNTL 0x40011b |
| #define regBIFPLR0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_9_MARGINING_LANE_STATUS 0x40011b |
| #define regBIFPLR0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_10_MARGINING_LANE_CNTL 0x40011c |
| #define regBIFPLR0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_10_MARGINING_LANE_STATUS 0x40011c |
| #define regBIFPLR0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_11_MARGINING_LANE_CNTL 0x40011d |
| #define regBIFPLR0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_11_MARGINING_LANE_STATUS 0x40011d |
| #define regBIFPLR0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_12_MARGINING_LANE_CNTL 0x40011e |
| #define regBIFPLR0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_12_MARGINING_LANE_STATUS 0x40011e |
| #define regBIFPLR0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_13_MARGINING_LANE_CNTL 0x40011f |
| #define regBIFPLR0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_13_MARGINING_LANE_STATUS 0x40011f |
| #define regBIFPLR0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_14_MARGINING_LANE_CNTL 0x400120 |
| #define regBIFPLR0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_14_MARGINING_LANE_STATUS 0x400120 |
| #define regBIFPLR0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_15_MARGINING_LANE_CNTL 0x400121 |
| #define regBIFPLR0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LANE_15_MARGINING_LANE_STATUS 0x400121 |
| #define regBIFPLR0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CCIX_CAP_LIST 0x400122 |
| #define regBIFPLR0_0_PCIE_CCIX_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CCIX_HEADER_1 0x400123 |
| #define regBIFPLR0_0_PCIE_CCIX_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CCIX_HEADER_2 0x400124 |
| #define regBIFPLR0_0_PCIE_CCIX_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CCIX_CAP 0x400124 |
| #define regBIFPLR0_0_PCIE_CCIX_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP 0x400125 |
| #define regBIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CCIX_ESM_OPTL_CAP 0x400126 |
| #define regBIFPLR0_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CCIX_ESM_STATUS 0x400127 |
| #define regBIFPLR0_0_PCIE_CCIX_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CCIX_ESM_CNTL 0x400128 |
| #define regBIFPLR0_0_PCIE_CCIX_ESM_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x400129 |
| #define regBIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x400129 |
| #define regBIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x400129 |
| #define regBIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x400129 |
| #define regBIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x40012a |
| #define regBIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x40012a |
| #define regBIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x40012a |
| #define regBIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x40012a |
| #define regBIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x40012b |
| #define regBIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x40012b |
| #define regBIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x40012b |
| #define regBIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x40012b |
| #define regBIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x40012c |
| #define regBIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x40012c |
| #define regBIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x40012c |
| #define regBIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x40012c |
| #define regBIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x40012d |
| #define regBIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x40012d |
| #define regBIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x40012d |
| #define regBIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x40012d |
| #define regBIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x40012e |
| #define regBIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x40012e |
| #define regBIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x40012e |
| #define regBIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x40012e |
| #define regBIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x40012f |
| #define regBIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x40012f |
| #define regBIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x40012f |
| #define regBIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x40012f |
| #define regBIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x400130 |
| #define regBIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x400130 |
| #define regBIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x400130 |
| #define regBIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x400130 |
| #define regBIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CCIX_TRANS_CAP 0x400131 |
| #define regBIFPLR0_0_PCIE_CCIX_TRANS_CAP_BASE_IDX 5 |
| #define regBIFPLR0_0_PCIE_CCIX_TRANS_CNTL 0x400132 |
| #define regBIFPLR0_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_0_LINK_CAP_32GT 0x400141 |
| #define regBIFPLR0_0_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LINK_CNTL_32GT 0x400142 |
| #define regBIFPLR0_0_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR0_0_LINK_STATUS_32GT 0x400143 |
| #define regBIFPLR0_0_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifplr1_cfgdecp |
| // base address: 0x11101000 |
| #define regBIFPLR1_0_VENDOR_ID 0x400400 |
| #define regBIFPLR1_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR1_0_DEVICE_ID 0x400400 |
| #define regBIFPLR1_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR1_0_COMMAND 0x400401 |
| #define regBIFPLR1_0_COMMAND_BASE_IDX 5 |
| #define regBIFPLR1_0_STATUS 0x400401 |
| #define regBIFPLR1_0_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_REVISION_ID 0x400402 |
| #define regBIFPLR1_0_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR1_0_PROG_INTERFACE 0x400402 |
| #define regBIFPLR1_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR1_0_SUB_CLASS 0x400402 |
| #define regBIFPLR1_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR1_0_BASE_CLASS 0x400402 |
| #define regBIFPLR1_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR1_0_CACHE_LINE 0x400403 |
| #define regBIFPLR1_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR1_0_LATENCY 0x400403 |
| #define regBIFPLR1_0_LATENCY_BASE_IDX 5 |
| #define regBIFPLR1_0_HEADER 0x400403 |
| #define regBIFPLR1_0_HEADER_BASE_IDX 5 |
| #define regBIFPLR1_0_BIST 0x400403 |
| #define regBIFPLR1_0_BIST_BASE_IDX 5 |
| #define regBIFPLR1_0_SUB_BUS_NUMBER_LATENCY 0x400406 |
| #define regBIFPLR1_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR1_0_IO_BASE_LIMIT 0x400407 |
| #define regBIFPLR1_0_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR1_0_SECONDARY_STATUS 0x400407 |
| #define regBIFPLR1_0_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_MEM_BASE_LIMIT 0x400408 |
| #define regBIFPLR1_0_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR1_0_PREF_BASE_LIMIT 0x400409 |
| #define regBIFPLR1_0_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR1_0_PREF_BASE_UPPER 0x40040a |
| #define regBIFPLR1_0_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR1_0_PREF_LIMIT_UPPER 0x40040b |
| #define regBIFPLR1_0_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR1_0_IO_BASE_LIMIT_HI 0x40040c |
| #define regBIFPLR1_0_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR1_0_CAP_PTR 0x40040d |
| #define regBIFPLR1_0_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR1_0_ROM_BASE_ADDR 0x40040e |
| #define regBIFPLR1_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIFPLR1_0_INTERRUPT_LINE 0x40040f |
| #define regBIFPLR1_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR1_0_INTERRUPT_PIN 0x40040f |
| #define regBIFPLR1_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR1_0_EXT_BRIDGE_CNTL 0x400410 |
| #define regBIFPLR1_0_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_VENDOR_CAP_LIST 0x400412 |
| #define regBIFPLR1_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_ADAPTER_ID_W 0x400413 |
| #define regBIFPLR1_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIFPLR1_0_PMI_CAP_LIST 0x400414 |
| #define regBIFPLR1_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PMI_CAP 0x400414 |
| #define regBIFPLR1_0_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_PMI_STATUS_CNTL 0x400415 |
| #define regBIFPLR1_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CAP_LIST 0x400416 |
| #define regBIFPLR1_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CAP 0x400416 |
| #define regBIFPLR1_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_DEVICE_CAP 0x400417 |
| #define regBIFPLR1_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_DEVICE_CNTL 0x400418 |
| #define regBIFPLR1_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_DEVICE_STATUS 0x400418 |
| #define regBIFPLR1_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LINK_CAP 0x400419 |
| #define regBIFPLR1_0_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_LINK_CNTL 0x40041a |
| #define regBIFPLR1_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LINK_STATUS 0x40041a |
| #define regBIFPLR1_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_SLOT_CAP 0x40041b |
| #define regBIFPLR1_0_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_SLOT_CNTL 0x40041c |
| #define regBIFPLR1_0_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_SLOT_STATUS 0x40041c |
| #define regBIFPLR1_0_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_ROOT_CNTL 0x40041d |
| #define regBIFPLR1_0_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_ROOT_CAP 0x40041d |
| #define regBIFPLR1_0_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_ROOT_STATUS 0x40041e |
| #define regBIFPLR1_0_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_DEVICE_CAP2 0x40041f |
| #define regBIFPLR1_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR1_0_DEVICE_CNTL2 0x400420 |
| #define regBIFPLR1_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_0_DEVICE_STATUS2 0x400420 |
| #define regBIFPLR1_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR1_0_LINK_CAP2 0x400421 |
| #define regBIFPLR1_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR1_0_LINK_CNTL2 0x400422 |
| #define regBIFPLR1_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_0_LINK_STATUS2 0x400422 |
| #define regBIFPLR1_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR1_0_SLOT_CAP2 0x400423 |
| #define regBIFPLR1_0_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR1_0_SLOT_CNTL2 0x400424 |
| #define regBIFPLR1_0_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_0_SLOT_STATUS2 0x400424 |
| #define regBIFPLR1_0_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR1_0_MSI_CAP_LIST 0x400428 |
| #define regBIFPLR1_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_MSI_MSG_CNTL 0x400428 |
| #define regBIFPLR1_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_MSI_MSG_ADDR_LO 0x400429 |
| #define regBIFPLR1_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR1_0_MSI_MSG_ADDR_HI 0x40042a |
| #define regBIFPLR1_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR1_0_MSI_MSG_DATA 0x40042a |
| #define regBIFPLR1_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR1_0_MSI_MSG_DATA_64 0x40042b |
| #define regBIFPLR1_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR1_0_SSID_CAP_LIST 0x400430 |
| #define regBIFPLR1_0_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_SSID_CAP 0x400431 |
| #define regBIFPLR1_0_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_MSI_MAP_CAP_LIST 0x400432 |
| #define regBIFPLR1_0_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_MSI_MAP_CAP 0x400432 |
| #define regBIFPLR1_0_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x400440 |
| #define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR 0x400441 |
| #define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC1 0x400442 |
| #define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC2 0x400443 |
| #define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_VC_ENH_CAP_LIST 0x400444 |
| #define regBIFPLR1_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_PORT_VC_CAP_REG1 0x400445 |
| #define regBIFPLR1_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_PORT_VC_CAP_REG2 0x400446 |
| #define regBIFPLR1_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_PORT_VC_CNTL 0x400447 |
| #define regBIFPLR1_0_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_PORT_VC_STATUS 0x400447 |
| #define regBIFPLR1_0_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_VC0_RESOURCE_CAP 0x400448 |
| #define regBIFPLR1_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_VC0_RESOURCE_CNTL 0x400449 |
| #define regBIFPLR1_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_VC0_RESOURCE_STATUS 0x40044a |
| #define regBIFPLR1_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_VC1_RESOURCE_CAP 0x40044b |
| #define regBIFPLR1_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_VC1_RESOURCE_CNTL 0x40044c |
| #define regBIFPLR1_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_VC1_RESOURCE_STATUS 0x40044d |
| #define regBIFPLR1_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x400450 |
| #define regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1 0x400451 |
| #define regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2 0x400452 |
| #define regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x400454 |
| #define regBIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_UNCORR_ERR_STATUS 0x400455 |
| #define regBIFPLR1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_UNCORR_ERR_MASK 0x400456 |
| #define regBIFPLR1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY 0x400457 |
| #define regBIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CORR_ERR_STATUS 0x400458 |
| #define regBIFPLR1_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CORR_ERR_MASK 0x400459 |
| #define regBIFPLR1_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL 0x40045a |
| #define regBIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_HDR_LOG0 0x40045b |
| #define regBIFPLR1_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_HDR_LOG1 0x40045c |
| #define regBIFPLR1_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_HDR_LOG2 0x40045d |
| #define regBIFPLR1_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_HDR_LOG3 0x40045e |
| #define regBIFPLR1_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ROOT_ERR_CMD 0x40045f |
| #define regBIFPLR1_0_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ROOT_ERR_STATUS 0x400460 |
| #define regBIFPLR1_0_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ERR_SRC_ID 0x400461 |
| #define regBIFPLR1_0_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG0 0x400462 |
| #define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG1 0x400463 |
| #define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG2 0x400464 |
| #define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG3 0x400465 |
| #define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x40049c |
| #define regBIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LINK_CNTL3 0x40049d |
| #define regBIFPLR1_0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_ERROR_STATUS 0x40049e |
| #define regBIFPLR1_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x40049f |
| #define regBIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x40049f |
| #define regBIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x4004a0 |
| #define regBIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x4004a0 |
| #define regBIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x4004a1 |
| #define regBIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x4004a1 |
| #define regBIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x4004a2 |
| #define regBIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x4004a2 |
| #define regBIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x4004a3 |
| #define regBIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x4004a3 |
| #define regBIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x4004a4 |
| #define regBIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x4004a4 |
| #define regBIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x4004a5 |
| #define regBIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x4004a5 |
| #define regBIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x4004a6 |
| #define regBIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x4004a6 |
| #define regBIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ACS_ENH_CAP_LIST 0x4004a8 |
| #define regBIFPLR1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ACS_CAP 0x4004a9 |
| #define regBIFPLR1_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ACS_CNTL 0x4004a9 |
| #define regBIFPLR1_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_ENH_CAP_LIST 0x4004bc |
| #define regBIFPLR1_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_CAP 0x4004bd |
| #define regBIFPLR1_0_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_CNTL 0x4004bd |
| #define regBIFPLR1_0_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_ADDR0 0x4004be |
| #define regBIFPLR1_0_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_ADDR1 0x4004bf |
| #define regBIFPLR1_0_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_RCV0 0x4004c0 |
| #define regBIFPLR1_0_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_RCV1 0x4004c1 |
| #define regBIFPLR1_0_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_BLOCK_ALL0 0x4004c2 |
| #define regBIFPLR1_0_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_BLOCK_ALL1 0x4004c3 |
| #define regBIFPLR1_0_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x4004c4 |
| #define regBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x4004c5 |
| #define regBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_OVERLAY_BAR0 0x4004c6 |
| #define regBIFPLR1_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MC_OVERLAY_BAR1 0x4004c7 |
| #define regBIFPLR1_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST 0x4004dc |
| #define regBIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_L1_PM_SUB_CAP 0x4004dd |
| #define regBIFPLR1_0_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_L1_PM_SUB_CNTL 0x4004de |
| #define regBIFPLR1_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_L1_PM_SUB_CNTL2 0x4004df |
| #define regBIFPLR1_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_DPC_ENH_CAP_LIST 0x4004e0 |
| #define regBIFPLR1_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_DPC_CAP_LIST 0x4004e1 |
| #define regBIFPLR1_0_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_DPC_CNTL 0x4004e1 |
| #define regBIFPLR1_0_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_DPC_STATUS 0x4004e2 |
| #define regBIFPLR1_0_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID 0x4004e2 |
| #define regBIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_STATUS 0x4004e3 |
| #define regBIFPLR1_0_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_MASK 0x4004e4 |
| #define regBIFPLR1_0_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_SEVERITY 0x4004e5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_SYSERROR 0x4004e6 |
| #define regBIFPLR1_0_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_EXCEPTION 0x4004e7 |
| #define regBIFPLR1_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG0 0x4004e8 |
| #define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG1 0x4004e9 |
| #define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG2 0x4004ea |
| #define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG3 0x4004eb |
| #define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0 0x4004ed |
| #define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1 0x4004ee |
| #define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2 0x4004ef |
| #define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3 0x4004f0 |
| #define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_LIST 0x4004f1 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ESM_HEADER_1 0x4004f2 |
| #define regBIFPLR1_0_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ESM_HEADER_2 0x4004f3 |
| #define regBIFPLR1_0_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ESM_STATUS 0x4004f3 |
| #define regBIFPLR1_0_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ESM_CTRL 0x4004f4 |
| #define regBIFPLR1_0_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_1 0x4004f5 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_2 0x4004f6 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_3 0x4004f7 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_4 0x4004f8 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_5 0x4004f9 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_6 0x4004fa |
| #define regBIFPLR1_0_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_ESM_CAP_7 0x4004fb |
| #define regBIFPLR1_0_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_DLF_ENH_CAP_LIST 0x400500 |
| #define regBIFPLR1_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_DATA_LINK_FEATURE_CAP 0x400501 |
| #define regBIFPLR1_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_DATA_LINK_FEATURE_STATUS 0x400502 |
| #define regBIFPLR1_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x400504 |
| #define regBIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_LINK_CAP_16GT 0x400505 |
| #define regBIFPLR1_0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LINK_CNTL_16GT 0x400506 |
| #define regBIFPLR1_0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LINK_STATUS_16GT 0x400507 |
| #define regBIFPLR1_0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x400508 |
| #define regBIFPLR1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x400509 |
| #define regBIFPLR1_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x40050a |
| #define regBIFPLR1_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT 0x40050c |
| #define regBIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT 0x40050c |
| #define regBIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT 0x40050c |
| #define regBIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT 0x40050c |
| #define regBIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT 0x40050d |
| #define regBIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT 0x40050d |
| #define regBIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT 0x40050d |
| #define regBIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT 0x40050d |
| #define regBIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT 0x40050e |
| #define regBIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT 0x40050e |
| #define regBIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT 0x40050e |
| #define regBIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT 0x40050e |
| #define regBIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT 0x40050f |
| #define regBIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT 0x40050f |
| #define regBIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT 0x40050f |
| #define regBIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT 0x40050f |
| #define regBIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST 0x400510 |
| #define regBIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_MARGINING_PORT_CAP 0x400511 |
| #define regBIFPLR1_0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_MARGINING_PORT_STATUS 0x400511 |
| #define regBIFPLR1_0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_0_MARGINING_LANE_CNTL 0x400512 |
| #define regBIFPLR1_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_0_MARGINING_LANE_STATUS 0x400512 |
| #define regBIFPLR1_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_1_MARGINING_LANE_CNTL 0x400513 |
| #define regBIFPLR1_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_1_MARGINING_LANE_STATUS 0x400513 |
| #define regBIFPLR1_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_2_MARGINING_LANE_CNTL 0x400514 |
| #define regBIFPLR1_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_2_MARGINING_LANE_STATUS 0x400514 |
| #define regBIFPLR1_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_3_MARGINING_LANE_CNTL 0x400515 |
| #define regBIFPLR1_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_3_MARGINING_LANE_STATUS 0x400515 |
| #define regBIFPLR1_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_4_MARGINING_LANE_CNTL 0x400516 |
| #define regBIFPLR1_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_4_MARGINING_LANE_STATUS 0x400516 |
| #define regBIFPLR1_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_5_MARGINING_LANE_CNTL 0x400517 |
| #define regBIFPLR1_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_5_MARGINING_LANE_STATUS 0x400517 |
| #define regBIFPLR1_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_6_MARGINING_LANE_CNTL 0x400518 |
| #define regBIFPLR1_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_6_MARGINING_LANE_STATUS 0x400518 |
| #define regBIFPLR1_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_7_MARGINING_LANE_CNTL 0x400519 |
| #define regBIFPLR1_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_7_MARGINING_LANE_STATUS 0x400519 |
| #define regBIFPLR1_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_8_MARGINING_LANE_CNTL 0x40051a |
| #define regBIFPLR1_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_8_MARGINING_LANE_STATUS 0x40051a |
| #define regBIFPLR1_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_9_MARGINING_LANE_CNTL 0x40051b |
| #define regBIFPLR1_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_9_MARGINING_LANE_STATUS 0x40051b |
| #define regBIFPLR1_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_10_MARGINING_LANE_CNTL 0x40051c |
| #define regBIFPLR1_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_10_MARGINING_LANE_STATUS 0x40051c |
| #define regBIFPLR1_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_11_MARGINING_LANE_CNTL 0x40051d |
| #define regBIFPLR1_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_11_MARGINING_LANE_STATUS 0x40051d |
| #define regBIFPLR1_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_12_MARGINING_LANE_CNTL 0x40051e |
| #define regBIFPLR1_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_12_MARGINING_LANE_STATUS 0x40051e |
| #define regBIFPLR1_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_13_MARGINING_LANE_CNTL 0x40051f |
| #define regBIFPLR1_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_13_MARGINING_LANE_STATUS 0x40051f |
| #define regBIFPLR1_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_14_MARGINING_LANE_CNTL 0x400520 |
| #define regBIFPLR1_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_14_MARGINING_LANE_STATUS 0x400520 |
| #define regBIFPLR1_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_15_MARGINING_LANE_CNTL 0x400521 |
| #define regBIFPLR1_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LANE_15_MARGINING_LANE_STATUS 0x400521 |
| #define regBIFPLR1_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CCIX_CAP_LIST 0x400522 |
| #define regBIFPLR1_0_PCIE_CCIX_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CCIX_HEADER_1 0x400523 |
| #define regBIFPLR1_0_PCIE_CCIX_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CCIX_HEADER_2 0x400524 |
| #define regBIFPLR1_0_PCIE_CCIX_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CCIX_CAP 0x400524 |
| #define regBIFPLR1_0_PCIE_CCIX_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP 0x400525 |
| #define regBIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CCIX_ESM_OPTL_CAP 0x400526 |
| #define regBIFPLR1_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CCIX_ESM_STATUS 0x400527 |
| #define regBIFPLR1_0_PCIE_CCIX_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CCIX_ESM_CNTL 0x400528 |
| #define regBIFPLR1_0_PCIE_CCIX_ESM_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x400529 |
| #define regBIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x400529 |
| #define regBIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x400529 |
| #define regBIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x400529 |
| #define regBIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x40052a |
| #define regBIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x40052a |
| #define regBIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x40052a |
| #define regBIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x40052a |
| #define regBIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x40052b |
| #define regBIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x40052b |
| #define regBIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x40052b |
| #define regBIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x40052b |
| #define regBIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x40052c |
| #define regBIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x40052c |
| #define regBIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x40052c |
| #define regBIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x40052c |
| #define regBIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x40052d |
| #define regBIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x40052d |
| #define regBIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x40052d |
| #define regBIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x40052d |
| #define regBIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x40052e |
| #define regBIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x40052e |
| #define regBIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x40052e |
| #define regBIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x40052e |
| #define regBIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x40052f |
| #define regBIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x40052f |
| #define regBIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x40052f |
| #define regBIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x40052f |
| #define regBIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x400530 |
| #define regBIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x400530 |
| #define regBIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x400530 |
| #define regBIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x400530 |
| #define regBIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CCIX_TRANS_CAP 0x400531 |
| #define regBIFPLR1_0_PCIE_CCIX_TRANS_CAP_BASE_IDX 5 |
| #define regBIFPLR1_0_PCIE_CCIX_TRANS_CNTL 0x400532 |
| #define regBIFPLR1_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_0_LINK_CAP_32GT 0x400541 |
| #define regBIFPLR1_0_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LINK_CNTL_32GT 0x400542 |
| #define regBIFPLR1_0_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR1_0_LINK_STATUS_32GT 0x400543 |
| #define regBIFPLR1_0_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifplr2_cfgdecp |
| // base address: 0x11102000 |
| #define regBIFPLR2_0_VENDOR_ID 0x400800 |
| #define regBIFPLR2_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR2_0_DEVICE_ID 0x400800 |
| #define regBIFPLR2_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR2_0_COMMAND 0x400801 |
| #define regBIFPLR2_0_COMMAND_BASE_IDX 5 |
| #define regBIFPLR2_0_STATUS 0x400801 |
| #define regBIFPLR2_0_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_REVISION_ID 0x400802 |
| #define regBIFPLR2_0_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR2_0_PROG_INTERFACE 0x400802 |
| #define regBIFPLR2_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR2_0_SUB_CLASS 0x400802 |
| #define regBIFPLR2_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR2_0_BASE_CLASS 0x400802 |
| #define regBIFPLR2_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR2_0_CACHE_LINE 0x400803 |
| #define regBIFPLR2_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR2_0_LATENCY 0x400803 |
| #define regBIFPLR2_0_LATENCY_BASE_IDX 5 |
| #define regBIFPLR2_0_HEADER 0x400803 |
| #define regBIFPLR2_0_HEADER_BASE_IDX 5 |
| #define regBIFPLR2_0_BIST 0x400803 |
| #define regBIFPLR2_0_BIST_BASE_IDX 5 |
| #define regBIFPLR2_0_SUB_BUS_NUMBER_LATENCY 0x400806 |
| #define regBIFPLR2_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR2_0_IO_BASE_LIMIT 0x400807 |
| #define regBIFPLR2_0_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR2_0_SECONDARY_STATUS 0x400807 |
| #define regBIFPLR2_0_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_MEM_BASE_LIMIT 0x400808 |
| #define regBIFPLR2_0_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR2_0_PREF_BASE_LIMIT 0x400809 |
| #define regBIFPLR2_0_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR2_0_PREF_BASE_UPPER 0x40080a |
| #define regBIFPLR2_0_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR2_0_PREF_LIMIT_UPPER 0x40080b |
| #define regBIFPLR2_0_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR2_0_IO_BASE_LIMIT_HI 0x40080c |
| #define regBIFPLR2_0_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR2_0_CAP_PTR 0x40080d |
| #define regBIFPLR2_0_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR2_0_ROM_BASE_ADDR 0x40080e |
| #define regBIFPLR2_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIFPLR2_0_INTERRUPT_LINE 0x40080f |
| #define regBIFPLR2_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR2_0_INTERRUPT_PIN 0x40080f |
| #define regBIFPLR2_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR2_0_EXT_BRIDGE_CNTL 0x400810 |
| #define regBIFPLR2_0_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_VENDOR_CAP_LIST 0x400812 |
| #define regBIFPLR2_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_ADAPTER_ID_W 0x400813 |
| #define regBIFPLR2_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIFPLR2_0_PMI_CAP_LIST 0x400814 |
| #define regBIFPLR2_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PMI_CAP 0x400814 |
| #define regBIFPLR2_0_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_PMI_STATUS_CNTL 0x400815 |
| #define regBIFPLR2_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CAP_LIST 0x400816 |
| #define regBIFPLR2_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CAP 0x400816 |
| #define regBIFPLR2_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_DEVICE_CAP 0x400817 |
| #define regBIFPLR2_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_DEVICE_CNTL 0x400818 |
| #define regBIFPLR2_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_DEVICE_STATUS 0x400818 |
| #define regBIFPLR2_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LINK_CAP 0x400819 |
| #define regBIFPLR2_0_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_LINK_CNTL 0x40081a |
| #define regBIFPLR2_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LINK_STATUS 0x40081a |
| #define regBIFPLR2_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_SLOT_CAP 0x40081b |
| #define regBIFPLR2_0_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_SLOT_CNTL 0x40081c |
| #define regBIFPLR2_0_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_SLOT_STATUS 0x40081c |
| #define regBIFPLR2_0_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_ROOT_CNTL 0x40081d |
| #define regBIFPLR2_0_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_ROOT_CAP 0x40081d |
| #define regBIFPLR2_0_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_ROOT_STATUS 0x40081e |
| #define regBIFPLR2_0_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_DEVICE_CAP2 0x40081f |
| #define regBIFPLR2_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR2_0_DEVICE_CNTL2 0x400820 |
| #define regBIFPLR2_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_0_DEVICE_STATUS2 0x400820 |
| #define regBIFPLR2_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR2_0_LINK_CAP2 0x400821 |
| #define regBIFPLR2_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR2_0_LINK_CNTL2 0x400822 |
| #define regBIFPLR2_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_0_LINK_STATUS2 0x400822 |
| #define regBIFPLR2_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR2_0_SLOT_CAP2 0x400823 |
| #define regBIFPLR2_0_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR2_0_SLOT_CNTL2 0x400824 |
| #define regBIFPLR2_0_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_0_SLOT_STATUS2 0x400824 |
| #define regBIFPLR2_0_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR2_0_MSI_CAP_LIST 0x400828 |
| #define regBIFPLR2_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_MSI_MSG_CNTL 0x400828 |
| #define regBIFPLR2_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_MSI_MSG_ADDR_LO 0x400829 |
| #define regBIFPLR2_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR2_0_MSI_MSG_ADDR_HI 0x40082a |
| #define regBIFPLR2_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR2_0_MSI_MSG_DATA 0x40082a |
| #define regBIFPLR2_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR2_0_MSI_MSG_DATA_64 0x40082b |
| #define regBIFPLR2_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR2_0_SSID_CAP_LIST 0x400830 |
| #define regBIFPLR2_0_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_SSID_CAP 0x400831 |
| #define regBIFPLR2_0_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_MSI_MAP_CAP_LIST 0x400832 |
| #define regBIFPLR2_0_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_MSI_MAP_CAP 0x400832 |
| #define regBIFPLR2_0_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x400840 |
| #define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR 0x400841 |
| #define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC1 0x400842 |
| #define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC2 0x400843 |
| #define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_VC_ENH_CAP_LIST 0x400844 |
| #define regBIFPLR2_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_PORT_VC_CAP_REG1 0x400845 |
| #define regBIFPLR2_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_PORT_VC_CAP_REG2 0x400846 |
| #define regBIFPLR2_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_PORT_VC_CNTL 0x400847 |
| #define regBIFPLR2_0_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_PORT_VC_STATUS 0x400847 |
| #define regBIFPLR2_0_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_VC0_RESOURCE_CAP 0x400848 |
| #define regBIFPLR2_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_VC0_RESOURCE_CNTL 0x400849 |
| #define regBIFPLR2_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_VC0_RESOURCE_STATUS 0x40084a |
| #define regBIFPLR2_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_VC1_RESOURCE_CAP 0x40084b |
| #define regBIFPLR2_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_VC1_RESOURCE_CNTL 0x40084c |
| #define regBIFPLR2_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_VC1_RESOURCE_STATUS 0x40084d |
| #define regBIFPLR2_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x400850 |
| #define regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1 0x400851 |
| #define regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2 0x400852 |
| #define regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x400854 |
| #define regBIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_UNCORR_ERR_STATUS 0x400855 |
| #define regBIFPLR2_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_UNCORR_ERR_MASK 0x400856 |
| #define regBIFPLR2_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY 0x400857 |
| #define regBIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CORR_ERR_STATUS 0x400858 |
| #define regBIFPLR2_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CORR_ERR_MASK 0x400859 |
| #define regBIFPLR2_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL 0x40085a |
| #define regBIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_HDR_LOG0 0x40085b |
| #define regBIFPLR2_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_HDR_LOG1 0x40085c |
| #define regBIFPLR2_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_HDR_LOG2 0x40085d |
| #define regBIFPLR2_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_HDR_LOG3 0x40085e |
| #define regBIFPLR2_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ROOT_ERR_CMD 0x40085f |
| #define regBIFPLR2_0_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ROOT_ERR_STATUS 0x400860 |
| #define regBIFPLR2_0_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ERR_SRC_ID 0x400861 |
| #define regBIFPLR2_0_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG0 0x400862 |
| #define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG1 0x400863 |
| #define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG2 0x400864 |
| #define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG3 0x400865 |
| #define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST 0x40089c |
| #define regBIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LINK_CNTL3 0x40089d |
| #define regBIFPLR2_0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_ERROR_STATUS 0x40089e |
| #define regBIFPLR2_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x40089f |
| #define regBIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x40089f |
| #define regBIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x4008a0 |
| #define regBIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x4008a0 |
| #define regBIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x4008a1 |
| #define regBIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x4008a1 |
| #define regBIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x4008a2 |
| #define regBIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x4008a2 |
| #define regBIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x4008a3 |
| #define regBIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x4008a3 |
| #define regBIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x4008a4 |
| #define regBIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x4008a4 |
| #define regBIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x4008a5 |
| #define regBIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x4008a5 |
| #define regBIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x4008a6 |
| #define regBIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x4008a6 |
| #define regBIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ACS_ENH_CAP_LIST 0x4008a8 |
| #define regBIFPLR2_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ACS_CAP 0x4008a9 |
| #define regBIFPLR2_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ACS_CNTL 0x4008a9 |
| #define regBIFPLR2_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_ENH_CAP_LIST 0x4008bc |
| #define regBIFPLR2_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_CAP 0x4008bd |
| #define regBIFPLR2_0_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_CNTL 0x4008bd |
| #define regBIFPLR2_0_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_ADDR0 0x4008be |
| #define regBIFPLR2_0_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_ADDR1 0x4008bf |
| #define regBIFPLR2_0_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_RCV0 0x4008c0 |
| #define regBIFPLR2_0_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_RCV1 0x4008c1 |
| #define regBIFPLR2_0_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_BLOCK_ALL0 0x4008c2 |
| #define regBIFPLR2_0_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_BLOCK_ALL1 0x4008c3 |
| #define regBIFPLR2_0_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x4008c4 |
| #define regBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x4008c5 |
| #define regBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_OVERLAY_BAR0 0x4008c6 |
| #define regBIFPLR2_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MC_OVERLAY_BAR1 0x4008c7 |
| #define regBIFPLR2_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST 0x4008dc |
| #define regBIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_L1_PM_SUB_CAP 0x4008dd |
| #define regBIFPLR2_0_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_L1_PM_SUB_CNTL 0x4008de |
| #define regBIFPLR2_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_L1_PM_SUB_CNTL2 0x4008df |
| #define regBIFPLR2_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_DPC_ENH_CAP_LIST 0x4008e0 |
| #define regBIFPLR2_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_DPC_CAP_LIST 0x4008e1 |
| #define regBIFPLR2_0_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_DPC_CNTL 0x4008e1 |
| #define regBIFPLR2_0_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_DPC_STATUS 0x4008e2 |
| #define regBIFPLR2_0_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID 0x4008e2 |
| #define regBIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_STATUS 0x4008e3 |
| #define regBIFPLR2_0_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_MASK 0x4008e4 |
| #define regBIFPLR2_0_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_SEVERITY 0x4008e5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_SYSERROR 0x4008e6 |
| #define regBIFPLR2_0_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_EXCEPTION 0x4008e7 |
| #define regBIFPLR2_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG0 0x4008e8 |
| #define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG1 0x4008e9 |
| #define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG2 0x4008ea |
| #define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG3 0x4008eb |
| #define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0 0x4008ed |
| #define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1 0x4008ee |
| #define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2 0x4008ef |
| #define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3 0x4008f0 |
| #define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_LIST 0x4008f1 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ESM_HEADER_1 0x4008f2 |
| #define regBIFPLR2_0_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ESM_HEADER_2 0x4008f3 |
| #define regBIFPLR2_0_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ESM_STATUS 0x4008f3 |
| #define regBIFPLR2_0_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ESM_CTRL 0x4008f4 |
| #define regBIFPLR2_0_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_1 0x4008f5 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_2 0x4008f6 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_3 0x4008f7 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_4 0x4008f8 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_5 0x4008f9 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_6 0x4008fa |
| #define regBIFPLR2_0_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_ESM_CAP_7 0x4008fb |
| #define regBIFPLR2_0_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_DLF_ENH_CAP_LIST 0x400900 |
| #define regBIFPLR2_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_DATA_LINK_FEATURE_CAP 0x400901 |
| #define regBIFPLR2_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_DATA_LINK_FEATURE_STATUS 0x400902 |
| #define regBIFPLR2_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x400904 |
| #define regBIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_LINK_CAP_16GT 0x400905 |
| #define regBIFPLR2_0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LINK_CNTL_16GT 0x400906 |
| #define regBIFPLR2_0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LINK_STATUS_16GT 0x400907 |
| #define regBIFPLR2_0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x400908 |
| #define regBIFPLR2_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x400909 |
| #define regBIFPLR2_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x40090a |
| #define regBIFPLR2_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT 0x40090c |
| #define regBIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT 0x40090c |
| #define regBIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT 0x40090c |
| #define regBIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT 0x40090c |
| #define regBIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT 0x40090d |
| #define regBIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT 0x40090d |
| #define regBIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT 0x40090d |
| #define regBIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT 0x40090d |
| #define regBIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT 0x40090e |
| #define regBIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT 0x40090e |
| #define regBIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT 0x40090e |
| #define regBIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT 0x40090e |
| #define regBIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT 0x40090f |
| #define regBIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT 0x40090f |
| #define regBIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT 0x40090f |
| #define regBIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT 0x40090f |
| #define regBIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST 0x400910 |
| #define regBIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_MARGINING_PORT_CAP 0x400911 |
| #define regBIFPLR2_0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_MARGINING_PORT_STATUS 0x400911 |
| #define regBIFPLR2_0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_0_MARGINING_LANE_CNTL 0x400912 |
| #define regBIFPLR2_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_0_MARGINING_LANE_STATUS 0x400912 |
| #define regBIFPLR2_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_1_MARGINING_LANE_CNTL 0x400913 |
| #define regBIFPLR2_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_1_MARGINING_LANE_STATUS 0x400913 |
| #define regBIFPLR2_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_2_MARGINING_LANE_CNTL 0x400914 |
| #define regBIFPLR2_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_2_MARGINING_LANE_STATUS 0x400914 |
| #define regBIFPLR2_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_3_MARGINING_LANE_CNTL 0x400915 |
| #define regBIFPLR2_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_3_MARGINING_LANE_STATUS 0x400915 |
| #define regBIFPLR2_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_4_MARGINING_LANE_CNTL 0x400916 |
| #define regBIFPLR2_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_4_MARGINING_LANE_STATUS 0x400916 |
| #define regBIFPLR2_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_5_MARGINING_LANE_CNTL 0x400917 |
| #define regBIFPLR2_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_5_MARGINING_LANE_STATUS 0x400917 |
| #define regBIFPLR2_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_6_MARGINING_LANE_CNTL 0x400918 |
| #define regBIFPLR2_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_6_MARGINING_LANE_STATUS 0x400918 |
| #define regBIFPLR2_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_7_MARGINING_LANE_CNTL 0x400919 |
| #define regBIFPLR2_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_7_MARGINING_LANE_STATUS 0x400919 |
| #define regBIFPLR2_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_8_MARGINING_LANE_CNTL 0x40091a |
| #define regBIFPLR2_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_8_MARGINING_LANE_STATUS 0x40091a |
| #define regBIFPLR2_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_9_MARGINING_LANE_CNTL 0x40091b |
| #define regBIFPLR2_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_9_MARGINING_LANE_STATUS 0x40091b |
| #define regBIFPLR2_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_10_MARGINING_LANE_CNTL 0x40091c |
| #define regBIFPLR2_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_10_MARGINING_LANE_STATUS 0x40091c |
| #define regBIFPLR2_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_11_MARGINING_LANE_CNTL 0x40091d |
| #define regBIFPLR2_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_11_MARGINING_LANE_STATUS 0x40091d |
| #define regBIFPLR2_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_12_MARGINING_LANE_CNTL 0x40091e |
| #define regBIFPLR2_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_12_MARGINING_LANE_STATUS 0x40091e |
| #define regBIFPLR2_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_13_MARGINING_LANE_CNTL 0x40091f |
| #define regBIFPLR2_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_13_MARGINING_LANE_STATUS 0x40091f |
| #define regBIFPLR2_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_14_MARGINING_LANE_CNTL 0x400920 |
| #define regBIFPLR2_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_14_MARGINING_LANE_STATUS 0x400920 |
| #define regBIFPLR2_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_15_MARGINING_LANE_CNTL 0x400921 |
| #define regBIFPLR2_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LANE_15_MARGINING_LANE_STATUS 0x400921 |
| #define regBIFPLR2_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CCIX_CAP_LIST 0x400922 |
| #define regBIFPLR2_0_PCIE_CCIX_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CCIX_HEADER_1 0x400923 |
| #define regBIFPLR2_0_PCIE_CCIX_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CCIX_HEADER_2 0x400924 |
| #define regBIFPLR2_0_PCIE_CCIX_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CCIX_CAP 0x400924 |
| #define regBIFPLR2_0_PCIE_CCIX_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP 0x400925 |
| #define regBIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CCIX_ESM_OPTL_CAP 0x400926 |
| #define regBIFPLR2_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CCIX_ESM_STATUS 0x400927 |
| #define regBIFPLR2_0_PCIE_CCIX_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CCIX_ESM_CNTL 0x400928 |
| #define regBIFPLR2_0_PCIE_CCIX_ESM_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x400929 |
| #define regBIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x400929 |
| #define regBIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x400929 |
| #define regBIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x400929 |
| #define regBIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x40092a |
| #define regBIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x40092a |
| #define regBIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x40092a |
| #define regBIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x40092a |
| #define regBIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x40092b |
| #define regBIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x40092b |
| #define regBIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x40092b |
| #define regBIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x40092b |
| #define regBIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x40092c |
| #define regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x40092c |
| #define regBIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x40092c |
| #define regBIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x40092c |
| #define regBIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x40092d |
| #define regBIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x40092d |
| #define regBIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x40092d |
| #define regBIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x40092d |
| #define regBIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x40092e |
| #define regBIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x40092e |
| #define regBIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x40092e |
| #define regBIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x40092e |
| #define regBIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x40092f |
| #define regBIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x40092f |
| #define regBIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x40092f |
| #define regBIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x40092f |
| #define regBIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x400930 |
| #define regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x400930 |
| #define regBIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x400930 |
| #define regBIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x400930 |
| #define regBIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CCIX_TRANS_CAP 0x400931 |
| #define regBIFPLR2_0_PCIE_CCIX_TRANS_CAP_BASE_IDX 5 |
| #define regBIFPLR2_0_PCIE_CCIX_TRANS_CNTL 0x400932 |
| #define regBIFPLR2_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_0_LINK_CAP_32GT 0x400941 |
| #define regBIFPLR2_0_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LINK_CNTL_32GT 0x400942 |
| #define regBIFPLR2_0_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR2_0_LINK_STATUS_32GT 0x400943 |
| #define regBIFPLR2_0_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifplr3_cfgdecp |
| // base address: 0x11103000 |
| #define regBIFPLR3_0_VENDOR_ID 0x400c00 |
| #define regBIFPLR3_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR3_0_DEVICE_ID 0x400c00 |
| #define regBIFPLR3_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR3_0_COMMAND 0x400c01 |
| #define regBIFPLR3_0_COMMAND_BASE_IDX 5 |
| #define regBIFPLR3_0_STATUS 0x400c01 |
| #define regBIFPLR3_0_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_REVISION_ID 0x400c02 |
| #define regBIFPLR3_0_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR3_0_PROG_INTERFACE 0x400c02 |
| #define regBIFPLR3_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR3_0_SUB_CLASS 0x400c02 |
| #define regBIFPLR3_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR3_0_BASE_CLASS 0x400c02 |
| #define regBIFPLR3_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR3_0_CACHE_LINE 0x400c03 |
| #define regBIFPLR3_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR3_0_LATENCY 0x400c03 |
| #define regBIFPLR3_0_LATENCY_BASE_IDX 5 |
| #define regBIFPLR3_0_HEADER 0x400c03 |
| #define regBIFPLR3_0_HEADER_BASE_IDX 5 |
| #define regBIFPLR3_0_BIST 0x400c03 |
| #define regBIFPLR3_0_BIST_BASE_IDX 5 |
| #define regBIFPLR3_0_SUB_BUS_NUMBER_LATENCY 0x400c06 |
| #define regBIFPLR3_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR3_0_IO_BASE_LIMIT 0x400c07 |
| #define regBIFPLR3_0_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR3_0_SECONDARY_STATUS 0x400c07 |
| #define regBIFPLR3_0_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_MEM_BASE_LIMIT 0x400c08 |
| #define regBIFPLR3_0_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR3_0_PREF_BASE_LIMIT 0x400c09 |
| #define regBIFPLR3_0_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR3_0_PREF_BASE_UPPER 0x400c0a |
| #define regBIFPLR3_0_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR3_0_PREF_LIMIT_UPPER 0x400c0b |
| #define regBIFPLR3_0_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR3_0_IO_BASE_LIMIT_HI 0x400c0c |
| #define regBIFPLR3_0_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR3_0_CAP_PTR 0x400c0d |
| #define regBIFPLR3_0_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR3_0_ROM_BASE_ADDR 0x400c0e |
| #define regBIFPLR3_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIFPLR3_0_INTERRUPT_LINE 0x400c0f |
| #define regBIFPLR3_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR3_0_INTERRUPT_PIN 0x400c0f |
| #define regBIFPLR3_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR3_0_EXT_BRIDGE_CNTL 0x400c10 |
| #define regBIFPLR3_0_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_VENDOR_CAP_LIST 0x400c12 |
| #define regBIFPLR3_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_ADAPTER_ID_W 0x400c13 |
| #define regBIFPLR3_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIFPLR3_0_PMI_CAP_LIST 0x400c14 |
| #define regBIFPLR3_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PMI_CAP 0x400c14 |
| #define regBIFPLR3_0_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_PMI_STATUS_CNTL 0x400c15 |
| #define regBIFPLR3_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CAP_LIST 0x400c16 |
| #define regBIFPLR3_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CAP 0x400c16 |
| #define regBIFPLR3_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_DEVICE_CAP 0x400c17 |
| #define regBIFPLR3_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_DEVICE_CNTL 0x400c18 |
| #define regBIFPLR3_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_DEVICE_STATUS 0x400c18 |
| #define regBIFPLR3_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LINK_CAP 0x400c19 |
| #define regBIFPLR3_0_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_LINK_CNTL 0x400c1a |
| #define regBIFPLR3_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LINK_STATUS 0x400c1a |
| #define regBIFPLR3_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_SLOT_CAP 0x400c1b |
| #define regBIFPLR3_0_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_SLOT_CNTL 0x400c1c |
| #define regBIFPLR3_0_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_SLOT_STATUS 0x400c1c |
| #define regBIFPLR3_0_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_ROOT_CNTL 0x400c1d |
| #define regBIFPLR3_0_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_ROOT_CAP 0x400c1d |
| #define regBIFPLR3_0_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_ROOT_STATUS 0x400c1e |
| #define regBIFPLR3_0_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_DEVICE_CAP2 0x400c1f |
| #define regBIFPLR3_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR3_0_DEVICE_CNTL2 0x400c20 |
| #define regBIFPLR3_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_0_DEVICE_STATUS2 0x400c20 |
| #define regBIFPLR3_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR3_0_LINK_CAP2 0x400c21 |
| #define regBIFPLR3_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR3_0_LINK_CNTL2 0x400c22 |
| #define regBIFPLR3_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_0_LINK_STATUS2 0x400c22 |
| #define regBIFPLR3_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR3_0_SLOT_CAP2 0x400c23 |
| #define regBIFPLR3_0_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR3_0_SLOT_CNTL2 0x400c24 |
| #define regBIFPLR3_0_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_0_SLOT_STATUS2 0x400c24 |
| #define regBIFPLR3_0_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR3_0_MSI_CAP_LIST 0x400c28 |
| #define regBIFPLR3_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_MSI_MSG_CNTL 0x400c28 |
| #define regBIFPLR3_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_MSI_MSG_ADDR_LO 0x400c29 |
| #define regBIFPLR3_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR3_0_MSI_MSG_ADDR_HI 0x400c2a |
| #define regBIFPLR3_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR3_0_MSI_MSG_DATA 0x400c2a |
| #define regBIFPLR3_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR3_0_MSI_MSG_DATA_64 0x400c2b |
| #define regBIFPLR3_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR3_0_SSID_CAP_LIST 0x400c30 |
| #define regBIFPLR3_0_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_SSID_CAP 0x400c31 |
| #define regBIFPLR3_0_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_MSI_MAP_CAP_LIST 0x400c32 |
| #define regBIFPLR3_0_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_MSI_MAP_CAP 0x400c32 |
| #define regBIFPLR3_0_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x400c40 |
| #define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR 0x400c41 |
| #define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC1 0x400c42 |
| #define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC2 0x400c43 |
| #define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_VC_ENH_CAP_LIST 0x400c44 |
| #define regBIFPLR3_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_PORT_VC_CAP_REG1 0x400c45 |
| #define regBIFPLR3_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_PORT_VC_CAP_REG2 0x400c46 |
| #define regBIFPLR3_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_PORT_VC_CNTL 0x400c47 |
| #define regBIFPLR3_0_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_PORT_VC_STATUS 0x400c47 |
| #define regBIFPLR3_0_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_VC0_RESOURCE_CAP 0x400c48 |
| #define regBIFPLR3_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_VC0_RESOURCE_CNTL 0x400c49 |
| #define regBIFPLR3_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_VC0_RESOURCE_STATUS 0x400c4a |
| #define regBIFPLR3_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_VC1_RESOURCE_CAP 0x400c4b |
| #define regBIFPLR3_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_VC1_RESOURCE_CNTL 0x400c4c |
| #define regBIFPLR3_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_VC1_RESOURCE_STATUS 0x400c4d |
| #define regBIFPLR3_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x400c50 |
| #define regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1 0x400c51 |
| #define regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2 0x400c52 |
| #define regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x400c54 |
| #define regBIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_UNCORR_ERR_STATUS 0x400c55 |
| #define regBIFPLR3_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_UNCORR_ERR_MASK 0x400c56 |
| #define regBIFPLR3_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY 0x400c57 |
| #define regBIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CORR_ERR_STATUS 0x400c58 |
| #define regBIFPLR3_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CORR_ERR_MASK 0x400c59 |
| #define regBIFPLR3_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL 0x400c5a |
| #define regBIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_HDR_LOG0 0x400c5b |
| #define regBIFPLR3_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_HDR_LOG1 0x400c5c |
| #define regBIFPLR3_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_HDR_LOG2 0x400c5d |
| #define regBIFPLR3_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_HDR_LOG3 0x400c5e |
| #define regBIFPLR3_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ROOT_ERR_CMD 0x400c5f |
| #define regBIFPLR3_0_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ROOT_ERR_STATUS 0x400c60 |
| #define regBIFPLR3_0_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ERR_SRC_ID 0x400c61 |
| #define regBIFPLR3_0_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG0 0x400c62 |
| #define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG1 0x400c63 |
| #define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG2 0x400c64 |
| #define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG3 0x400c65 |
| #define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST 0x400c9c |
| #define regBIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LINK_CNTL3 0x400c9d |
| #define regBIFPLR3_0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_ERROR_STATUS 0x400c9e |
| #define regBIFPLR3_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x400c9f |
| #define regBIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x400c9f |
| #define regBIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x400ca0 |
| #define regBIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x400ca0 |
| #define regBIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x400ca1 |
| #define regBIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x400ca1 |
| #define regBIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x400ca2 |
| #define regBIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x400ca2 |
| #define regBIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x400ca3 |
| #define regBIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x400ca3 |
| #define regBIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x400ca4 |
| #define regBIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x400ca4 |
| #define regBIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x400ca5 |
| #define regBIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x400ca5 |
| #define regBIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x400ca6 |
| #define regBIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x400ca6 |
| #define regBIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ACS_ENH_CAP_LIST 0x400ca8 |
| #define regBIFPLR3_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ACS_CAP 0x400ca9 |
| #define regBIFPLR3_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ACS_CNTL 0x400ca9 |
| #define regBIFPLR3_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_ENH_CAP_LIST 0x400cbc |
| #define regBIFPLR3_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_CAP 0x400cbd |
| #define regBIFPLR3_0_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_CNTL 0x400cbd |
| #define regBIFPLR3_0_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_ADDR0 0x400cbe |
| #define regBIFPLR3_0_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_ADDR1 0x400cbf |
| #define regBIFPLR3_0_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_RCV0 0x400cc0 |
| #define regBIFPLR3_0_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_RCV1 0x400cc1 |
| #define regBIFPLR3_0_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_BLOCK_ALL0 0x400cc2 |
| #define regBIFPLR3_0_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_BLOCK_ALL1 0x400cc3 |
| #define regBIFPLR3_0_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x400cc4 |
| #define regBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x400cc5 |
| #define regBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_OVERLAY_BAR0 0x400cc6 |
| #define regBIFPLR3_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MC_OVERLAY_BAR1 0x400cc7 |
| #define regBIFPLR3_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST 0x400cdc |
| #define regBIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_L1_PM_SUB_CAP 0x400cdd |
| #define regBIFPLR3_0_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_L1_PM_SUB_CNTL 0x400cde |
| #define regBIFPLR3_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_L1_PM_SUB_CNTL2 0x400cdf |
| #define regBIFPLR3_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_DPC_ENH_CAP_LIST 0x400ce0 |
| #define regBIFPLR3_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_DPC_CAP_LIST 0x400ce1 |
| #define regBIFPLR3_0_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_DPC_CNTL 0x400ce1 |
| #define regBIFPLR3_0_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_DPC_STATUS 0x400ce2 |
| #define regBIFPLR3_0_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID 0x400ce2 |
| #define regBIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_STATUS 0x400ce3 |
| #define regBIFPLR3_0_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_MASK 0x400ce4 |
| #define regBIFPLR3_0_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_SEVERITY 0x400ce5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_SYSERROR 0x400ce6 |
| #define regBIFPLR3_0_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_EXCEPTION 0x400ce7 |
| #define regBIFPLR3_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG0 0x400ce8 |
| #define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG1 0x400ce9 |
| #define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG2 0x400cea |
| #define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG3 0x400ceb |
| #define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0 0x400ced |
| #define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1 0x400cee |
| #define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2 0x400cef |
| #define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3 0x400cf0 |
| #define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_LIST 0x400cf1 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ESM_HEADER_1 0x400cf2 |
| #define regBIFPLR3_0_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ESM_HEADER_2 0x400cf3 |
| #define regBIFPLR3_0_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ESM_STATUS 0x400cf3 |
| #define regBIFPLR3_0_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ESM_CTRL 0x400cf4 |
| #define regBIFPLR3_0_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_1 0x400cf5 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_2 0x400cf6 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_3 0x400cf7 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_4 0x400cf8 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_5 0x400cf9 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_6 0x400cfa |
| #define regBIFPLR3_0_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_ESM_CAP_7 0x400cfb |
| #define regBIFPLR3_0_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_DLF_ENH_CAP_LIST 0x400d00 |
| #define regBIFPLR3_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_DATA_LINK_FEATURE_CAP 0x400d01 |
| #define regBIFPLR3_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_DATA_LINK_FEATURE_STATUS 0x400d02 |
| #define regBIFPLR3_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x400d04 |
| #define regBIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_LINK_CAP_16GT 0x400d05 |
| #define regBIFPLR3_0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LINK_CNTL_16GT 0x400d06 |
| #define regBIFPLR3_0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LINK_STATUS_16GT 0x400d07 |
| #define regBIFPLR3_0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x400d08 |
| #define regBIFPLR3_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x400d09 |
| #define regBIFPLR3_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x400d0a |
| #define regBIFPLR3_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT 0x400d0c |
| #define regBIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT 0x400d0c |
| #define regBIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT 0x400d0c |
| #define regBIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT 0x400d0c |
| #define regBIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT 0x400d0d |
| #define regBIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT 0x400d0d |
| #define regBIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT 0x400d0d |
| #define regBIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT 0x400d0d |
| #define regBIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT 0x400d0e |
| #define regBIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT 0x400d0e |
| #define regBIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT 0x400d0e |
| #define regBIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT 0x400d0e |
| #define regBIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT 0x400d0f |
| #define regBIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT 0x400d0f |
| #define regBIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT 0x400d0f |
| #define regBIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT 0x400d0f |
| #define regBIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST 0x400d10 |
| #define regBIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_MARGINING_PORT_CAP 0x400d11 |
| #define regBIFPLR3_0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_MARGINING_PORT_STATUS 0x400d11 |
| #define regBIFPLR3_0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_0_MARGINING_LANE_CNTL 0x400d12 |
| #define regBIFPLR3_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_0_MARGINING_LANE_STATUS 0x400d12 |
| #define regBIFPLR3_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_1_MARGINING_LANE_CNTL 0x400d13 |
| #define regBIFPLR3_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_1_MARGINING_LANE_STATUS 0x400d13 |
| #define regBIFPLR3_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_2_MARGINING_LANE_CNTL 0x400d14 |
| #define regBIFPLR3_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_2_MARGINING_LANE_STATUS 0x400d14 |
| #define regBIFPLR3_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_3_MARGINING_LANE_CNTL 0x400d15 |
| #define regBIFPLR3_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_3_MARGINING_LANE_STATUS 0x400d15 |
| #define regBIFPLR3_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_4_MARGINING_LANE_CNTL 0x400d16 |
| #define regBIFPLR3_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_4_MARGINING_LANE_STATUS 0x400d16 |
| #define regBIFPLR3_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_5_MARGINING_LANE_CNTL 0x400d17 |
| #define regBIFPLR3_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_5_MARGINING_LANE_STATUS 0x400d17 |
| #define regBIFPLR3_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_6_MARGINING_LANE_CNTL 0x400d18 |
| #define regBIFPLR3_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_6_MARGINING_LANE_STATUS 0x400d18 |
| #define regBIFPLR3_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_7_MARGINING_LANE_CNTL 0x400d19 |
| #define regBIFPLR3_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_7_MARGINING_LANE_STATUS 0x400d19 |
| #define regBIFPLR3_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_8_MARGINING_LANE_CNTL 0x400d1a |
| #define regBIFPLR3_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_8_MARGINING_LANE_STATUS 0x400d1a |
| #define regBIFPLR3_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_9_MARGINING_LANE_CNTL 0x400d1b |
| #define regBIFPLR3_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_9_MARGINING_LANE_STATUS 0x400d1b |
| #define regBIFPLR3_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_10_MARGINING_LANE_CNTL 0x400d1c |
| #define regBIFPLR3_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_10_MARGINING_LANE_STATUS 0x400d1c |
| #define regBIFPLR3_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_11_MARGINING_LANE_CNTL 0x400d1d |
| #define regBIFPLR3_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_11_MARGINING_LANE_STATUS 0x400d1d |
| #define regBIFPLR3_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_12_MARGINING_LANE_CNTL 0x400d1e |
| #define regBIFPLR3_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_12_MARGINING_LANE_STATUS 0x400d1e |
| #define regBIFPLR3_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_13_MARGINING_LANE_CNTL 0x400d1f |
| #define regBIFPLR3_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_13_MARGINING_LANE_STATUS 0x400d1f |
| #define regBIFPLR3_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_14_MARGINING_LANE_CNTL 0x400d20 |
| #define regBIFPLR3_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_14_MARGINING_LANE_STATUS 0x400d20 |
| #define regBIFPLR3_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_15_MARGINING_LANE_CNTL 0x400d21 |
| #define regBIFPLR3_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LANE_15_MARGINING_LANE_STATUS 0x400d21 |
| #define regBIFPLR3_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CCIX_CAP_LIST 0x400d22 |
| #define regBIFPLR3_0_PCIE_CCIX_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CCIX_HEADER_1 0x400d23 |
| #define regBIFPLR3_0_PCIE_CCIX_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CCIX_HEADER_2 0x400d24 |
| #define regBIFPLR3_0_PCIE_CCIX_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CCIX_CAP 0x400d24 |
| #define regBIFPLR3_0_PCIE_CCIX_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP 0x400d25 |
| #define regBIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CCIX_ESM_OPTL_CAP 0x400d26 |
| #define regBIFPLR3_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CCIX_ESM_STATUS 0x400d27 |
| #define regBIFPLR3_0_PCIE_CCIX_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CCIX_ESM_CNTL 0x400d28 |
| #define regBIFPLR3_0_PCIE_CCIX_ESM_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x400d29 |
| #define regBIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x400d29 |
| #define regBIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x400d29 |
| #define regBIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x400d29 |
| #define regBIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x400d2a |
| #define regBIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x400d2a |
| #define regBIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x400d2a |
| #define regBIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x400d2a |
| #define regBIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x400d2b |
| #define regBIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x400d2b |
| #define regBIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x400d2b |
| #define regBIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x400d2b |
| #define regBIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x400d2c |
| #define regBIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x400d2c |
| #define regBIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x400d2c |
| #define regBIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x400d2c |
| #define regBIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x400d2d |
| #define regBIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x400d2d |
| #define regBIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x400d2d |
| #define regBIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x400d2d |
| #define regBIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x400d2e |
| #define regBIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x400d2e |
| #define regBIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x400d2e |
| #define regBIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x400d2e |
| #define regBIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x400d2f |
| #define regBIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x400d2f |
| #define regBIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x400d2f |
| #define regBIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x400d2f |
| #define regBIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x400d30 |
| #define regBIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x400d30 |
| #define regBIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x400d30 |
| #define regBIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x400d30 |
| #define regBIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CCIX_TRANS_CAP 0x400d31 |
| #define regBIFPLR3_0_PCIE_CCIX_TRANS_CAP_BASE_IDX 5 |
| #define regBIFPLR3_0_PCIE_CCIX_TRANS_CNTL 0x400d32 |
| #define regBIFPLR3_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_0_LINK_CAP_32GT 0x400d41 |
| #define regBIFPLR3_0_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LINK_CNTL_32GT 0x400d42 |
| #define regBIFPLR3_0_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR3_0_LINK_STATUS_32GT 0x400d43 |
| #define regBIFPLR3_0_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifplr4_cfgdecp |
| // base address: 0x11104000 |
| #define regBIFPLR4_0_VENDOR_ID 0x401000 |
| #define regBIFPLR4_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR4_0_DEVICE_ID 0x401000 |
| #define regBIFPLR4_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR4_0_COMMAND 0x401001 |
| #define regBIFPLR4_0_COMMAND_BASE_IDX 5 |
| #define regBIFPLR4_0_STATUS 0x401001 |
| #define regBIFPLR4_0_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_REVISION_ID 0x401002 |
| #define regBIFPLR4_0_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR4_0_PROG_INTERFACE 0x401002 |
| #define regBIFPLR4_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR4_0_SUB_CLASS 0x401002 |
| #define regBIFPLR4_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR4_0_BASE_CLASS 0x401002 |
| #define regBIFPLR4_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR4_0_CACHE_LINE 0x401003 |
| #define regBIFPLR4_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR4_0_LATENCY 0x401003 |
| #define regBIFPLR4_0_LATENCY_BASE_IDX 5 |
| #define regBIFPLR4_0_HEADER 0x401003 |
| #define regBIFPLR4_0_HEADER_BASE_IDX 5 |
| #define regBIFPLR4_0_BIST 0x401003 |
| #define regBIFPLR4_0_BIST_BASE_IDX 5 |
| #define regBIFPLR4_0_SUB_BUS_NUMBER_LATENCY 0x401006 |
| #define regBIFPLR4_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR4_0_IO_BASE_LIMIT 0x401007 |
| #define regBIFPLR4_0_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR4_0_SECONDARY_STATUS 0x401007 |
| #define regBIFPLR4_0_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_MEM_BASE_LIMIT 0x401008 |
| #define regBIFPLR4_0_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR4_0_PREF_BASE_LIMIT 0x401009 |
| #define regBIFPLR4_0_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR4_0_PREF_BASE_UPPER 0x40100a |
| #define regBIFPLR4_0_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR4_0_PREF_LIMIT_UPPER 0x40100b |
| #define regBIFPLR4_0_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR4_0_IO_BASE_LIMIT_HI 0x40100c |
| #define regBIFPLR4_0_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR4_0_CAP_PTR 0x40100d |
| #define regBIFPLR4_0_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR4_0_ROM_BASE_ADDR 0x40100e |
| #define regBIFPLR4_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIFPLR4_0_INTERRUPT_LINE 0x40100f |
| #define regBIFPLR4_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR4_0_INTERRUPT_PIN 0x40100f |
| #define regBIFPLR4_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR4_0_EXT_BRIDGE_CNTL 0x401010 |
| #define regBIFPLR4_0_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_VENDOR_CAP_LIST 0x401012 |
| #define regBIFPLR4_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_ADAPTER_ID_W 0x401013 |
| #define regBIFPLR4_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIFPLR4_0_PMI_CAP_LIST 0x401014 |
| #define regBIFPLR4_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PMI_CAP 0x401014 |
| #define regBIFPLR4_0_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_PMI_STATUS_CNTL 0x401015 |
| #define regBIFPLR4_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CAP_LIST 0x401016 |
| #define regBIFPLR4_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CAP 0x401016 |
| #define regBIFPLR4_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_DEVICE_CAP 0x401017 |
| #define regBIFPLR4_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_DEVICE_CNTL 0x401018 |
| #define regBIFPLR4_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_DEVICE_STATUS 0x401018 |
| #define regBIFPLR4_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LINK_CAP 0x401019 |
| #define regBIFPLR4_0_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_LINK_CNTL 0x40101a |
| #define regBIFPLR4_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LINK_STATUS 0x40101a |
| #define regBIFPLR4_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_SLOT_CAP 0x40101b |
| #define regBIFPLR4_0_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_SLOT_CNTL 0x40101c |
| #define regBIFPLR4_0_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_SLOT_STATUS 0x40101c |
| #define regBIFPLR4_0_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_ROOT_CNTL 0x40101d |
| #define regBIFPLR4_0_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_ROOT_CAP 0x40101d |
| #define regBIFPLR4_0_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_ROOT_STATUS 0x40101e |
| #define regBIFPLR4_0_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_DEVICE_CAP2 0x40101f |
| #define regBIFPLR4_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR4_0_DEVICE_CNTL2 0x401020 |
| #define regBIFPLR4_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_0_DEVICE_STATUS2 0x401020 |
| #define regBIFPLR4_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR4_0_LINK_CAP2 0x401021 |
| #define regBIFPLR4_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR4_0_LINK_CNTL2 0x401022 |
| #define regBIFPLR4_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_0_LINK_STATUS2 0x401022 |
| #define regBIFPLR4_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR4_0_SLOT_CAP2 0x401023 |
| #define regBIFPLR4_0_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR4_0_SLOT_CNTL2 0x401024 |
| #define regBIFPLR4_0_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_0_SLOT_STATUS2 0x401024 |
| #define regBIFPLR4_0_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR4_0_MSI_CAP_LIST 0x401028 |
| #define regBIFPLR4_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_MSI_MSG_CNTL 0x401028 |
| #define regBIFPLR4_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_MSI_MSG_ADDR_LO 0x401029 |
| #define regBIFPLR4_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR4_0_MSI_MSG_ADDR_HI 0x40102a |
| #define regBIFPLR4_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR4_0_MSI_MSG_DATA 0x40102a |
| #define regBIFPLR4_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR4_0_MSI_MSG_DATA_64 0x40102b |
| #define regBIFPLR4_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR4_0_SSID_CAP_LIST 0x401030 |
| #define regBIFPLR4_0_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_SSID_CAP 0x401031 |
| #define regBIFPLR4_0_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_MSI_MAP_CAP_LIST 0x401032 |
| #define regBIFPLR4_0_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_MSI_MAP_CAP 0x401032 |
| #define regBIFPLR4_0_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x401040 |
| #define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR 0x401041 |
| #define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC1 0x401042 |
| #define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC2 0x401043 |
| #define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_VC_ENH_CAP_LIST 0x401044 |
| #define regBIFPLR4_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_PORT_VC_CAP_REG1 0x401045 |
| #define regBIFPLR4_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_PORT_VC_CAP_REG2 0x401046 |
| #define regBIFPLR4_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_PORT_VC_CNTL 0x401047 |
| #define regBIFPLR4_0_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_PORT_VC_STATUS 0x401047 |
| #define regBIFPLR4_0_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_VC0_RESOURCE_CAP 0x401048 |
| #define regBIFPLR4_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_VC0_RESOURCE_CNTL 0x401049 |
| #define regBIFPLR4_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_VC0_RESOURCE_STATUS 0x40104a |
| #define regBIFPLR4_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_VC1_RESOURCE_CAP 0x40104b |
| #define regBIFPLR4_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_VC1_RESOURCE_CNTL 0x40104c |
| #define regBIFPLR4_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_VC1_RESOURCE_STATUS 0x40104d |
| #define regBIFPLR4_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x401050 |
| #define regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1 0x401051 |
| #define regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2 0x401052 |
| #define regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x401054 |
| #define regBIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_UNCORR_ERR_STATUS 0x401055 |
| #define regBIFPLR4_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_UNCORR_ERR_MASK 0x401056 |
| #define regBIFPLR4_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY 0x401057 |
| #define regBIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CORR_ERR_STATUS 0x401058 |
| #define regBIFPLR4_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CORR_ERR_MASK 0x401059 |
| #define regBIFPLR4_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL 0x40105a |
| #define regBIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_HDR_LOG0 0x40105b |
| #define regBIFPLR4_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_HDR_LOG1 0x40105c |
| #define regBIFPLR4_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_HDR_LOG2 0x40105d |
| #define regBIFPLR4_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_HDR_LOG3 0x40105e |
| #define regBIFPLR4_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ROOT_ERR_CMD 0x40105f |
| #define regBIFPLR4_0_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ROOT_ERR_STATUS 0x401060 |
| #define regBIFPLR4_0_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ERR_SRC_ID 0x401061 |
| #define regBIFPLR4_0_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG0 0x401062 |
| #define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG1 0x401063 |
| #define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG2 0x401064 |
| #define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG3 0x401065 |
| #define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST 0x40109c |
| #define regBIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LINK_CNTL3 0x40109d |
| #define regBIFPLR4_0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_ERROR_STATUS 0x40109e |
| #define regBIFPLR4_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x40109f |
| #define regBIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x40109f |
| #define regBIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x4010a0 |
| #define regBIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x4010a0 |
| #define regBIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x4010a1 |
| #define regBIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x4010a1 |
| #define regBIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x4010a2 |
| #define regBIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x4010a2 |
| #define regBIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x4010a3 |
| #define regBIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x4010a3 |
| #define regBIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x4010a4 |
| #define regBIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x4010a4 |
| #define regBIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x4010a5 |
| #define regBIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x4010a5 |
| #define regBIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x4010a6 |
| #define regBIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x4010a6 |
| #define regBIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ACS_ENH_CAP_LIST 0x4010a8 |
| #define regBIFPLR4_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ACS_CAP 0x4010a9 |
| #define regBIFPLR4_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ACS_CNTL 0x4010a9 |
| #define regBIFPLR4_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_ENH_CAP_LIST 0x4010bc |
| #define regBIFPLR4_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_CAP 0x4010bd |
| #define regBIFPLR4_0_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_CNTL 0x4010bd |
| #define regBIFPLR4_0_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_ADDR0 0x4010be |
| #define regBIFPLR4_0_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_ADDR1 0x4010bf |
| #define regBIFPLR4_0_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_RCV0 0x4010c0 |
| #define regBIFPLR4_0_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_RCV1 0x4010c1 |
| #define regBIFPLR4_0_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_BLOCK_ALL0 0x4010c2 |
| #define regBIFPLR4_0_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_BLOCK_ALL1 0x4010c3 |
| #define regBIFPLR4_0_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x4010c4 |
| #define regBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x4010c5 |
| #define regBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_OVERLAY_BAR0 0x4010c6 |
| #define regBIFPLR4_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MC_OVERLAY_BAR1 0x4010c7 |
| #define regBIFPLR4_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST 0x4010dc |
| #define regBIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_L1_PM_SUB_CAP 0x4010dd |
| #define regBIFPLR4_0_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_L1_PM_SUB_CNTL 0x4010de |
| #define regBIFPLR4_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_L1_PM_SUB_CNTL2 0x4010df |
| #define regBIFPLR4_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_DPC_ENH_CAP_LIST 0x4010e0 |
| #define regBIFPLR4_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_DPC_CAP_LIST 0x4010e1 |
| #define regBIFPLR4_0_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_DPC_CNTL 0x4010e1 |
| #define regBIFPLR4_0_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_DPC_STATUS 0x4010e2 |
| #define regBIFPLR4_0_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID 0x4010e2 |
| #define regBIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_STATUS 0x4010e3 |
| #define regBIFPLR4_0_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_MASK 0x4010e4 |
| #define regBIFPLR4_0_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_SEVERITY 0x4010e5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_SYSERROR 0x4010e6 |
| #define regBIFPLR4_0_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_EXCEPTION 0x4010e7 |
| #define regBIFPLR4_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG0 0x4010e8 |
| #define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG1 0x4010e9 |
| #define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG2 0x4010ea |
| #define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG3 0x4010eb |
| #define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0 0x4010ed |
| #define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1 0x4010ee |
| #define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2 0x4010ef |
| #define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3 0x4010f0 |
| #define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_LIST 0x4010f1 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ESM_HEADER_1 0x4010f2 |
| #define regBIFPLR4_0_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ESM_HEADER_2 0x4010f3 |
| #define regBIFPLR4_0_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ESM_STATUS 0x4010f3 |
| #define regBIFPLR4_0_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ESM_CTRL 0x4010f4 |
| #define regBIFPLR4_0_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_1 0x4010f5 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_2 0x4010f6 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_3 0x4010f7 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_4 0x4010f8 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_5 0x4010f9 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_6 0x4010fa |
| #define regBIFPLR4_0_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_ESM_CAP_7 0x4010fb |
| #define regBIFPLR4_0_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_DLF_ENH_CAP_LIST 0x401100 |
| #define regBIFPLR4_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_DATA_LINK_FEATURE_CAP 0x401101 |
| #define regBIFPLR4_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_DATA_LINK_FEATURE_STATUS 0x401102 |
| #define regBIFPLR4_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x401104 |
| #define regBIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_LINK_CAP_16GT 0x401105 |
| #define regBIFPLR4_0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LINK_CNTL_16GT 0x401106 |
| #define regBIFPLR4_0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LINK_STATUS_16GT 0x401107 |
| #define regBIFPLR4_0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x401108 |
| #define regBIFPLR4_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x401109 |
| #define regBIFPLR4_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x40110a |
| #define regBIFPLR4_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT 0x40110c |
| #define regBIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT 0x40110c |
| #define regBIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT 0x40110c |
| #define regBIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT 0x40110c |
| #define regBIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT 0x40110d |
| #define regBIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT 0x40110d |
| #define regBIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT 0x40110d |
| #define regBIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT 0x40110d |
| #define regBIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT 0x40110e |
| #define regBIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT 0x40110e |
| #define regBIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT 0x40110e |
| #define regBIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT 0x40110e |
| #define regBIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT 0x40110f |
| #define regBIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT 0x40110f |
| #define regBIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT 0x40110f |
| #define regBIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT 0x40110f |
| #define regBIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST 0x401110 |
| #define regBIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_MARGINING_PORT_CAP 0x401111 |
| #define regBIFPLR4_0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_MARGINING_PORT_STATUS 0x401111 |
| #define regBIFPLR4_0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_0_MARGINING_LANE_CNTL 0x401112 |
| #define regBIFPLR4_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_0_MARGINING_LANE_STATUS 0x401112 |
| #define regBIFPLR4_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_1_MARGINING_LANE_CNTL 0x401113 |
| #define regBIFPLR4_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_1_MARGINING_LANE_STATUS 0x401113 |
| #define regBIFPLR4_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_2_MARGINING_LANE_CNTL 0x401114 |
| #define regBIFPLR4_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_2_MARGINING_LANE_STATUS 0x401114 |
| #define regBIFPLR4_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_3_MARGINING_LANE_CNTL 0x401115 |
| #define regBIFPLR4_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_3_MARGINING_LANE_STATUS 0x401115 |
| #define regBIFPLR4_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_4_MARGINING_LANE_CNTL 0x401116 |
| #define regBIFPLR4_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_4_MARGINING_LANE_STATUS 0x401116 |
| #define regBIFPLR4_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_5_MARGINING_LANE_CNTL 0x401117 |
| #define regBIFPLR4_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_5_MARGINING_LANE_STATUS 0x401117 |
| #define regBIFPLR4_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_6_MARGINING_LANE_CNTL 0x401118 |
| #define regBIFPLR4_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_6_MARGINING_LANE_STATUS 0x401118 |
| #define regBIFPLR4_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_7_MARGINING_LANE_CNTL 0x401119 |
| #define regBIFPLR4_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_7_MARGINING_LANE_STATUS 0x401119 |
| #define regBIFPLR4_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_8_MARGINING_LANE_CNTL 0x40111a |
| #define regBIFPLR4_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_8_MARGINING_LANE_STATUS 0x40111a |
| #define regBIFPLR4_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_9_MARGINING_LANE_CNTL 0x40111b |
| #define regBIFPLR4_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_9_MARGINING_LANE_STATUS 0x40111b |
| #define regBIFPLR4_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_10_MARGINING_LANE_CNTL 0x40111c |
| #define regBIFPLR4_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_10_MARGINING_LANE_STATUS 0x40111c |
| #define regBIFPLR4_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_11_MARGINING_LANE_CNTL 0x40111d |
| #define regBIFPLR4_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_11_MARGINING_LANE_STATUS 0x40111d |
| #define regBIFPLR4_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_12_MARGINING_LANE_CNTL 0x40111e |
| #define regBIFPLR4_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_12_MARGINING_LANE_STATUS 0x40111e |
| #define regBIFPLR4_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_13_MARGINING_LANE_CNTL 0x40111f |
| #define regBIFPLR4_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_13_MARGINING_LANE_STATUS 0x40111f |
| #define regBIFPLR4_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_14_MARGINING_LANE_CNTL 0x401120 |
| #define regBIFPLR4_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_14_MARGINING_LANE_STATUS 0x401120 |
| #define regBIFPLR4_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_15_MARGINING_LANE_CNTL 0x401121 |
| #define regBIFPLR4_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LANE_15_MARGINING_LANE_STATUS 0x401121 |
| #define regBIFPLR4_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CCIX_CAP_LIST 0x401122 |
| #define regBIFPLR4_0_PCIE_CCIX_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CCIX_HEADER_1 0x401123 |
| #define regBIFPLR4_0_PCIE_CCIX_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CCIX_HEADER_2 0x401124 |
| #define regBIFPLR4_0_PCIE_CCIX_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CCIX_CAP 0x401124 |
| #define regBIFPLR4_0_PCIE_CCIX_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP 0x401125 |
| #define regBIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CCIX_ESM_OPTL_CAP 0x401126 |
| #define regBIFPLR4_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CCIX_ESM_STATUS 0x401127 |
| #define regBIFPLR4_0_PCIE_CCIX_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CCIX_ESM_CNTL 0x401128 |
| #define regBIFPLR4_0_PCIE_CCIX_ESM_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x401129 |
| #define regBIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x401129 |
| #define regBIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x401129 |
| #define regBIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x401129 |
| #define regBIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x40112a |
| #define regBIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x40112a |
| #define regBIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x40112a |
| #define regBIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x40112a |
| #define regBIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x40112b |
| #define regBIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x40112b |
| #define regBIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x40112b |
| #define regBIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x40112b |
| #define regBIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x40112c |
| #define regBIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x40112c |
| #define regBIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x40112c |
| #define regBIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x40112c |
| #define regBIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x40112d |
| #define regBIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x40112d |
| #define regBIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x40112d |
| #define regBIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x40112d |
| #define regBIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x40112e |
| #define regBIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x40112e |
| #define regBIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x40112e |
| #define regBIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x40112e |
| #define regBIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x40112f |
| #define regBIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x40112f |
| #define regBIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x40112f |
| #define regBIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x40112f |
| #define regBIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x401130 |
| #define regBIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x401130 |
| #define regBIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x401130 |
| #define regBIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x401130 |
| #define regBIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CCIX_TRANS_CAP 0x401131 |
| #define regBIFPLR4_0_PCIE_CCIX_TRANS_CAP_BASE_IDX 5 |
| #define regBIFPLR4_0_PCIE_CCIX_TRANS_CNTL 0x401132 |
| #define regBIFPLR4_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_0_LINK_CAP_32GT 0x401141 |
| #define regBIFPLR4_0_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LINK_CNTL_32GT 0x401142 |
| #define regBIFPLR4_0_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR4_0_LINK_STATUS_32GT 0x401143 |
| #define regBIFPLR4_0_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifp0_pciedir_p |
| // base address: 0x11140000 |
| #define regBIFP0_0_PCIEP_RESERVED 0x410000 |
| #define regBIFP0_0_PCIEP_RESERVED_BASE_IDX 5 |
| #define regBIFP0_0_PCIEP_SCRATCH 0x410001 |
| #define regBIFP0_0_PCIEP_SCRATCH_BASE_IDX 5 |
| #define regBIFP0_0_PCIEP_PORT_CNTL 0x410010 |
| #define regBIFP0_0_PCIEP_PORT_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_REQUESTER_ID 0x410021 |
| #define regBIFP0_0_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_P_PORT_LANE_STATUS 0x410050 |
| #define regBIFP0_0_PCIE_P_PORT_LANE_STATUS_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_ERR_CNTL 0x41006a |
| #define regBIFP0_0_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_RX_CNTL 0x410070 |
| #define regBIFP0_0_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_RX_EXPECTED_SEQNUM 0x410071 |
| #define regBIFP0_0_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_RX_VENDOR_SPECIFIC 0x410072 |
| #define regBIFP0_0_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_RX_CNTL3 0x410074 |
| #define regBIFP0_0_PCIE_RX_CNTL3_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_RX_CREDITS_ALLOCATED_P 0x410080 |
| #define regBIFP0_0_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_RX_CREDITS_ALLOCATED_NP 0x410081 |
| #define regBIFP0_0_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_RX_CREDITS_ALLOCATED_CPL 0x410082 |
| #define regBIFP0_0_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 |
| #define regBIFP0_0_PCIEP_ERROR_INJECT_PHYSICAL 0x410083 |
| #define regBIFP0_0_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 |
| #define regBIFP0_0_PCIEP_ERROR_INJECT_TRANSACTION 0x410084 |
| #define regBIFP0_0_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 |
| #define regBIFP0_0_PCIEP_NAK_COUNTER 0x410086 |
| #define regBIFP0_0_PCIEP_NAK_COUNTER_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CNTL 0x4100a0 |
| #define regBIFP0_0_PCIE_LC_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_TRAINING_CNTL 0x4100a1 |
| #define regBIFP0_0_PCIE_LC_TRAINING_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_LINK_WIDTH_CNTL 0x4100a2 |
| #define regBIFP0_0_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_N_FTS_CNTL 0x4100a3 |
| #define regBIFP0_0_PCIE_LC_N_FTS_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_SPEED_CNTL 0x4100a4 |
| #define regBIFP0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_STATE0 0x4100a5 |
| #define regBIFP0_0_PCIE_LC_STATE0_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_STATE1 0x4100a6 |
| #define regBIFP0_0_PCIE_LC_STATE1_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_STATE2 0x4100a7 |
| #define regBIFP0_0_PCIE_LC_STATE2_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_STATE3 0x4100a8 |
| #define regBIFP0_0_PCIE_LC_STATE3_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_STATE4 0x4100a9 |
| #define regBIFP0_0_PCIE_LC_STATE4_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_STATE5 0x4100aa |
| #define regBIFP0_0_PCIE_LC_STATE5_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CNTL2 0x4100b1 |
| #define regBIFP0_0_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_BW_CHANGE_CNTL 0x4100b2 |
| #define regBIFP0_0_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CDR_CNTL 0x4100b3 |
| #define regBIFP0_0_PCIE_LC_CDR_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_LANE_CNTL 0x4100b4 |
| #define regBIFP0_0_PCIE_LC_LANE_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CNTL3 0x4100b5 |
| #define regBIFP0_0_PCIE_LC_CNTL3_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CNTL4 0x4100b6 |
| #define regBIFP0_0_PCIE_LC_CNTL4_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CNTL5 0x4100b7 |
| #define regBIFP0_0_PCIE_LC_CNTL5_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_FORCE_COEFF 0x4100b8 |
| #define regBIFP0_0_PCIE_LC_FORCE_COEFF_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_BEST_EQ_SETTINGS 0x4100b9 |
| #define regBIFP0_0_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_FORCE_EQ_REQ_COEFF 0x4100ba |
| #define regBIFP0_0_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CNTL6 0x4100bb |
| #define regBIFP0_0_PCIE_LC_CNTL6_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CNTL7 0x4100bc |
| #define regBIFP0_0_PCIE_LC_CNTL7_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_LINK_MANAGEMENT_MASK 0x4100be |
| #define regBIFP0_0_PCIE_LC_LINK_MANAGEMENT_MASK_BASE_IDX 5 |
| #define regBIFP0_0_PCIEP_STRAP_LC 0x4100c0 |
| #define regBIFP0_0_PCIEP_STRAP_LC_BASE_IDX 5 |
| #define regBIFP0_0_PCIEP_STRAP_MISC 0x4100c1 |
| #define regBIFP0_0_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regBIFP0_0_PCIEP_STRAP_LC2 0x4100c2 |
| #define regBIFP0_0_PCIEP_STRAP_LC2_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_L1_PM_SUBSTATE 0x4100c6 |
| #define regBIFP0_0_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_L1_PM_SUBSTATE2 0x4100c7 |
| #define regBIFP0_0_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_L1_PM_SUBSTATE3 0x4100c8 |
| #define regBIFP0_0_PCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_L1_PM_SUBSTATE4 0x4100c9 |
| #define regBIFP0_0_PCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_L1_PM_SUBSTATE5 0x4100ca |
| #define regBIFP0_0_PCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 |
| #define regBIFP0_0_PCIEP_BCH_ECC_CNTL 0x4100d0 |
| #define regBIFP0_0_PCIEP_BCH_ECC_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CNTL8 0x4100dd |
| #define regBIFP0_0_PCIE_LC_CNTL8_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CNTL9 0x4100de |
| #define regBIFP0_0_PCIE_LC_CNTL9_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_FORCE_COEFF2 0x4100df |
| #define regBIFP0_0_PCIE_LC_FORCE_COEFF2_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_FORCE_EQ_REQ_COEFF2 0x4100e0 |
| #define regBIFP0_0_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x4100e2 |
| #define regBIFP0_0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CNTL10 0x4100e3 |
| #define regBIFP0_0_PCIE_LC_CNTL10_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_SAVE_RESTORE_1 0x4100e6 |
| #define regBIFP0_0_PCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_SAVE_RESTORE_2 0x4100e7 |
| #define regBIFP0_0_PCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CNTL11 0x410103 |
| #define regBIFP0_0_PCIE_LC_CNTL11_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_CNTL12 0x410104 |
| #define regBIFP0_0_PCIE_LC_CNTL12_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_SPEED_CNTL2 0x410105 |
| #define regBIFP0_0_PCIE_LC_SPEED_CNTL2_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_FORCE_COEFF3 0x410106 |
| #define regBIFP0_0_PCIE_LC_FORCE_COEFF3_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_LC_FORCE_EQ_REQ_COEFF3 0x410107 |
| #define regBIFP0_0_PCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_SEQ 0x410188 |
| #define regBIFP0_0_PCIE_TX_SEQ_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_REPLAY 0x410189 |
| #define regBIFP0_0_PCIE_TX_REPLAY_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_ACK_LATENCY_LIMIT 0x41018c |
| #define regBIFP0_0_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_CREDITS_FCU_THRESHOLD 0x410190 |
| #define regBIFP0_0_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_VENDOR_SPECIFIC 0x410194 |
| #define regBIFP0_0_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_NOP_DLLP 0x410195 |
| #define regBIFP0_0_PCIE_TX_NOP_DLLP_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_REQUEST_NUM_CNTL 0x410198 |
| #define regBIFP0_0_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_CREDITS_ADVT_P 0x4101a0 |
| #define regBIFP0_0_PCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_CREDITS_ADVT_NP 0x4101a1 |
| #define regBIFP0_0_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_CREDITS_ADVT_CPL 0x4101a2 |
| #define regBIFP0_0_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_CREDITS_INIT_P 0x4101a3 |
| #define regBIFP0_0_PCIE_TX_CREDITS_INIT_P_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_CREDITS_INIT_NP 0x4101a4 |
| #define regBIFP0_0_PCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_CREDITS_INIT_CPL 0x4101a5 |
| #define regBIFP0_0_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_TX_CREDITS_STATUS 0x4101a6 |
| #define regBIFP0_0_PCIE_TX_CREDITS_STATUS_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_FC_P 0x4101a8 |
| #define regBIFP0_0_PCIE_FC_P_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_FC_NP 0x4101a9 |
| #define regBIFP0_0_PCIE_FC_NP_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_FC_CPL 0x4101aa |
| #define regBIFP0_0_PCIE_FC_CPL_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_FC_P_VC1 0x4101ab |
| #define regBIFP0_0_PCIE_FC_P_VC1_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_FC_NP_VC1 0x4101ac |
| #define regBIFP0_0_PCIE_FC_NP_VC1_BASE_IDX 5 |
| #define regBIFP0_0_PCIE_FC_CPL_VC1 0x4101ad |
| #define regBIFP0_0_PCIE_FC_CPL_VC1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifp1_pciedir_p |
| // base address: 0x11141000 |
| #define regBIFP1_0_PCIEP_RESERVED 0x410400 |
| #define regBIFP1_0_PCIEP_RESERVED_BASE_IDX 5 |
| #define regBIFP1_0_PCIEP_SCRATCH 0x410401 |
| #define regBIFP1_0_PCIEP_SCRATCH_BASE_IDX 5 |
| #define regBIFP1_0_PCIEP_PORT_CNTL 0x410410 |
| #define regBIFP1_0_PCIEP_PORT_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_REQUESTER_ID 0x410421 |
| #define regBIFP1_0_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_P_PORT_LANE_STATUS 0x410450 |
| #define regBIFP1_0_PCIE_P_PORT_LANE_STATUS_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_ERR_CNTL 0x41046a |
| #define regBIFP1_0_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_RX_CNTL 0x410470 |
| #define regBIFP1_0_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_RX_EXPECTED_SEQNUM 0x410471 |
| #define regBIFP1_0_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_RX_VENDOR_SPECIFIC 0x410472 |
| #define regBIFP1_0_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_RX_CNTL3 0x410474 |
| #define regBIFP1_0_PCIE_RX_CNTL3_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_RX_CREDITS_ALLOCATED_P 0x410480 |
| #define regBIFP1_0_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_RX_CREDITS_ALLOCATED_NP 0x410481 |
| #define regBIFP1_0_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_RX_CREDITS_ALLOCATED_CPL 0x410482 |
| #define regBIFP1_0_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 |
| #define regBIFP1_0_PCIEP_ERROR_INJECT_PHYSICAL 0x410483 |
| #define regBIFP1_0_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 |
| #define regBIFP1_0_PCIEP_ERROR_INJECT_TRANSACTION 0x410484 |
| #define regBIFP1_0_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 |
| #define regBIFP1_0_PCIEP_NAK_COUNTER 0x410486 |
| #define regBIFP1_0_PCIEP_NAK_COUNTER_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CNTL 0x4104a0 |
| #define regBIFP1_0_PCIE_LC_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_TRAINING_CNTL 0x4104a1 |
| #define regBIFP1_0_PCIE_LC_TRAINING_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_LINK_WIDTH_CNTL 0x4104a2 |
| #define regBIFP1_0_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_N_FTS_CNTL 0x4104a3 |
| #define regBIFP1_0_PCIE_LC_N_FTS_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_SPEED_CNTL 0x4104a4 |
| #define regBIFP1_0_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_STATE0 0x4104a5 |
| #define regBIFP1_0_PCIE_LC_STATE0_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_STATE1 0x4104a6 |
| #define regBIFP1_0_PCIE_LC_STATE1_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_STATE2 0x4104a7 |
| #define regBIFP1_0_PCIE_LC_STATE2_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_STATE3 0x4104a8 |
| #define regBIFP1_0_PCIE_LC_STATE3_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_STATE4 0x4104a9 |
| #define regBIFP1_0_PCIE_LC_STATE4_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_STATE5 0x4104aa |
| #define regBIFP1_0_PCIE_LC_STATE5_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CNTL2 0x4104b1 |
| #define regBIFP1_0_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_BW_CHANGE_CNTL 0x4104b2 |
| #define regBIFP1_0_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CDR_CNTL 0x4104b3 |
| #define regBIFP1_0_PCIE_LC_CDR_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_LANE_CNTL 0x4104b4 |
| #define regBIFP1_0_PCIE_LC_LANE_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CNTL3 0x4104b5 |
| #define regBIFP1_0_PCIE_LC_CNTL3_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CNTL4 0x4104b6 |
| #define regBIFP1_0_PCIE_LC_CNTL4_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CNTL5 0x4104b7 |
| #define regBIFP1_0_PCIE_LC_CNTL5_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_FORCE_COEFF 0x4104b8 |
| #define regBIFP1_0_PCIE_LC_FORCE_COEFF_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_BEST_EQ_SETTINGS 0x4104b9 |
| #define regBIFP1_0_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_FORCE_EQ_REQ_COEFF 0x4104ba |
| #define regBIFP1_0_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CNTL6 0x4104bb |
| #define regBIFP1_0_PCIE_LC_CNTL6_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CNTL7 0x4104bc |
| #define regBIFP1_0_PCIE_LC_CNTL7_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_LINK_MANAGEMENT_MASK 0x4104be |
| #define regBIFP1_0_PCIE_LC_LINK_MANAGEMENT_MASK_BASE_IDX 5 |
| #define regBIFP1_0_PCIEP_STRAP_LC 0x4104c0 |
| #define regBIFP1_0_PCIEP_STRAP_LC_BASE_IDX 5 |
| #define regBIFP1_0_PCIEP_STRAP_MISC 0x4104c1 |
| #define regBIFP1_0_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regBIFP1_0_PCIEP_STRAP_LC2 0x4104c2 |
| #define regBIFP1_0_PCIEP_STRAP_LC2_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_L1_PM_SUBSTATE 0x4104c6 |
| #define regBIFP1_0_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_L1_PM_SUBSTATE2 0x4104c7 |
| #define regBIFP1_0_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_L1_PM_SUBSTATE3 0x4104c8 |
| #define regBIFP1_0_PCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_L1_PM_SUBSTATE4 0x4104c9 |
| #define regBIFP1_0_PCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_L1_PM_SUBSTATE5 0x4104ca |
| #define regBIFP1_0_PCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 |
| #define regBIFP1_0_PCIEP_BCH_ECC_CNTL 0x4104d0 |
| #define regBIFP1_0_PCIEP_BCH_ECC_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CNTL8 0x4104dd |
| #define regBIFP1_0_PCIE_LC_CNTL8_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CNTL9 0x4104de |
| #define regBIFP1_0_PCIE_LC_CNTL9_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_FORCE_COEFF2 0x4104df |
| #define regBIFP1_0_PCIE_LC_FORCE_COEFF2_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_FORCE_EQ_REQ_COEFF2 0x4104e0 |
| #define regBIFP1_0_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x4104e2 |
| #define regBIFP1_0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CNTL10 0x4104e3 |
| #define regBIFP1_0_PCIE_LC_CNTL10_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_SAVE_RESTORE_1 0x4104e6 |
| #define regBIFP1_0_PCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_SAVE_RESTORE_2 0x4104e7 |
| #define regBIFP1_0_PCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CNTL11 0x410503 |
| #define regBIFP1_0_PCIE_LC_CNTL11_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_CNTL12 0x410504 |
| #define regBIFP1_0_PCIE_LC_CNTL12_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_SPEED_CNTL2 0x410505 |
| #define regBIFP1_0_PCIE_LC_SPEED_CNTL2_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_FORCE_COEFF3 0x410506 |
| #define regBIFP1_0_PCIE_LC_FORCE_COEFF3_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_LC_FORCE_EQ_REQ_COEFF3 0x410507 |
| #define regBIFP1_0_PCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_SEQ 0x410588 |
| #define regBIFP1_0_PCIE_TX_SEQ_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_REPLAY 0x410589 |
| #define regBIFP1_0_PCIE_TX_REPLAY_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_ACK_LATENCY_LIMIT 0x41058c |
| #define regBIFP1_0_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_CREDITS_FCU_THRESHOLD 0x410590 |
| #define regBIFP1_0_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_VENDOR_SPECIFIC 0x410594 |
| #define regBIFP1_0_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_NOP_DLLP 0x410595 |
| #define regBIFP1_0_PCIE_TX_NOP_DLLP_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_REQUEST_NUM_CNTL 0x410598 |
| #define regBIFP1_0_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_CREDITS_ADVT_P 0x4105a0 |
| #define regBIFP1_0_PCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_CREDITS_ADVT_NP 0x4105a1 |
| #define regBIFP1_0_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_CREDITS_ADVT_CPL 0x4105a2 |
| #define regBIFP1_0_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_CREDITS_INIT_P 0x4105a3 |
| #define regBIFP1_0_PCIE_TX_CREDITS_INIT_P_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_CREDITS_INIT_NP 0x4105a4 |
| #define regBIFP1_0_PCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_CREDITS_INIT_CPL 0x4105a5 |
| #define regBIFP1_0_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_TX_CREDITS_STATUS 0x4105a6 |
| #define regBIFP1_0_PCIE_TX_CREDITS_STATUS_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_FC_P 0x4105a8 |
| #define regBIFP1_0_PCIE_FC_P_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_FC_NP 0x4105a9 |
| #define regBIFP1_0_PCIE_FC_NP_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_FC_CPL 0x4105aa |
| #define regBIFP1_0_PCIE_FC_CPL_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_FC_P_VC1 0x4105ab |
| #define regBIFP1_0_PCIE_FC_P_VC1_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_FC_NP_VC1 0x4105ac |
| #define regBIFP1_0_PCIE_FC_NP_VC1_BASE_IDX 5 |
| #define regBIFP1_0_PCIE_FC_CPL_VC1 0x4105ad |
| #define regBIFP1_0_PCIE_FC_CPL_VC1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifp2_pciedir_p |
| // base address: 0x11142000 |
| #define regBIFP2_0_PCIEP_RESERVED 0x410800 |
| #define regBIFP2_0_PCIEP_RESERVED_BASE_IDX 5 |
| #define regBIFP2_0_PCIEP_SCRATCH 0x410801 |
| #define regBIFP2_0_PCIEP_SCRATCH_BASE_IDX 5 |
| #define regBIFP2_0_PCIEP_PORT_CNTL 0x410810 |
| #define regBIFP2_0_PCIEP_PORT_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_REQUESTER_ID 0x410821 |
| #define regBIFP2_0_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_P_PORT_LANE_STATUS 0x410850 |
| #define regBIFP2_0_PCIE_P_PORT_LANE_STATUS_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_ERR_CNTL 0x41086a |
| #define regBIFP2_0_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_RX_CNTL 0x410870 |
| #define regBIFP2_0_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_RX_EXPECTED_SEQNUM 0x410871 |
| #define regBIFP2_0_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_RX_VENDOR_SPECIFIC 0x410872 |
| #define regBIFP2_0_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_RX_CNTL3 0x410874 |
| #define regBIFP2_0_PCIE_RX_CNTL3_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_RX_CREDITS_ALLOCATED_P 0x410880 |
| #define regBIFP2_0_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_RX_CREDITS_ALLOCATED_NP 0x410881 |
| #define regBIFP2_0_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_RX_CREDITS_ALLOCATED_CPL 0x410882 |
| #define regBIFP2_0_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 |
| #define regBIFP2_0_PCIEP_ERROR_INJECT_PHYSICAL 0x410883 |
| #define regBIFP2_0_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 |
| #define regBIFP2_0_PCIEP_ERROR_INJECT_TRANSACTION 0x410884 |
| #define regBIFP2_0_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 |
| #define regBIFP2_0_PCIEP_NAK_COUNTER 0x410886 |
| #define regBIFP2_0_PCIEP_NAK_COUNTER_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CNTL 0x4108a0 |
| #define regBIFP2_0_PCIE_LC_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_TRAINING_CNTL 0x4108a1 |
| #define regBIFP2_0_PCIE_LC_TRAINING_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_LINK_WIDTH_CNTL 0x4108a2 |
| #define regBIFP2_0_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_N_FTS_CNTL 0x4108a3 |
| #define regBIFP2_0_PCIE_LC_N_FTS_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_SPEED_CNTL 0x4108a4 |
| #define regBIFP2_0_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_STATE0 0x4108a5 |
| #define regBIFP2_0_PCIE_LC_STATE0_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_STATE1 0x4108a6 |
| #define regBIFP2_0_PCIE_LC_STATE1_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_STATE2 0x4108a7 |
| #define regBIFP2_0_PCIE_LC_STATE2_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_STATE3 0x4108a8 |
| #define regBIFP2_0_PCIE_LC_STATE3_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_STATE4 0x4108a9 |
| #define regBIFP2_0_PCIE_LC_STATE4_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_STATE5 0x4108aa |
| #define regBIFP2_0_PCIE_LC_STATE5_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CNTL2 0x4108b1 |
| #define regBIFP2_0_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_BW_CHANGE_CNTL 0x4108b2 |
| #define regBIFP2_0_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CDR_CNTL 0x4108b3 |
| #define regBIFP2_0_PCIE_LC_CDR_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_LANE_CNTL 0x4108b4 |
| #define regBIFP2_0_PCIE_LC_LANE_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CNTL3 0x4108b5 |
| #define regBIFP2_0_PCIE_LC_CNTL3_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CNTL4 0x4108b6 |
| #define regBIFP2_0_PCIE_LC_CNTL4_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CNTL5 0x4108b7 |
| #define regBIFP2_0_PCIE_LC_CNTL5_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_FORCE_COEFF 0x4108b8 |
| #define regBIFP2_0_PCIE_LC_FORCE_COEFF_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_BEST_EQ_SETTINGS 0x4108b9 |
| #define regBIFP2_0_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_FORCE_EQ_REQ_COEFF 0x4108ba |
| #define regBIFP2_0_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CNTL6 0x4108bb |
| #define regBIFP2_0_PCIE_LC_CNTL6_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CNTL7 0x4108bc |
| #define regBIFP2_0_PCIE_LC_CNTL7_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_LINK_MANAGEMENT_MASK 0x4108be |
| #define regBIFP2_0_PCIE_LC_LINK_MANAGEMENT_MASK_BASE_IDX 5 |
| #define regBIFP2_0_PCIEP_STRAP_LC 0x4108c0 |
| #define regBIFP2_0_PCIEP_STRAP_LC_BASE_IDX 5 |
| #define regBIFP2_0_PCIEP_STRAP_MISC 0x4108c1 |
| #define regBIFP2_0_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regBIFP2_0_PCIEP_STRAP_LC2 0x4108c2 |
| #define regBIFP2_0_PCIEP_STRAP_LC2_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_L1_PM_SUBSTATE 0x4108c6 |
| #define regBIFP2_0_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_L1_PM_SUBSTATE2 0x4108c7 |
| #define regBIFP2_0_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_L1_PM_SUBSTATE3 0x4108c8 |
| #define regBIFP2_0_PCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_L1_PM_SUBSTATE4 0x4108c9 |
| #define regBIFP2_0_PCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_L1_PM_SUBSTATE5 0x4108ca |
| #define regBIFP2_0_PCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 |
| #define regBIFP2_0_PCIEP_BCH_ECC_CNTL 0x4108d0 |
| #define regBIFP2_0_PCIEP_BCH_ECC_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CNTL8 0x4108dd |
| #define regBIFP2_0_PCIE_LC_CNTL8_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CNTL9 0x4108de |
| #define regBIFP2_0_PCIE_LC_CNTL9_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_FORCE_COEFF2 0x4108df |
| #define regBIFP2_0_PCIE_LC_FORCE_COEFF2_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_FORCE_EQ_REQ_COEFF2 0x4108e0 |
| #define regBIFP2_0_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x4108e2 |
| #define regBIFP2_0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CNTL10 0x4108e3 |
| #define regBIFP2_0_PCIE_LC_CNTL10_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_SAVE_RESTORE_1 0x4108e6 |
| #define regBIFP2_0_PCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_SAVE_RESTORE_2 0x4108e7 |
| #define regBIFP2_0_PCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CNTL11 0x410903 |
| #define regBIFP2_0_PCIE_LC_CNTL11_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_CNTL12 0x410904 |
| #define regBIFP2_0_PCIE_LC_CNTL12_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_SPEED_CNTL2 0x410905 |
| #define regBIFP2_0_PCIE_LC_SPEED_CNTL2_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_FORCE_COEFF3 0x410906 |
| #define regBIFP2_0_PCIE_LC_FORCE_COEFF3_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_LC_FORCE_EQ_REQ_COEFF3 0x410907 |
| #define regBIFP2_0_PCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_SEQ 0x410988 |
| #define regBIFP2_0_PCIE_TX_SEQ_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_REPLAY 0x410989 |
| #define regBIFP2_0_PCIE_TX_REPLAY_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_ACK_LATENCY_LIMIT 0x41098c |
| #define regBIFP2_0_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_CREDITS_FCU_THRESHOLD 0x410990 |
| #define regBIFP2_0_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_VENDOR_SPECIFIC 0x410994 |
| #define regBIFP2_0_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_NOP_DLLP 0x410995 |
| #define regBIFP2_0_PCIE_TX_NOP_DLLP_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_REQUEST_NUM_CNTL 0x410998 |
| #define regBIFP2_0_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_CREDITS_ADVT_P 0x4109a0 |
| #define regBIFP2_0_PCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_CREDITS_ADVT_NP 0x4109a1 |
| #define regBIFP2_0_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_CREDITS_ADVT_CPL 0x4109a2 |
| #define regBIFP2_0_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_CREDITS_INIT_P 0x4109a3 |
| #define regBIFP2_0_PCIE_TX_CREDITS_INIT_P_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_CREDITS_INIT_NP 0x4109a4 |
| #define regBIFP2_0_PCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_CREDITS_INIT_CPL 0x4109a5 |
| #define regBIFP2_0_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_TX_CREDITS_STATUS 0x4109a6 |
| #define regBIFP2_0_PCIE_TX_CREDITS_STATUS_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_FC_P 0x4109a8 |
| #define regBIFP2_0_PCIE_FC_P_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_FC_NP 0x4109a9 |
| #define regBIFP2_0_PCIE_FC_NP_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_FC_CPL 0x4109aa |
| #define regBIFP2_0_PCIE_FC_CPL_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_FC_P_VC1 0x4109ab |
| #define regBIFP2_0_PCIE_FC_P_VC1_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_FC_NP_VC1 0x4109ac |
| #define regBIFP2_0_PCIE_FC_NP_VC1_BASE_IDX 5 |
| #define regBIFP2_0_PCIE_FC_CPL_VC1 0x4109ad |
| #define regBIFP2_0_PCIE_FC_CPL_VC1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifp3_pciedir_p |
| // base address: 0x11143000 |
| #define regBIFP3_0_PCIEP_RESERVED 0x410c00 |
| #define regBIFP3_0_PCIEP_RESERVED_BASE_IDX 5 |
| #define regBIFP3_0_PCIEP_SCRATCH 0x410c01 |
| #define regBIFP3_0_PCIEP_SCRATCH_BASE_IDX 5 |
| #define regBIFP3_0_PCIEP_PORT_CNTL 0x410c10 |
| #define regBIFP3_0_PCIEP_PORT_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_REQUESTER_ID 0x410c21 |
| #define regBIFP3_0_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_P_PORT_LANE_STATUS 0x410c50 |
| #define regBIFP3_0_PCIE_P_PORT_LANE_STATUS_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_ERR_CNTL 0x410c6a |
| #define regBIFP3_0_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_RX_CNTL 0x410c70 |
| #define regBIFP3_0_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_RX_EXPECTED_SEQNUM 0x410c71 |
| #define regBIFP3_0_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_RX_VENDOR_SPECIFIC 0x410c72 |
| #define regBIFP3_0_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_RX_CNTL3 0x410c74 |
| #define regBIFP3_0_PCIE_RX_CNTL3_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_RX_CREDITS_ALLOCATED_P 0x410c80 |
| #define regBIFP3_0_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_RX_CREDITS_ALLOCATED_NP 0x410c81 |
| #define regBIFP3_0_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_RX_CREDITS_ALLOCATED_CPL 0x410c82 |
| #define regBIFP3_0_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 |
| #define regBIFP3_0_PCIEP_ERROR_INJECT_PHYSICAL 0x410c83 |
| #define regBIFP3_0_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 |
| #define regBIFP3_0_PCIEP_ERROR_INJECT_TRANSACTION 0x410c84 |
| #define regBIFP3_0_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 |
| #define regBIFP3_0_PCIEP_NAK_COUNTER 0x410c86 |
| #define regBIFP3_0_PCIEP_NAK_COUNTER_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CNTL 0x410ca0 |
| #define regBIFP3_0_PCIE_LC_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_TRAINING_CNTL 0x410ca1 |
| #define regBIFP3_0_PCIE_LC_TRAINING_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_LINK_WIDTH_CNTL 0x410ca2 |
| #define regBIFP3_0_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_N_FTS_CNTL 0x410ca3 |
| #define regBIFP3_0_PCIE_LC_N_FTS_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_SPEED_CNTL 0x410ca4 |
| #define regBIFP3_0_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_STATE0 0x410ca5 |
| #define regBIFP3_0_PCIE_LC_STATE0_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_STATE1 0x410ca6 |
| #define regBIFP3_0_PCIE_LC_STATE1_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_STATE2 0x410ca7 |
| #define regBIFP3_0_PCIE_LC_STATE2_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_STATE3 0x410ca8 |
| #define regBIFP3_0_PCIE_LC_STATE3_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_STATE4 0x410ca9 |
| #define regBIFP3_0_PCIE_LC_STATE4_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_STATE5 0x410caa |
| #define regBIFP3_0_PCIE_LC_STATE5_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CNTL2 0x410cb1 |
| #define regBIFP3_0_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_BW_CHANGE_CNTL 0x410cb2 |
| #define regBIFP3_0_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CDR_CNTL 0x410cb3 |
| #define regBIFP3_0_PCIE_LC_CDR_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_LANE_CNTL 0x410cb4 |
| #define regBIFP3_0_PCIE_LC_LANE_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CNTL3 0x410cb5 |
| #define regBIFP3_0_PCIE_LC_CNTL3_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CNTL4 0x410cb6 |
| #define regBIFP3_0_PCIE_LC_CNTL4_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CNTL5 0x410cb7 |
| #define regBIFP3_0_PCIE_LC_CNTL5_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_FORCE_COEFF 0x410cb8 |
| #define regBIFP3_0_PCIE_LC_FORCE_COEFF_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_BEST_EQ_SETTINGS 0x410cb9 |
| #define regBIFP3_0_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_FORCE_EQ_REQ_COEFF 0x410cba |
| #define regBIFP3_0_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CNTL6 0x410cbb |
| #define regBIFP3_0_PCIE_LC_CNTL6_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CNTL7 0x410cbc |
| #define regBIFP3_0_PCIE_LC_CNTL7_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_LINK_MANAGEMENT_MASK 0x410cbe |
| #define regBIFP3_0_PCIE_LC_LINK_MANAGEMENT_MASK_BASE_IDX 5 |
| #define regBIFP3_0_PCIEP_STRAP_LC 0x410cc0 |
| #define regBIFP3_0_PCIEP_STRAP_LC_BASE_IDX 5 |
| #define regBIFP3_0_PCIEP_STRAP_MISC 0x410cc1 |
| #define regBIFP3_0_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regBIFP3_0_PCIEP_STRAP_LC2 0x410cc2 |
| #define regBIFP3_0_PCIEP_STRAP_LC2_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_L1_PM_SUBSTATE 0x410cc6 |
| #define regBIFP3_0_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_L1_PM_SUBSTATE2 0x410cc7 |
| #define regBIFP3_0_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_L1_PM_SUBSTATE3 0x410cc8 |
| #define regBIFP3_0_PCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_L1_PM_SUBSTATE4 0x410cc9 |
| #define regBIFP3_0_PCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_L1_PM_SUBSTATE5 0x410cca |
| #define regBIFP3_0_PCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 |
| #define regBIFP3_0_PCIEP_BCH_ECC_CNTL 0x410cd0 |
| #define regBIFP3_0_PCIEP_BCH_ECC_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CNTL8 0x410cdd |
| #define regBIFP3_0_PCIE_LC_CNTL8_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CNTL9 0x410cde |
| #define regBIFP3_0_PCIE_LC_CNTL9_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_FORCE_COEFF2 0x410cdf |
| #define regBIFP3_0_PCIE_LC_FORCE_COEFF2_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_FORCE_EQ_REQ_COEFF2 0x410ce0 |
| #define regBIFP3_0_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x410ce2 |
| #define regBIFP3_0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CNTL10 0x410ce3 |
| #define regBIFP3_0_PCIE_LC_CNTL10_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_SAVE_RESTORE_1 0x410ce6 |
| #define regBIFP3_0_PCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_SAVE_RESTORE_2 0x410ce7 |
| #define regBIFP3_0_PCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CNTL11 0x410d03 |
| #define regBIFP3_0_PCIE_LC_CNTL11_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_CNTL12 0x410d04 |
| #define regBIFP3_0_PCIE_LC_CNTL12_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_SPEED_CNTL2 0x410d05 |
| #define regBIFP3_0_PCIE_LC_SPEED_CNTL2_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_FORCE_COEFF3 0x410d06 |
| #define regBIFP3_0_PCIE_LC_FORCE_COEFF3_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_LC_FORCE_EQ_REQ_COEFF3 0x410d07 |
| #define regBIFP3_0_PCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_SEQ 0x410d88 |
| #define regBIFP3_0_PCIE_TX_SEQ_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_REPLAY 0x410d89 |
| #define regBIFP3_0_PCIE_TX_REPLAY_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_ACK_LATENCY_LIMIT 0x410d8c |
| #define regBIFP3_0_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_CREDITS_FCU_THRESHOLD 0x410d90 |
| #define regBIFP3_0_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_VENDOR_SPECIFIC 0x410d94 |
| #define regBIFP3_0_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_NOP_DLLP 0x410d95 |
| #define regBIFP3_0_PCIE_TX_NOP_DLLP_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_REQUEST_NUM_CNTL 0x410d98 |
| #define regBIFP3_0_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_CREDITS_ADVT_P 0x410da0 |
| #define regBIFP3_0_PCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_CREDITS_ADVT_NP 0x410da1 |
| #define regBIFP3_0_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_CREDITS_ADVT_CPL 0x410da2 |
| #define regBIFP3_0_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_CREDITS_INIT_P 0x410da3 |
| #define regBIFP3_0_PCIE_TX_CREDITS_INIT_P_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_CREDITS_INIT_NP 0x410da4 |
| #define regBIFP3_0_PCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_CREDITS_INIT_CPL 0x410da5 |
| #define regBIFP3_0_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_TX_CREDITS_STATUS 0x410da6 |
| #define regBIFP3_0_PCIE_TX_CREDITS_STATUS_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_FC_P 0x410da8 |
| #define regBIFP3_0_PCIE_FC_P_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_FC_NP 0x410da9 |
| #define regBIFP3_0_PCIE_FC_NP_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_FC_CPL 0x410daa |
| #define regBIFP3_0_PCIE_FC_CPL_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_FC_P_VC1 0x410dab |
| #define regBIFP3_0_PCIE_FC_P_VC1_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_FC_NP_VC1 0x410dac |
| #define regBIFP3_0_PCIE_FC_NP_VC1_BASE_IDX 5 |
| #define regBIFP3_0_PCIE_FC_CPL_VC1 0x410dad |
| #define regBIFP3_0_PCIE_FC_CPL_VC1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifp4_pciedir_p |
| // base address: 0x11144000 |
| #define regBIFP4_0_PCIEP_RESERVED 0x411000 |
| #define regBIFP4_0_PCIEP_RESERVED_BASE_IDX 5 |
| #define regBIFP4_0_PCIEP_SCRATCH 0x411001 |
| #define regBIFP4_0_PCIEP_SCRATCH_BASE_IDX 5 |
| #define regBIFP4_0_PCIEP_PORT_CNTL 0x411010 |
| #define regBIFP4_0_PCIEP_PORT_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_REQUESTER_ID 0x411021 |
| #define regBIFP4_0_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_P_PORT_LANE_STATUS 0x411050 |
| #define regBIFP4_0_PCIE_P_PORT_LANE_STATUS_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_ERR_CNTL 0x41106a |
| #define regBIFP4_0_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_RX_CNTL 0x411070 |
| #define regBIFP4_0_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_RX_EXPECTED_SEQNUM 0x411071 |
| #define regBIFP4_0_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_RX_VENDOR_SPECIFIC 0x411072 |
| #define regBIFP4_0_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_RX_CNTL3 0x411074 |
| #define regBIFP4_0_PCIE_RX_CNTL3_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_RX_CREDITS_ALLOCATED_P 0x411080 |
| #define regBIFP4_0_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_RX_CREDITS_ALLOCATED_NP 0x411081 |
| #define regBIFP4_0_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_RX_CREDITS_ALLOCATED_CPL 0x411082 |
| #define regBIFP4_0_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 |
| #define regBIFP4_0_PCIEP_ERROR_INJECT_PHYSICAL 0x411083 |
| #define regBIFP4_0_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 |
| #define regBIFP4_0_PCIEP_ERROR_INJECT_TRANSACTION 0x411084 |
| #define regBIFP4_0_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 |
| #define regBIFP4_0_PCIEP_NAK_COUNTER 0x411086 |
| #define regBIFP4_0_PCIEP_NAK_COUNTER_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CNTL 0x4110a0 |
| #define regBIFP4_0_PCIE_LC_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_TRAINING_CNTL 0x4110a1 |
| #define regBIFP4_0_PCIE_LC_TRAINING_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_LINK_WIDTH_CNTL 0x4110a2 |
| #define regBIFP4_0_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_N_FTS_CNTL 0x4110a3 |
| #define regBIFP4_0_PCIE_LC_N_FTS_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_SPEED_CNTL 0x4110a4 |
| #define regBIFP4_0_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_STATE0 0x4110a5 |
| #define regBIFP4_0_PCIE_LC_STATE0_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_STATE1 0x4110a6 |
| #define regBIFP4_0_PCIE_LC_STATE1_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_STATE2 0x4110a7 |
| #define regBIFP4_0_PCIE_LC_STATE2_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_STATE3 0x4110a8 |
| #define regBIFP4_0_PCIE_LC_STATE3_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_STATE4 0x4110a9 |
| #define regBIFP4_0_PCIE_LC_STATE4_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_STATE5 0x4110aa |
| #define regBIFP4_0_PCIE_LC_STATE5_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CNTL2 0x4110b1 |
| #define regBIFP4_0_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_BW_CHANGE_CNTL 0x4110b2 |
| #define regBIFP4_0_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CDR_CNTL 0x4110b3 |
| #define regBIFP4_0_PCIE_LC_CDR_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_LANE_CNTL 0x4110b4 |
| #define regBIFP4_0_PCIE_LC_LANE_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CNTL3 0x4110b5 |
| #define regBIFP4_0_PCIE_LC_CNTL3_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CNTL4 0x4110b6 |
| #define regBIFP4_0_PCIE_LC_CNTL4_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CNTL5 0x4110b7 |
| #define regBIFP4_0_PCIE_LC_CNTL5_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_FORCE_COEFF 0x4110b8 |
| #define regBIFP4_0_PCIE_LC_FORCE_COEFF_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_BEST_EQ_SETTINGS 0x4110b9 |
| #define regBIFP4_0_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_FORCE_EQ_REQ_COEFF 0x4110ba |
| #define regBIFP4_0_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CNTL6 0x4110bb |
| #define regBIFP4_0_PCIE_LC_CNTL6_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CNTL7 0x4110bc |
| #define regBIFP4_0_PCIE_LC_CNTL7_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_LINK_MANAGEMENT_MASK 0x4110be |
| #define regBIFP4_0_PCIE_LC_LINK_MANAGEMENT_MASK_BASE_IDX 5 |
| #define regBIFP4_0_PCIEP_STRAP_LC 0x4110c0 |
| #define regBIFP4_0_PCIEP_STRAP_LC_BASE_IDX 5 |
| #define regBIFP4_0_PCIEP_STRAP_MISC 0x4110c1 |
| #define regBIFP4_0_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regBIFP4_0_PCIEP_STRAP_LC2 0x4110c2 |
| #define regBIFP4_0_PCIEP_STRAP_LC2_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_L1_PM_SUBSTATE 0x4110c6 |
| #define regBIFP4_0_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_L1_PM_SUBSTATE2 0x4110c7 |
| #define regBIFP4_0_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_L1_PM_SUBSTATE3 0x4110c8 |
| #define regBIFP4_0_PCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_L1_PM_SUBSTATE4 0x4110c9 |
| #define regBIFP4_0_PCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_L1_PM_SUBSTATE5 0x4110ca |
| #define regBIFP4_0_PCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 |
| #define regBIFP4_0_PCIEP_BCH_ECC_CNTL 0x4110d0 |
| #define regBIFP4_0_PCIEP_BCH_ECC_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CNTL8 0x4110dd |
| #define regBIFP4_0_PCIE_LC_CNTL8_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CNTL9 0x4110de |
| #define regBIFP4_0_PCIE_LC_CNTL9_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_FORCE_COEFF2 0x4110df |
| #define regBIFP4_0_PCIE_LC_FORCE_COEFF2_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_FORCE_EQ_REQ_COEFF2 0x4110e0 |
| #define regBIFP4_0_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x4110e2 |
| #define regBIFP4_0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CNTL10 0x4110e3 |
| #define regBIFP4_0_PCIE_LC_CNTL10_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_SAVE_RESTORE_1 0x4110e6 |
| #define regBIFP4_0_PCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_SAVE_RESTORE_2 0x4110e7 |
| #define regBIFP4_0_PCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CNTL11 0x411103 |
| #define regBIFP4_0_PCIE_LC_CNTL11_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_CNTL12 0x411104 |
| #define regBIFP4_0_PCIE_LC_CNTL12_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_SPEED_CNTL2 0x411105 |
| #define regBIFP4_0_PCIE_LC_SPEED_CNTL2_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_FORCE_COEFF3 0x411106 |
| #define regBIFP4_0_PCIE_LC_FORCE_COEFF3_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_LC_FORCE_EQ_REQ_COEFF3 0x411107 |
| #define regBIFP4_0_PCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_SEQ 0x411188 |
| #define regBIFP4_0_PCIE_TX_SEQ_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_REPLAY 0x411189 |
| #define regBIFP4_0_PCIE_TX_REPLAY_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_ACK_LATENCY_LIMIT 0x41118c |
| #define regBIFP4_0_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_CREDITS_FCU_THRESHOLD 0x411190 |
| #define regBIFP4_0_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_VENDOR_SPECIFIC 0x411194 |
| #define regBIFP4_0_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_NOP_DLLP 0x411195 |
| #define regBIFP4_0_PCIE_TX_NOP_DLLP_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_REQUEST_NUM_CNTL 0x411198 |
| #define regBIFP4_0_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_CREDITS_ADVT_P 0x4111a0 |
| #define regBIFP4_0_PCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_CREDITS_ADVT_NP 0x4111a1 |
| #define regBIFP4_0_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_CREDITS_ADVT_CPL 0x4111a2 |
| #define regBIFP4_0_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_CREDITS_INIT_P 0x4111a3 |
| #define regBIFP4_0_PCIE_TX_CREDITS_INIT_P_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_CREDITS_INIT_NP 0x4111a4 |
| #define regBIFP4_0_PCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_CREDITS_INIT_CPL 0x4111a5 |
| #define regBIFP4_0_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_TX_CREDITS_STATUS 0x4111a6 |
| #define regBIFP4_0_PCIE_TX_CREDITS_STATUS_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_FC_P 0x4111a8 |
| #define regBIFP4_0_PCIE_FC_P_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_FC_NP 0x4111a9 |
| #define regBIFP4_0_PCIE_FC_NP_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_FC_CPL 0x4111aa |
| #define regBIFP4_0_PCIE_FC_CPL_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_FC_P_VC1 0x4111ab |
| #define regBIFP4_0_PCIE_FC_P_VC1_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_FC_NP_VC1 0x4111ac |
| #define regBIFP4_0_PCIE_FC_NP_VC1_BASE_IDX 5 |
| #define regBIFP4_0_PCIE_FC_CPL_VC1 0x4111ad |
| #define regBIFP4_0_PCIE_FC_CPL_VC1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_pciedir |
| // base address: 0x11180000 |
| #define regBIF0_PCIE_RESERVED 0x420000 |
| #define regBIF0_PCIE_RESERVED_BASE_IDX 5 |
| #define regBIF0_PCIE_SCRATCH 0x420001 |
| #define regBIF0_PCIE_SCRATCH_BASE_IDX 5 |
| #define regBIF0_PCIE_RX_NUM_NAK 0x42000e |
| #define regBIF0_PCIE_RX_NUM_NAK_BASE_IDX 5 |
| #define regBIF0_PCIE_RX_NUM_NAK_GENERATED 0x42000f |
| #define regBIF0_PCIE_RX_NUM_NAK_GENERATED_BASE_IDX 5 |
| #define regBIF0_PCIE_CNTL 0x420010 |
| #define regBIF0_PCIE_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_CONFIG_CNTL 0x420011 |
| #define regBIF0_PCIE_CONFIG_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_DEBUG_CNTL 0x420012 |
| #define regBIF0_PCIE_DEBUG_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_RX_CNTL5 0x420018 |
| #define regBIF0_PCIE_RX_CNTL5_BASE_IDX 5 |
| #define regBIF0_PCIE_RX_CNTL4 0x420019 |
| #define regBIF0_PCIE_RX_CNTL4_BASE_IDX 5 |
| #define regBIF0_PCIE_COMMON_AER_MASK 0x42001a |
| #define regBIF0_PCIE_COMMON_AER_MASK_BASE_IDX 5 |
| #define regBIF0_PCIE_CNTL2 0x42001c |
| #define regBIF0_PCIE_CNTL2_BASE_IDX 5 |
| #define regBIF0_PCIE_RX_CNTL2 0x42001d |
| #define regBIF0_PCIE_RX_CNTL2_BASE_IDX 5 |
| #define regBIF0_PCIE_CI_CNTL 0x420020 |
| #define regBIF0_PCIE_CI_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_BUS_CNTL 0x420021 |
| #define regBIF0_PCIE_BUS_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_LC_STATE6 0x420022 |
| #define regBIF0_PCIE_LC_STATE6_BASE_IDX 5 |
| #define regBIF0_PCIE_LC_STATE7 0x420023 |
| #define regBIF0_PCIE_LC_STATE7_BASE_IDX 5 |
| #define regBIF0_PCIE_LC_STATE8 0x420024 |
| #define regBIF0_PCIE_LC_STATE8_BASE_IDX 5 |
| #define regBIF0_PCIE_LC_STATE9 0x420025 |
| #define regBIF0_PCIE_LC_STATE9_BASE_IDX 5 |
| #define regBIF0_PCIE_LC_STATE10 0x420026 |
| #define regBIF0_PCIE_LC_STATE10_BASE_IDX 5 |
| #define regBIF0_PCIE_LC_STATE11 0x420027 |
| #define regBIF0_PCIE_LC_STATE11_BASE_IDX 5 |
| #define regBIF0_PCIE_LC_STATUS1 0x420028 |
| #define regBIF0_PCIE_LC_STATUS1_BASE_IDX 5 |
| #define regBIF0_PCIE_LC_STATUS2 0x420029 |
| #define regBIF0_PCIE_LC_STATUS2_BASE_IDX 5 |
| #define regBIF0_PCIE_WPR_CNTL 0x420030 |
| #define regBIF0_PCIE_WPR_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_RX_LAST_TLP0 0x420031 |
| #define regBIF0_PCIE_RX_LAST_TLP0_BASE_IDX 5 |
| #define regBIF0_PCIE_RX_LAST_TLP1 0x420032 |
| #define regBIF0_PCIE_RX_LAST_TLP1_BASE_IDX 5 |
| #define regBIF0_PCIE_RX_LAST_TLP2 0x420033 |
| #define regBIF0_PCIE_RX_LAST_TLP2_BASE_IDX 5 |
| #define regBIF0_PCIE_RX_LAST_TLP3 0x420034 |
| #define regBIF0_PCIE_RX_LAST_TLP3_BASE_IDX 5 |
| #define regBIF0_PCIE_I2C_REG_ADDR_EXPAND 0x42003a |
| #define regBIF0_PCIE_I2C_REG_ADDR_EXPAND_BASE_IDX 5 |
| #define regBIF0_PCIE_I2C_REG_DATA 0x42003b |
| #define regBIF0_PCIE_I2C_REG_DATA_BASE_IDX 5 |
| #define regBIF0_PCIE_CFG_CNTL 0x42003c |
| #define regBIF0_PCIE_CFG_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_LC_PM_CNTL 0x42003d |
| #define regBIF0_PCIE_LC_PM_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_LC_PM_CNTL2 0x42003e |
| #define regBIF0_PCIE_LC_PM_CNTL2_BASE_IDX 5 |
| #define regBIF0_PCIE_P_CNTL 0x420040 |
| #define regBIF0_PCIE_P_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_P_BUF_STATUS 0x420041 |
| #define regBIF0_PCIE_P_BUF_STATUS_BASE_IDX 5 |
| #define regBIF0_PCIE_P_DECODER_STATUS 0x420042 |
| #define regBIF0_PCIE_P_DECODER_STATUS_BASE_IDX 5 |
| #define regBIF0_PCIE_P_MISC_STATUS 0x420043 |
| #define regBIF0_PCIE_P_MISC_STATUS_BASE_IDX 5 |
| #define regBIF0_PCIE_P_RCV_L0S_FTS_DET 0x420050 |
| #define regBIF0_PCIE_P_RCV_L0S_FTS_DET_BASE_IDX 5 |
| #define regBIF0_PCIE_RX_AD 0x420062 |
| #define regBIF0_PCIE_RX_AD_BASE_IDX 5 |
| #define regBIF0_PCIE_SDP_CTRL 0x420063 |
| #define regBIF0_PCIE_SDP_CTRL_BASE_IDX 5 |
| #define regBIF0_NBIO_CLKREQb_MAP_CNTL 0x420064 |
| #define regBIF0_NBIO_CLKREQb_MAP_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_SDP_SWUS_SLV_ATTR_CTRL 0x420065 |
| #define regBIF0_PCIE_SDP_SWUS_SLV_ATTR_CTRL_BASE_IDX 5 |
| #define regBIF0_PCIE_SDP_RC_SLV_ATTR_CTRL 0x420066 |
| #define regBIF0_PCIE_SDP_RC_SLV_ATTR_CTRL_BASE_IDX 5 |
| #define regBIF0_NBIO_CLKREQb_MAP_CNTL2 0x420067 |
| #define regBIF0_NBIO_CLKREQb_MAP_CNTL2_BASE_IDX 5 |
| #define regBIF0_PCIE_SDP_CTRL2 0x420068 |
| #define regBIF0_PCIE_SDP_CTRL2_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT_CNTL 0x420080 |
| #define regBIF0_PCIE_PERF_COUNT_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK1 0x420081 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK1_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK1 0x420082 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK1_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK1 0x420083 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK1_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK2 0x420084 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK2_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK2 0x420085 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK2_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK2 0x420086 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK2_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK3 0x420087 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK3_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK3 0x420088 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK3_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK3 0x420089 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK3_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK4 0x42008a |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK4_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK4 0x42008b |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK4_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK4 0x42008c |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK4_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_CNTL_EVENT_LC_PORT_SEL 0x420093 |
| #define regBIF0_PCIE_PERF_CNTL_EVENT_LC_PORT_SEL_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_CNTL_EVENT_CI_PORT_SEL 0x420094 |
| #define regBIF0_PCIE_PERF_CNTL_EVENT_CI_PORT_SEL_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK5 0x420096 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK5_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK5 0x420097 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK5_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK5 0x420098 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK5_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK6 0x420099 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK6_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK6 0x42009a |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK6_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK6 0x42009b |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK6_BASE_IDX 5 |
| #define regBIF0_PCIE_STRAP_F0 0x4200b0 |
| #define regBIF0_PCIE_STRAP_F0_BASE_IDX 5 |
| #define regBIF0_PCIE_STRAP_NTB 0x4200b1 |
| #define regBIF0_PCIE_STRAP_NTB_BASE_IDX 5 |
| #define regBIF0_PCIE_STRAP_MISC 0x4200c0 |
| #define regBIF0_PCIE_STRAP_MISC_BASE_IDX 5 |
| #define regBIF0_PCIE_STRAP_MISC2 0x4200c1 |
| #define regBIF0_PCIE_STRAP_MISC2_BASE_IDX 5 |
| #define regBIF0_PCIE_STRAP_PI 0x4200c2 |
| #define regBIF0_PCIE_STRAP_PI_BASE_IDX 5 |
| #define regBIF0_PCIE_STRAP_I2C_BD 0x4200c4 |
| #define regBIF0_PCIE_STRAP_I2C_BD_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_CLR 0x4200c8 |
| #define regBIF0_PCIE_PRBS_CLR_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_STATUS1 0x4200c9 |
| #define regBIF0_PCIE_PRBS_STATUS1_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_STATUS2 0x4200ca |
| #define regBIF0_PCIE_PRBS_STATUS2_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_FREERUN 0x4200cb |
| #define regBIF0_PCIE_PRBS_FREERUN_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_MISC 0x4200cc |
| #define regBIF0_PCIE_PRBS_MISC_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_USER_PATTERN 0x4200cd |
| #define regBIF0_PCIE_PRBS_USER_PATTERN_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_LO_BITCNT 0x4200ce |
| #define regBIF0_PCIE_PRBS_LO_BITCNT_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_HI_BITCNT 0x4200cf |
| #define regBIF0_PCIE_PRBS_HI_BITCNT_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_0 0x4200d0 |
| #define regBIF0_PCIE_PRBS_ERRCNT_0_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_1 0x4200d1 |
| #define regBIF0_PCIE_PRBS_ERRCNT_1_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_2 0x4200d2 |
| #define regBIF0_PCIE_PRBS_ERRCNT_2_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_3 0x4200d3 |
| #define regBIF0_PCIE_PRBS_ERRCNT_3_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_4 0x4200d4 |
| #define regBIF0_PCIE_PRBS_ERRCNT_4_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_5 0x4200d5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_5_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_6 0x4200d6 |
| #define regBIF0_PCIE_PRBS_ERRCNT_6_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_7 0x4200d7 |
| #define regBIF0_PCIE_PRBS_ERRCNT_7_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_8 0x4200d8 |
| #define regBIF0_PCIE_PRBS_ERRCNT_8_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_9 0x4200d9 |
| #define regBIF0_PCIE_PRBS_ERRCNT_9_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_10 0x4200da |
| #define regBIF0_PCIE_PRBS_ERRCNT_10_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_11 0x4200db |
| #define regBIF0_PCIE_PRBS_ERRCNT_11_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_12 0x4200dc |
| #define regBIF0_PCIE_PRBS_ERRCNT_12_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_13 0x4200dd |
| #define regBIF0_PCIE_PRBS_ERRCNT_13_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_14 0x4200de |
| #define regBIF0_PCIE_PRBS_ERRCNT_14_BASE_IDX 5 |
| #define regBIF0_PCIE_PRBS_ERRCNT_15 0x4200df |
| #define regBIF0_PCIE_PRBS_ERRCNT_15_BASE_IDX 5 |
| #define regBIF0_SWRST_COMMAND_STATUS 0x420100 |
| #define regBIF0_SWRST_COMMAND_STATUS_BASE_IDX 5 |
| #define regBIF0_SWRST_GENERAL_CONTROL 0x420101 |
| #define regBIF0_SWRST_GENERAL_CONTROL_BASE_IDX 5 |
| #define regBIF0_SWRST_COMMAND_0 0x420102 |
| #define regBIF0_SWRST_COMMAND_0_BASE_IDX 5 |
| #define regBIF0_SWRST_COMMAND_1 0x420103 |
| #define regBIF0_SWRST_COMMAND_1_BASE_IDX 5 |
| #define regBIF0_SWRST_CONTROL_0 0x420104 |
| #define regBIF0_SWRST_CONTROL_0_BASE_IDX 5 |
| #define regBIF0_SWRST_CONTROL_1 0x420105 |
| #define regBIF0_SWRST_CONTROL_1_BASE_IDX 5 |
| #define regBIF0_SWRST_CONTROL_2 0x420106 |
| #define regBIF0_SWRST_CONTROL_2_BASE_IDX 5 |
| #define regBIF0_SWRST_CONTROL_3 0x420107 |
| #define regBIF0_SWRST_CONTROL_3_BASE_IDX 5 |
| #define regBIF0_SWRST_CONTROL_4 0x420108 |
| #define regBIF0_SWRST_CONTROL_4_BASE_IDX 5 |
| #define regBIF0_SWRST_CONTROL_5 0x420109 |
| #define regBIF0_SWRST_CONTROL_5_BASE_IDX 5 |
| #define regBIF0_SWRST_CONTROL_6 0x42010a |
| #define regBIF0_SWRST_CONTROL_6_BASE_IDX 5 |
| #define regBIF0_SWRST_EP_COMMAND_0 0x42010b |
| #define regBIF0_SWRST_EP_COMMAND_0_BASE_IDX 5 |
| #define regBIF0_SWRST_EP_CONTROL_0 0x42010c |
| #define regBIF0_SWRST_EP_CONTROL_0_BASE_IDX 5 |
| #define regBIF0_CPM_CONTROL 0x420118 |
| #define regBIF0_CPM_CONTROL_BASE_IDX 5 |
| #define regBIF0_CPM_SPLIT_CONTROL 0x420119 |
| #define regBIF0_CPM_SPLIT_CONTROL_BASE_IDX 5 |
| #define regBIF0_CPM_CONTROL_EXT 0x42011a |
| #define regBIF0_CPM_CONTROL_EXT_BASE_IDX 5 |
| #define regBIF0_SMN_APERTURE_ID_A 0x42011d |
| #define regBIF0_SMN_APERTURE_ID_A_BASE_IDX 5 |
| #define regBIF0_SMN_APERTURE_ID_B 0x42011e |
| #define regBIF0_SMN_APERTURE_ID_B_BASE_IDX 5 |
| #define regBIF0_LNCNT_CONTROL 0x420125 |
| #define regBIF0_LNCNT_CONTROL_BASE_IDX 5 |
| #define regBIF0_SMU_HP_STATUS_UPDATE 0x42012c |
| #define regBIF0_SMU_HP_STATUS_UPDATE_BASE_IDX 5 |
| #define regBIF0_HP_SMU_COMMAND_UPDATE 0x42012d |
| #define regBIF0_HP_SMU_COMMAND_UPDATE_BASE_IDX 5 |
| #define regBIF0_SMU_HP_END_OF_INTERRUPT 0x42012e |
| #define regBIF0_SMU_HP_END_OF_INTERRUPT_BASE_IDX 5 |
| #define regBIF0_SMU_INT_PIN_SHARING_PORT_INDICATOR 0x42012f |
| #define regBIF0_SMU_INT_PIN_SHARING_PORT_INDICATOR_BASE_IDX 5 |
| #define regBIF0_PCIE_PGMST_CNTL 0x420130 |
| #define regBIF0_PCIE_PGMST_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_PGSLV_CNTL 0x420131 |
| #define regBIF0_PCIE_PGSLV_CNTL_BASE_IDX 5 |
| #define regBIF0_LC_CPM_CONTROL_0 0x420133 |
| #define regBIF0_LC_CPM_CONTROL_0_BASE_IDX 5 |
| #define regBIF0_LC_CPM_CONTROL_1 0x420134 |
| #define regBIF0_LC_CPM_CONTROL_1_BASE_IDX 5 |
| #define regBIF0_PCIE_RXMARGIN_CONTROL_CAPABILITIES 0x420135 |
| #define regBIF0_PCIE_RXMARGIN_CONTROL_CAPABILITIES_BASE_IDX 5 |
| #define regBIF0_PCIE_RXMARGIN_1_SETTINGS 0x420136 |
| #define regBIF0_PCIE_RXMARGIN_1_SETTINGS_BASE_IDX 5 |
| #define regBIF0_PCIE_RXMARGIN_2_SETTINGS 0x420137 |
| #define regBIF0_PCIE_RXMARGIN_2_SETTINGS_BASE_IDX 5 |
| #define regBIF0_PCIE_PRESENCE_DETECT_SELECT 0x420138 |
| #define regBIF0_PCIE_PRESENCE_DETECT_SELECT_BASE_IDX 5 |
| #define regBIF0_PCIE_LC_DEBUG_CNTL 0x420139 |
| #define regBIF0_PCIE_LC_DEBUG_CNTL_BASE_IDX 5 |
| #define regBIF0_SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO 0x42013a |
| #define regBIF0_SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO_BASE_IDX 5 |
| #define regBIF0_PCIE_TX_LAST_TLP0 0x420180 |
| #define regBIF0_PCIE_TX_LAST_TLP0_BASE_IDX 5 |
| #define regBIF0_PCIE_TX_LAST_TLP1 0x420181 |
| #define regBIF0_PCIE_TX_LAST_TLP1_BASE_IDX 5 |
| #define regBIF0_PCIE_TX_LAST_TLP2 0x420182 |
| #define regBIF0_PCIE_TX_LAST_TLP2_BASE_IDX 5 |
| #define regBIF0_PCIE_TX_LAST_TLP3 0x420183 |
| #define regBIF0_PCIE_TX_LAST_TLP3_BASE_IDX 5 |
| #define regBIF0_PCIE_TX_TRACKING_ADDR_LO 0x420184 |
| #define regBIF0_PCIE_TX_TRACKING_ADDR_LO_BASE_IDX 5 |
| #define regBIF0_PCIE_TX_TRACKING_ADDR_HI 0x420185 |
| #define regBIF0_PCIE_TX_TRACKING_ADDR_HI_BASE_IDX 5 |
| #define regBIF0_PCIE_TX_TRACKING_CTRL_STATUS 0x420186 |
| #define regBIF0_PCIE_TX_TRACKING_CTRL_STATUS_BASE_IDX 5 |
| #define regBIF0_PCIE_TX_POWER_CTRL_1 0x420187 |
| #define regBIF0_PCIE_TX_POWER_CTRL_1_BASE_IDX 5 |
| #define regBIF0_PCIE_TX_CTRL_4 0x42018b |
| #define regBIF0_PCIE_TX_CTRL_4_BASE_IDX 5 |
| #define regBIF0_PCIE_TX_STATUS 0x420194 |
| #define regBIF0_PCIE_TX_STATUS_BASE_IDX 5 |
| #define regBIF0_PCIE_TX_F0_ATTR_CNTL 0x42019c |
| #define regBIF0_PCIE_TX_F0_ATTR_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_TX_SWUS_ATTR_CNTL 0x42019d |
| #define regBIF0_PCIE_TX_SWUS_ATTR_CNTL_BASE_IDX 5 |
| #define regBIF0_PCIE_BW_BY_UNITID 0x4201c0 |
| #define regBIF0_PCIE_BW_BY_UNITID_BASE_IDX 5 |
| #define regBIF0_PCIE_MST_CTRL_1 0x4201c4 |
| #define regBIF0_PCIE_MST_CTRL_1_BASE_IDX 5 |
| #define regBIF0_PCIE_MST_CTRL_2 0x4201c5 |
| #define regBIF0_PCIE_MST_CTRL_2_BASE_IDX 5 |
| #define regBIF0_PCIE_MST_CTRL_3 0x4201c6 |
| #define regBIF0_PCIE_MST_CTRL_3_BASE_IDX 5 |
| #define regBIF0_PCIE_MST_CTRL_4 0x4201c7 |
| #define regBIF0_PCIE_MST_CTRL_4_BASE_IDX 5 |
| #define regBIF0_PCIE_MST_ERR_CTRL_1 0x4201d8 |
| #define regBIF0_PCIE_MST_ERR_CTRL_1_BASE_IDX 5 |
| #define regBIF0_PCIE_HIP_REG0 0x4201e0 |
| #define regBIF0_PCIE_HIP_REG0_BASE_IDX 5 |
| #define regBIF0_PCIE_HIP_REG1 0x4201e1 |
| #define regBIF0_PCIE_HIP_REG1_BASE_IDX 5 |
| #define regBIF0_PCIE_HIP_REG2 0x4201e2 |
| #define regBIF0_PCIE_HIP_REG2_BASE_IDX 5 |
| #define regBIF0_PCIE_HIP_REG3 0x4201e3 |
| #define regBIF0_PCIE_HIP_REG3_BASE_IDX 5 |
| #define regBIF0_PCIE_HIP_REG4 0x4201e4 |
| #define regBIF0_PCIE_HIP_REG4_BASE_IDX 5 |
| #define regBIF0_PCIE_HIP_REG5 0x4201e5 |
| #define regBIF0_PCIE_HIP_REG5_BASE_IDX 5 |
| #define regBIF0_PCIE_HIP_REG6 0x4201e6 |
| #define regBIF0_PCIE_HIP_REG6_BASE_IDX 5 |
| #define regBIF0_PCIE_HIP_REG7 0x4201e7 |
| #define regBIF0_PCIE_HIP_REG7_BASE_IDX 5 |
| #define regBIF0_PCIE_HIP_REG8 0x4201e8 |
| #define regBIF0_PCIE_HIP_REG8_BASE_IDX 5 |
| #define regBIF0_PCIE_MST_STATUS 0x4201fc |
| #define regBIF0_PCIE_MST_STATUS_BASE_IDX 5 |
| #define regBIF0_SMU_PCIE_FENCED1_REG 0x420200 |
| #define regBIF0_SMU_PCIE_FENCED1_REG_BASE_IDX 5 |
| #define regBIF0_SMU_PCIE_FENCED2_REG 0x420201 |
| #define regBIF0_SMU_PCIE_FENCED2_REG_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK7 0x420222 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK7_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK7 0x420223 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK7_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK7 0x420224 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK7_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK8 0x420225 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK8_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK8 0x420226 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK8_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK8 0x420227 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK8_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK9 0x420228 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK9_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK9 0x420229 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK9_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK9 0x42022a |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK9_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK10 0x42022b |
| #define regBIF0_PCIE_PERF_CNTL_TXCLK10_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK10 0x42022c |
| #define regBIF0_PCIE_PERF_COUNT0_TXCLK10_BASE_IDX 5 |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK10 0x42022d |
| #define regBIF0_PCIE_PERF_COUNT1_TXCLK10_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifplr0_cfgdecp |
| // base address: 0x11200000 |
| #define regBIFPLR0_1_VENDOR_ID 0x440000 |
| #define regBIFPLR0_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR0_1_DEVICE_ID 0x440000 |
| #define regBIFPLR0_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR0_1_COMMAND 0x440001 |
| #define regBIFPLR0_1_COMMAND_BASE_IDX 5 |
| #define regBIFPLR0_1_STATUS 0x440001 |
| #define regBIFPLR0_1_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_REVISION_ID 0x440002 |
| #define regBIFPLR0_1_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR0_1_PROG_INTERFACE 0x440002 |
| #define regBIFPLR0_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR0_1_SUB_CLASS 0x440002 |
| #define regBIFPLR0_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR0_1_BASE_CLASS 0x440002 |
| #define regBIFPLR0_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR0_1_CACHE_LINE 0x440003 |
| #define regBIFPLR0_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR0_1_LATENCY 0x440003 |
| #define regBIFPLR0_1_LATENCY_BASE_IDX 5 |
| #define regBIFPLR0_1_HEADER 0x440003 |
| #define regBIFPLR0_1_HEADER_BASE_IDX 5 |
| #define regBIFPLR0_1_BIST 0x440003 |
| #define regBIFPLR0_1_BIST_BASE_IDX 5 |
| #define regBIFPLR0_1_SUB_BUS_NUMBER_LATENCY 0x440006 |
| #define regBIFPLR0_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR0_1_IO_BASE_LIMIT 0x440007 |
| #define regBIFPLR0_1_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR0_1_SECONDARY_STATUS 0x440007 |
| #define regBIFPLR0_1_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_MEM_BASE_LIMIT 0x440008 |
| #define regBIFPLR0_1_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR0_1_PREF_BASE_LIMIT 0x440009 |
| #define regBIFPLR0_1_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR0_1_PREF_BASE_UPPER 0x44000a |
| #define regBIFPLR0_1_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR0_1_PREF_LIMIT_UPPER 0x44000b |
| #define regBIFPLR0_1_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR0_1_IO_BASE_LIMIT_HI 0x44000c |
| #define regBIFPLR0_1_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR0_1_CAP_PTR 0x44000d |
| #define regBIFPLR0_1_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR0_1_ROM_BASE_ADDR 0x44000e |
| #define regBIFPLR0_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIFPLR0_1_INTERRUPT_LINE 0x44000f |
| #define regBIFPLR0_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR0_1_INTERRUPT_PIN 0x44000f |
| #define regBIFPLR0_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR0_1_EXT_BRIDGE_CNTL 0x440010 |
| #define regBIFPLR0_1_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_VENDOR_CAP_LIST 0x440012 |
| #define regBIFPLR0_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_ADAPTER_ID_W 0x440013 |
| #define regBIFPLR0_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIFPLR0_1_PMI_CAP_LIST 0x440014 |
| #define regBIFPLR0_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PMI_CAP 0x440014 |
| #define regBIFPLR0_1_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_PMI_STATUS_CNTL 0x440015 |
| #define regBIFPLR0_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CAP_LIST 0x440016 |
| #define regBIFPLR0_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CAP 0x440016 |
| #define regBIFPLR0_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_DEVICE_CAP 0x440017 |
| #define regBIFPLR0_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_DEVICE_CNTL 0x440018 |
| #define regBIFPLR0_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_DEVICE_STATUS 0x440018 |
| #define regBIFPLR0_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LINK_CAP 0x440019 |
| #define regBIFPLR0_1_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_LINK_CNTL 0x44001a |
| #define regBIFPLR0_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LINK_STATUS 0x44001a |
| #define regBIFPLR0_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_SLOT_CAP 0x44001b |
| #define regBIFPLR0_1_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_SLOT_CNTL 0x44001c |
| #define regBIFPLR0_1_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_SLOT_STATUS 0x44001c |
| #define regBIFPLR0_1_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_ROOT_CNTL 0x44001d |
| #define regBIFPLR0_1_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_ROOT_CAP 0x44001d |
| #define regBIFPLR0_1_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_ROOT_STATUS 0x44001e |
| #define regBIFPLR0_1_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_DEVICE_CAP2 0x44001f |
| #define regBIFPLR0_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR0_1_DEVICE_CNTL2 0x440020 |
| #define regBIFPLR0_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_1_DEVICE_STATUS2 0x440020 |
| #define regBIFPLR0_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR0_1_LINK_CAP2 0x440021 |
| #define regBIFPLR0_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR0_1_LINK_CNTL2 0x440022 |
| #define regBIFPLR0_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_1_LINK_STATUS2 0x440022 |
| #define regBIFPLR0_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR0_1_SLOT_CAP2 0x440023 |
| #define regBIFPLR0_1_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR0_1_SLOT_CNTL2 0x440024 |
| #define regBIFPLR0_1_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_1_SLOT_STATUS2 0x440024 |
| #define regBIFPLR0_1_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR0_1_MSI_CAP_LIST 0x440028 |
| #define regBIFPLR0_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_MSI_MSG_CNTL 0x440028 |
| #define regBIFPLR0_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_MSI_MSG_ADDR_LO 0x440029 |
| #define regBIFPLR0_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR0_1_MSI_MSG_ADDR_HI 0x44002a |
| #define regBIFPLR0_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR0_1_MSI_MSG_DATA 0x44002a |
| #define regBIFPLR0_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR0_1_MSI_MSG_DATA_64 0x44002b |
| #define regBIFPLR0_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR0_1_SSID_CAP_LIST 0x440030 |
| #define regBIFPLR0_1_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_SSID_CAP 0x440031 |
| #define regBIFPLR0_1_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_MSI_MAP_CAP_LIST 0x440032 |
| #define regBIFPLR0_1_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_MSI_MAP_CAP 0x440032 |
| #define regBIFPLR0_1_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x440040 |
| #define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR 0x440041 |
| #define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC1 0x440042 |
| #define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC2 0x440043 |
| #define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_VC_ENH_CAP_LIST 0x440044 |
| #define regBIFPLR0_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_PORT_VC_CAP_REG1 0x440045 |
| #define regBIFPLR0_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_PORT_VC_CAP_REG2 0x440046 |
| #define regBIFPLR0_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_PORT_VC_CNTL 0x440047 |
| #define regBIFPLR0_1_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_PORT_VC_STATUS 0x440047 |
| #define regBIFPLR0_1_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_VC0_RESOURCE_CAP 0x440048 |
| #define regBIFPLR0_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_VC0_RESOURCE_CNTL 0x440049 |
| #define regBIFPLR0_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_VC0_RESOURCE_STATUS 0x44004a |
| #define regBIFPLR0_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_VC1_RESOURCE_CAP 0x44004b |
| #define regBIFPLR0_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_VC1_RESOURCE_CNTL 0x44004c |
| #define regBIFPLR0_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_VC1_RESOURCE_STATUS 0x44004d |
| #define regBIFPLR0_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x440050 |
| #define regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1 0x440051 |
| #define regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2 0x440052 |
| #define regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x440054 |
| #define regBIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_UNCORR_ERR_STATUS 0x440055 |
| #define regBIFPLR0_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_UNCORR_ERR_MASK 0x440056 |
| #define regBIFPLR0_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY 0x440057 |
| #define regBIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CORR_ERR_STATUS 0x440058 |
| #define regBIFPLR0_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CORR_ERR_MASK 0x440059 |
| #define regBIFPLR0_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL 0x44005a |
| #define regBIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_HDR_LOG0 0x44005b |
| #define regBIFPLR0_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_HDR_LOG1 0x44005c |
| #define regBIFPLR0_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_HDR_LOG2 0x44005d |
| #define regBIFPLR0_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_HDR_LOG3 0x44005e |
| #define regBIFPLR0_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ROOT_ERR_CMD 0x44005f |
| #define regBIFPLR0_1_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ROOT_ERR_STATUS 0x440060 |
| #define regBIFPLR0_1_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ERR_SRC_ID 0x440061 |
| #define regBIFPLR0_1_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG0 0x440062 |
| #define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG1 0x440063 |
| #define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG2 0x440064 |
| #define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG3 0x440065 |
| #define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST 0x44009c |
| #define regBIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LINK_CNTL3 0x44009d |
| #define regBIFPLR0_1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_ERROR_STATUS 0x44009e |
| #define regBIFPLR0_1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x44009f |
| #define regBIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x44009f |
| #define regBIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x4400a0 |
| #define regBIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x4400a0 |
| #define regBIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x4400a1 |
| #define regBIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x4400a1 |
| #define regBIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x4400a2 |
| #define regBIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x4400a2 |
| #define regBIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x4400a3 |
| #define regBIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x4400a3 |
| #define regBIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x4400a4 |
| #define regBIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x4400a4 |
| #define regBIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x4400a5 |
| #define regBIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x4400a5 |
| #define regBIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x4400a6 |
| #define regBIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x4400a6 |
| #define regBIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ACS_ENH_CAP_LIST 0x4400a8 |
| #define regBIFPLR0_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ACS_CAP 0x4400a9 |
| #define regBIFPLR0_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ACS_CNTL 0x4400a9 |
| #define regBIFPLR0_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_ENH_CAP_LIST 0x4400bc |
| #define regBIFPLR0_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_CAP 0x4400bd |
| #define regBIFPLR0_1_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_CNTL 0x4400bd |
| #define regBIFPLR0_1_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_ADDR0 0x4400be |
| #define regBIFPLR0_1_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_ADDR1 0x4400bf |
| #define regBIFPLR0_1_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_RCV0 0x4400c0 |
| #define regBIFPLR0_1_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_RCV1 0x4400c1 |
| #define regBIFPLR0_1_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_BLOCK_ALL0 0x4400c2 |
| #define regBIFPLR0_1_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_BLOCK_ALL1 0x4400c3 |
| #define regBIFPLR0_1_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x4400c4 |
| #define regBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x4400c5 |
| #define regBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_OVERLAY_BAR0 0x4400c6 |
| #define regBIFPLR0_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MC_OVERLAY_BAR1 0x4400c7 |
| #define regBIFPLR0_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST 0x4400dc |
| #define regBIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_L1_PM_SUB_CAP 0x4400dd |
| #define regBIFPLR0_1_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_L1_PM_SUB_CNTL 0x4400de |
| #define regBIFPLR0_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_L1_PM_SUB_CNTL2 0x4400df |
| #define regBIFPLR0_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_DPC_ENH_CAP_LIST 0x4400e0 |
| #define regBIFPLR0_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_DPC_CAP_LIST 0x4400e1 |
| #define regBIFPLR0_1_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_DPC_CNTL 0x4400e1 |
| #define regBIFPLR0_1_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_DPC_STATUS 0x4400e2 |
| #define regBIFPLR0_1_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID 0x4400e2 |
| #define regBIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_STATUS 0x4400e3 |
| #define regBIFPLR0_1_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_MASK 0x4400e4 |
| #define regBIFPLR0_1_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_SEVERITY 0x4400e5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_SYSERROR 0x4400e6 |
| #define regBIFPLR0_1_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_EXCEPTION 0x4400e7 |
| #define regBIFPLR0_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG0 0x4400e8 |
| #define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG1 0x4400e9 |
| #define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG2 0x4400ea |
| #define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG3 0x4400eb |
| #define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0 0x4400ed |
| #define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1 0x4400ee |
| #define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2 0x4400ef |
| #define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3 0x4400f0 |
| #define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_LIST 0x4400f1 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ESM_HEADER_1 0x4400f2 |
| #define regBIFPLR0_1_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ESM_HEADER_2 0x4400f3 |
| #define regBIFPLR0_1_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ESM_STATUS 0x4400f3 |
| #define regBIFPLR0_1_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ESM_CTRL 0x4400f4 |
| #define regBIFPLR0_1_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_1 0x4400f5 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_2 0x4400f6 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_3 0x4400f7 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_4 0x4400f8 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_5 0x4400f9 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_6 0x4400fa |
| #define regBIFPLR0_1_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_ESM_CAP_7 0x4400fb |
| #define regBIFPLR0_1_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_DLF_ENH_CAP_LIST 0x440100 |
| #define regBIFPLR0_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_DATA_LINK_FEATURE_CAP 0x440101 |
| #define regBIFPLR0_1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_DATA_LINK_FEATURE_STATUS 0x440102 |
| #define regBIFPLR0_1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x440104 |
| #define regBIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_LINK_CAP_16GT 0x440105 |
| #define regBIFPLR0_1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LINK_CNTL_16GT 0x440106 |
| #define regBIFPLR0_1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LINK_STATUS_16GT 0x440107 |
| #define regBIFPLR0_1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x440108 |
| #define regBIFPLR0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x440109 |
| #define regBIFPLR0_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x44010a |
| #define regBIFPLR0_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT 0x44010c |
| #define regBIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT 0x44010c |
| #define regBIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT 0x44010c |
| #define regBIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT 0x44010c |
| #define regBIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT 0x44010d |
| #define regBIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT 0x44010d |
| #define regBIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT 0x44010d |
| #define regBIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT 0x44010d |
| #define regBIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT 0x44010e |
| #define regBIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT 0x44010e |
| #define regBIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT 0x44010e |
| #define regBIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT 0x44010e |
| #define regBIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT 0x44010f |
| #define regBIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT 0x44010f |
| #define regBIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT 0x44010f |
| #define regBIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT 0x44010f |
| #define regBIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST 0x440110 |
| #define regBIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_MARGINING_PORT_CAP 0x440111 |
| #define regBIFPLR0_1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_MARGINING_PORT_STATUS 0x440111 |
| #define regBIFPLR0_1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_0_MARGINING_LANE_CNTL 0x440112 |
| #define regBIFPLR0_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_0_MARGINING_LANE_STATUS 0x440112 |
| #define regBIFPLR0_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_1_MARGINING_LANE_CNTL 0x440113 |
| #define regBIFPLR0_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_1_MARGINING_LANE_STATUS 0x440113 |
| #define regBIFPLR0_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_2_MARGINING_LANE_CNTL 0x440114 |
| #define regBIFPLR0_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_2_MARGINING_LANE_STATUS 0x440114 |
| #define regBIFPLR0_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_3_MARGINING_LANE_CNTL 0x440115 |
| #define regBIFPLR0_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_3_MARGINING_LANE_STATUS 0x440115 |
| #define regBIFPLR0_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_4_MARGINING_LANE_CNTL 0x440116 |
| #define regBIFPLR0_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_4_MARGINING_LANE_STATUS 0x440116 |
| #define regBIFPLR0_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_5_MARGINING_LANE_CNTL 0x440117 |
| #define regBIFPLR0_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_5_MARGINING_LANE_STATUS 0x440117 |
| #define regBIFPLR0_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_6_MARGINING_LANE_CNTL 0x440118 |
| #define regBIFPLR0_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_6_MARGINING_LANE_STATUS 0x440118 |
| #define regBIFPLR0_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_7_MARGINING_LANE_CNTL 0x440119 |
| #define regBIFPLR0_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_7_MARGINING_LANE_STATUS 0x440119 |
| #define regBIFPLR0_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_8_MARGINING_LANE_CNTL 0x44011a |
| #define regBIFPLR0_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_8_MARGINING_LANE_STATUS 0x44011a |
| #define regBIFPLR0_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_9_MARGINING_LANE_CNTL 0x44011b |
| #define regBIFPLR0_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_9_MARGINING_LANE_STATUS 0x44011b |
| #define regBIFPLR0_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_10_MARGINING_LANE_CNTL 0x44011c |
| #define regBIFPLR0_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_10_MARGINING_LANE_STATUS 0x44011c |
| #define regBIFPLR0_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_11_MARGINING_LANE_CNTL 0x44011d |
| #define regBIFPLR0_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_11_MARGINING_LANE_STATUS 0x44011d |
| #define regBIFPLR0_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_12_MARGINING_LANE_CNTL 0x44011e |
| #define regBIFPLR0_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_12_MARGINING_LANE_STATUS 0x44011e |
| #define regBIFPLR0_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_13_MARGINING_LANE_CNTL 0x44011f |
| #define regBIFPLR0_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_13_MARGINING_LANE_STATUS 0x44011f |
| #define regBIFPLR0_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_14_MARGINING_LANE_CNTL 0x440120 |
| #define regBIFPLR0_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_14_MARGINING_LANE_STATUS 0x440120 |
| #define regBIFPLR0_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_15_MARGINING_LANE_CNTL 0x440121 |
| #define regBIFPLR0_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LANE_15_MARGINING_LANE_STATUS 0x440121 |
| #define regBIFPLR0_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CCIX_CAP_LIST 0x440122 |
| #define regBIFPLR0_1_PCIE_CCIX_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CCIX_HEADER_1 0x440123 |
| #define regBIFPLR0_1_PCIE_CCIX_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CCIX_HEADER_2 0x440124 |
| #define regBIFPLR0_1_PCIE_CCIX_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CCIX_CAP 0x440124 |
| #define regBIFPLR0_1_PCIE_CCIX_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP 0x440125 |
| #define regBIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CCIX_ESM_OPTL_CAP 0x440126 |
| #define regBIFPLR0_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CCIX_ESM_STATUS 0x440127 |
| #define regBIFPLR0_1_PCIE_CCIX_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CCIX_ESM_CNTL 0x440128 |
| #define regBIFPLR0_1_PCIE_CCIX_ESM_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x440129 |
| #define regBIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x440129 |
| #define regBIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x440129 |
| #define regBIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x440129 |
| #define regBIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x44012a |
| #define regBIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x44012a |
| #define regBIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x44012a |
| #define regBIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x44012a |
| #define regBIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x44012b |
| #define regBIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x44012b |
| #define regBIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x44012b |
| #define regBIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x44012b |
| #define regBIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x44012c |
| #define regBIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x44012c |
| #define regBIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x44012c |
| #define regBIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x44012c |
| #define regBIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x44012d |
| #define regBIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x44012d |
| #define regBIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x44012d |
| #define regBIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x44012d |
| #define regBIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x44012e |
| #define regBIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x44012e |
| #define regBIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x44012e |
| #define regBIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x44012e |
| #define regBIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x44012f |
| #define regBIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x44012f |
| #define regBIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x44012f |
| #define regBIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x44012f |
| #define regBIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x440130 |
| #define regBIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x440130 |
| #define regBIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x440130 |
| #define regBIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x440130 |
| #define regBIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CCIX_TRANS_CAP 0x440131 |
| #define regBIFPLR0_1_PCIE_CCIX_TRANS_CAP_BASE_IDX 5 |
| #define regBIFPLR0_1_PCIE_CCIX_TRANS_CNTL 0x440132 |
| #define regBIFPLR0_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_1_LINK_CAP_32GT 0x440141 |
| #define regBIFPLR0_1_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LINK_CNTL_32GT 0x440142 |
| #define regBIFPLR0_1_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR0_1_LINK_STATUS_32GT 0x440143 |
| #define regBIFPLR0_1_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifplr1_cfgdecp |
| // base address: 0x11201000 |
| #define regBIFPLR1_1_VENDOR_ID 0x440400 |
| #define regBIFPLR1_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR1_1_DEVICE_ID 0x440400 |
| #define regBIFPLR1_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR1_1_COMMAND 0x440401 |
| #define regBIFPLR1_1_COMMAND_BASE_IDX 5 |
| #define regBIFPLR1_1_STATUS 0x440401 |
| #define regBIFPLR1_1_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_REVISION_ID 0x440402 |
| #define regBIFPLR1_1_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR1_1_PROG_INTERFACE 0x440402 |
| #define regBIFPLR1_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR1_1_SUB_CLASS 0x440402 |
| #define regBIFPLR1_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR1_1_BASE_CLASS 0x440402 |
| #define regBIFPLR1_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR1_1_CACHE_LINE 0x440403 |
| #define regBIFPLR1_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR1_1_LATENCY 0x440403 |
| #define regBIFPLR1_1_LATENCY_BASE_IDX 5 |
| #define regBIFPLR1_1_HEADER 0x440403 |
| #define regBIFPLR1_1_HEADER_BASE_IDX 5 |
| #define regBIFPLR1_1_BIST 0x440403 |
| #define regBIFPLR1_1_BIST_BASE_IDX 5 |
| #define regBIFPLR1_1_SUB_BUS_NUMBER_LATENCY 0x440406 |
| #define regBIFPLR1_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR1_1_IO_BASE_LIMIT 0x440407 |
| #define regBIFPLR1_1_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR1_1_SECONDARY_STATUS 0x440407 |
| #define regBIFPLR1_1_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_MEM_BASE_LIMIT 0x440408 |
| #define regBIFPLR1_1_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR1_1_PREF_BASE_LIMIT 0x440409 |
| #define regBIFPLR1_1_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR1_1_PREF_BASE_UPPER 0x44040a |
| #define regBIFPLR1_1_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR1_1_PREF_LIMIT_UPPER 0x44040b |
| #define regBIFPLR1_1_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR1_1_IO_BASE_LIMIT_HI 0x44040c |
| #define regBIFPLR1_1_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR1_1_CAP_PTR 0x44040d |
| #define regBIFPLR1_1_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR1_1_ROM_BASE_ADDR 0x44040e |
| #define regBIFPLR1_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIFPLR1_1_INTERRUPT_LINE 0x44040f |
| #define regBIFPLR1_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR1_1_INTERRUPT_PIN 0x44040f |
| #define regBIFPLR1_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR1_1_EXT_BRIDGE_CNTL 0x440410 |
| #define regBIFPLR1_1_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_VENDOR_CAP_LIST 0x440412 |
| #define regBIFPLR1_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_ADAPTER_ID_W 0x440413 |
| #define regBIFPLR1_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIFPLR1_1_PMI_CAP_LIST 0x440414 |
| #define regBIFPLR1_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PMI_CAP 0x440414 |
| #define regBIFPLR1_1_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_PMI_STATUS_CNTL 0x440415 |
| #define regBIFPLR1_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CAP_LIST 0x440416 |
| #define regBIFPLR1_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CAP 0x440416 |
| #define regBIFPLR1_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_DEVICE_CAP 0x440417 |
| #define regBIFPLR1_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_DEVICE_CNTL 0x440418 |
| #define regBIFPLR1_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_DEVICE_STATUS 0x440418 |
| #define regBIFPLR1_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LINK_CAP 0x440419 |
| #define regBIFPLR1_1_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_LINK_CNTL 0x44041a |
| #define regBIFPLR1_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LINK_STATUS 0x44041a |
| #define regBIFPLR1_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_SLOT_CAP 0x44041b |
| #define regBIFPLR1_1_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_SLOT_CNTL 0x44041c |
| #define regBIFPLR1_1_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_SLOT_STATUS 0x44041c |
| #define regBIFPLR1_1_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_ROOT_CNTL 0x44041d |
| #define regBIFPLR1_1_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_ROOT_CAP 0x44041d |
| #define regBIFPLR1_1_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_ROOT_STATUS 0x44041e |
| #define regBIFPLR1_1_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_DEVICE_CAP2 0x44041f |
| #define regBIFPLR1_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR1_1_DEVICE_CNTL2 0x440420 |
| #define regBIFPLR1_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_1_DEVICE_STATUS2 0x440420 |
| #define regBIFPLR1_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR1_1_LINK_CAP2 0x440421 |
| #define regBIFPLR1_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR1_1_LINK_CNTL2 0x440422 |
| #define regBIFPLR1_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_1_LINK_STATUS2 0x440422 |
| #define regBIFPLR1_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR1_1_SLOT_CAP2 0x440423 |
| #define regBIFPLR1_1_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR1_1_SLOT_CNTL2 0x440424 |
| #define regBIFPLR1_1_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_1_SLOT_STATUS2 0x440424 |
| #define regBIFPLR1_1_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR1_1_MSI_CAP_LIST 0x440428 |
| #define regBIFPLR1_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_MSI_MSG_CNTL 0x440428 |
| #define regBIFPLR1_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_MSI_MSG_ADDR_LO 0x440429 |
| #define regBIFPLR1_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR1_1_MSI_MSG_ADDR_HI 0x44042a |
| #define regBIFPLR1_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR1_1_MSI_MSG_DATA 0x44042a |
| #define regBIFPLR1_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR1_1_MSI_MSG_DATA_64 0x44042b |
| #define regBIFPLR1_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR1_1_SSID_CAP_LIST 0x440430 |
| #define regBIFPLR1_1_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_SSID_CAP 0x440431 |
| #define regBIFPLR1_1_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_MSI_MAP_CAP_LIST 0x440432 |
| #define regBIFPLR1_1_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_MSI_MAP_CAP 0x440432 |
| #define regBIFPLR1_1_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x440440 |
| #define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR 0x440441 |
| #define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC1 0x440442 |
| #define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC2 0x440443 |
| #define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_VC_ENH_CAP_LIST 0x440444 |
| #define regBIFPLR1_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_PORT_VC_CAP_REG1 0x440445 |
| #define regBIFPLR1_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_PORT_VC_CAP_REG2 0x440446 |
| #define regBIFPLR1_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_PORT_VC_CNTL 0x440447 |
| #define regBIFPLR1_1_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_PORT_VC_STATUS 0x440447 |
| #define regBIFPLR1_1_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_VC0_RESOURCE_CAP 0x440448 |
| #define regBIFPLR1_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_VC0_RESOURCE_CNTL 0x440449 |
| #define regBIFPLR1_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_VC0_RESOURCE_STATUS 0x44044a |
| #define regBIFPLR1_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_VC1_RESOURCE_CAP 0x44044b |
| #define regBIFPLR1_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_VC1_RESOURCE_CNTL 0x44044c |
| #define regBIFPLR1_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_VC1_RESOURCE_STATUS 0x44044d |
| #define regBIFPLR1_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x440450 |
| #define regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1 0x440451 |
| #define regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2 0x440452 |
| #define regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x440454 |
| #define regBIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_UNCORR_ERR_STATUS 0x440455 |
| #define regBIFPLR1_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_UNCORR_ERR_MASK 0x440456 |
| #define regBIFPLR1_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY 0x440457 |
| #define regBIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CORR_ERR_STATUS 0x440458 |
| #define regBIFPLR1_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CORR_ERR_MASK 0x440459 |
| #define regBIFPLR1_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL 0x44045a |
| #define regBIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_HDR_LOG0 0x44045b |
| #define regBIFPLR1_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_HDR_LOG1 0x44045c |
| #define regBIFPLR1_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_HDR_LOG2 0x44045d |
| #define regBIFPLR1_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_HDR_LOG3 0x44045e |
| #define regBIFPLR1_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ROOT_ERR_CMD 0x44045f |
| #define regBIFPLR1_1_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ROOT_ERR_STATUS 0x440460 |
| #define regBIFPLR1_1_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ERR_SRC_ID 0x440461 |
| #define regBIFPLR1_1_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG0 0x440462 |
| #define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG1 0x440463 |
| #define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG2 0x440464 |
| #define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG3 0x440465 |
| #define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST 0x44049c |
| #define regBIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LINK_CNTL3 0x44049d |
| #define regBIFPLR1_1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_ERROR_STATUS 0x44049e |
| #define regBIFPLR1_1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x44049f |
| #define regBIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x44049f |
| #define regBIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x4404a0 |
| #define regBIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x4404a0 |
| #define regBIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x4404a1 |
| #define regBIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x4404a1 |
| #define regBIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x4404a2 |
| #define regBIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x4404a2 |
| #define regBIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x4404a3 |
| #define regBIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x4404a3 |
| #define regBIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x4404a4 |
| #define regBIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x4404a4 |
| #define regBIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x4404a5 |
| #define regBIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x4404a5 |
| #define regBIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x4404a6 |
| #define regBIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x4404a6 |
| #define regBIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ACS_ENH_CAP_LIST 0x4404a8 |
| #define regBIFPLR1_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ACS_CAP 0x4404a9 |
| #define regBIFPLR1_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ACS_CNTL 0x4404a9 |
| #define regBIFPLR1_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_ENH_CAP_LIST 0x4404bc |
| #define regBIFPLR1_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_CAP 0x4404bd |
| #define regBIFPLR1_1_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_CNTL 0x4404bd |
| #define regBIFPLR1_1_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_ADDR0 0x4404be |
| #define regBIFPLR1_1_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_ADDR1 0x4404bf |
| #define regBIFPLR1_1_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_RCV0 0x4404c0 |
| #define regBIFPLR1_1_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_RCV1 0x4404c1 |
| #define regBIFPLR1_1_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_BLOCK_ALL0 0x4404c2 |
| #define regBIFPLR1_1_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_BLOCK_ALL1 0x4404c3 |
| #define regBIFPLR1_1_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x4404c4 |
| #define regBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x4404c5 |
| #define regBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_OVERLAY_BAR0 0x4404c6 |
| #define regBIFPLR1_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MC_OVERLAY_BAR1 0x4404c7 |
| #define regBIFPLR1_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST 0x4404dc |
| #define regBIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_L1_PM_SUB_CAP 0x4404dd |
| #define regBIFPLR1_1_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_L1_PM_SUB_CNTL 0x4404de |
| #define regBIFPLR1_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_L1_PM_SUB_CNTL2 0x4404df |
| #define regBIFPLR1_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_DPC_ENH_CAP_LIST 0x4404e0 |
| #define regBIFPLR1_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_DPC_CAP_LIST 0x4404e1 |
| #define regBIFPLR1_1_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_DPC_CNTL 0x4404e1 |
| #define regBIFPLR1_1_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_DPC_STATUS 0x4404e2 |
| #define regBIFPLR1_1_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID 0x4404e2 |
| #define regBIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_STATUS 0x4404e3 |
| #define regBIFPLR1_1_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_MASK 0x4404e4 |
| #define regBIFPLR1_1_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_SEVERITY 0x4404e5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_SYSERROR 0x4404e6 |
| #define regBIFPLR1_1_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_EXCEPTION 0x4404e7 |
| #define regBIFPLR1_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG0 0x4404e8 |
| #define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG1 0x4404e9 |
| #define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG2 0x4404ea |
| #define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG3 0x4404eb |
| #define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0 0x4404ed |
| #define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1 0x4404ee |
| #define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2 0x4404ef |
| #define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3 0x4404f0 |
| #define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_LIST 0x4404f1 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ESM_HEADER_1 0x4404f2 |
| #define regBIFPLR1_1_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ESM_HEADER_2 0x4404f3 |
| #define regBIFPLR1_1_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ESM_STATUS 0x4404f3 |
| #define regBIFPLR1_1_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ESM_CTRL 0x4404f4 |
| #define regBIFPLR1_1_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_1 0x4404f5 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_2 0x4404f6 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_3 0x4404f7 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_4 0x4404f8 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_5 0x4404f9 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_6 0x4404fa |
| #define regBIFPLR1_1_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_ESM_CAP_7 0x4404fb |
| #define regBIFPLR1_1_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_DLF_ENH_CAP_LIST 0x440500 |
| #define regBIFPLR1_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_DATA_LINK_FEATURE_CAP 0x440501 |
| #define regBIFPLR1_1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_DATA_LINK_FEATURE_STATUS 0x440502 |
| #define regBIFPLR1_1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x440504 |
| #define regBIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_LINK_CAP_16GT 0x440505 |
| #define regBIFPLR1_1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LINK_CNTL_16GT 0x440506 |
| #define regBIFPLR1_1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LINK_STATUS_16GT 0x440507 |
| #define regBIFPLR1_1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x440508 |
| #define regBIFPLR1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x440509 |
| #define regBIFPLR1_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x44050a |
| #define regBIFPLR1_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT 0x44050c |
| #define regBIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT 0x44050c |
| #define regBIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT 0x44050c |
| #define regBIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT 0x44050c |
| #define regBIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT 0x44050d |
| #define regBIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT 0x44050d |
| #define regBIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT 0x44050d |
| #define regBIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT 0x44050d |
| #define regBIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT 0x44050e |
| #define regBIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT 0x44050e |
| #define regBIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT 0x44050e |
| #define regBIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT 0x44050e |
| #define regBIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT 0x44050f |
| #define regBIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT 0x44050f |
| #define regBIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT 0x44050f |
| #define regBIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT 0x44050f |
| #define regBIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST 0x440510 |
| #define regBIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_MARGINING_PORT_CAP 0x440511 |
| #define regBIFPLR1_1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_MARGINING_PORT_STATUS 0x440511 |
| #define regBIFPLR1_1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_0_MARGINING_LANE_CNTL 0x440512 |
| #define regBIFPLR1_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_0_MARGINING_LANE_STATUS 0x440512 |
| #define regBIFPLR1_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_1_MARGINING_LANE_CNTL 0x440513 |
| #define regBIFPLR1_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_1_MARGINING_LANE_STATUS 0x440513 |
| #define regBIFPLR1_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_2_MARGINING_LANE_CNTL 0x440514 |
| #define regBIFPLR1_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_2_MARGINING_LANE_STATUS 0x440514 |
| #define regBIFPLR1_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_3_MARGINING_LANE_CNTL 0x440515 |
| #define regBIFPLR1_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_3_MARGINING_LANE_STATUS 0x440515 |
| #define regBIFPLR1_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_4_MARGINING_LANE_CNTL 0x440516 |
| #define regBIFPLR1_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_4_MARGINING_LANE_STATUS 0x440516 |
| #define regBIFPLR1_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_5_MARGINING_LANE_CNTL 0x440517 |
| #define regBIFPLR1_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_5_MARGINING_LANE_STATUS 0x440517 |
| #define regBIFPLR1_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_6_MARGINING_LANE_CNTL 0x440518 |
| #define regBIFPLR1_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_6_MARGINING_LANE_STATUS 0x440518 |
| #define regBIFPLR1_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_7_MARGINING_LANE_CNTL 0x440519 |
| #define regBIFPLR1_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_7_MARGINING_LANE_STATUS 0x440519 |
| #define regBIFPLR1_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_8_MARGINING_LANE_CNTL 0x44051a |
| #define regBIFPLR1_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_8_MARGINING_LANE_STATUS 0x44051a |
| #define regBIFPLR1_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_9_MARGINING_LANE_CNTL 0x44051b |
| #define regBIFPLR1_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_9_MARGINING_LANE_STATUS 0x44051b |
| #define regBIFPLR1_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_10_MARGINING_LANE_CNTL 0x44051c |
| #define regBIFPLR1_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_10_MARGINING_LANE_STATUS 0x44051c |
| #define regBIFPLR1_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_11_MARGINING_LANE_CNTL 0x44051d |
| #define regBIFPLR1_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_11_MARGINING_LANE_STATUS 0x44051d |
| #define regBIFPLR1_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_12_MARGINING_LANE_CNTL 0x44051e |
| #define regBIFPLR1_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_12_MARGINING_LANE_STATUS 0x44051e |
| #define regBIFPLR1_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_13_MARGINING_LANE_CNTL 0x44051f |
| #define regBIFPLR1_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_13_MARGINING_LANE_STATUS 0x44051f |
| #define regBIFPLR1_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_14_MARGINING_LANE_CNTL 0x440520 |
| #define regBIFPLR1_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_14_MARGINING_LANE_STATUS 0x440520 |
| #define regBIFPLR1_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_15_MARGINING_LANE_CNTL 0x440521 |
| #define regBIFPLR1_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LANE_15_MARGINING_LANE_STATUS 0x440521 |
| #define regBIFPLR1_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CCIX_CAP_LIST 0x440522 |
| #define regBIFPLR1_1_PCIE_CCIX_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CCIX_HEADER_1 0x440523 |
| #define regBIFPLR1_1_PCIE_CCIX_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CCIX_HEADER_2 0x440524 |
| #define regBIFPLR1_1_PCIE_CCIX_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CCIX_CAP 0x440524 |
| #define regBIFPLR1_1_PCIE_CCIX_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP 0x440525 |
| #define regBIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CCIX_ESM_OPTL_CAP 0x440526 |
| #define regBIFPLR1_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CCIX_ESM_STATUS 0x440527 |
| #define regBIFPLR1_1_PCIE_CCIX_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CCIX_ESM_CNTL 0x440528 |
| #define regBIFPLR1_1_PCIE_CCIX_ESM_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x440529 |
| #define regBIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x440529 |
| #define regBIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x440529 |
| #define regBIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x440529 |
| #define regBIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x44052a |
| #define regBIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x44052a |
| #define regBIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x44052a |
| #define regBIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x44052a |
| #define regBIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x44052b |
| #define regBIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x44052b |
| #define regBIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x44052b |
| #define regBIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x44052b |
| #define regBIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x44052c |
| #define regBIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x44052c |
| #define regBIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x44052c |
| #define regBIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x44052c |
| #define regBIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x44052d |
| #define regBIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x44052d |
| #define regBIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x44052d |
| #define regBIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x44052d |
| #define regBIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x44052e |
| #define regBIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x44052e |
| #define regBIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x44052e |
| #define regBIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x44052e |
| #define regBIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x44052f |
| #define regBIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x44052f |
| #define regBIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x44052f |
| #define regBIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x44052f |
| #define regBIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x440530 |
| #define regBIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x440530 |
| #define regBIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x440530 |
| #define regBIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x440530 |
| #define regBIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CCIX_TRANS_CAP 0x440531 |
| #define regBIFPLR1_1_PCIE_CCIX_TRANS_CAP_BASE_IDX 5 |
| #define regBIFPLR1_1_PCIE_CCIX_TRANS_CNTL 0x440532 |
| #define regBIFPLR1_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_1_LINK_CAP_32GT 0x440541 |
| #define regBIFPLR1_1_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LINK_CNTL_32GT 0x440542 |
| #define regBIFPLR1_1_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR1_1_LINK_STATUS_32GT 0x440543 |
| #define regBIFPLR1_1_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifplr2_cfgdecp |
| // base address: 0x11202000 |
| #define regBIFPLR2_1_VENDOR_ID 0x440800 |
| #define regBIFPLR2_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR2_1_DEVICE_ID 0x440800 |
| #define regBIFPLR2_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR2_1_COMMAND 0x440801 |
| #define regBIFPLR2_1_COMMAND_BASE_IDX 5 |
| #define regBIFPLR2_1_STATUS 0x440801 |
| #define regBIFPLR2_1_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_REVISION_ID 0x440802 |
| #define regBIFPLR2_1_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR2_1_PROG_INTERFACE 0x440802 |
| #define regBIFPLR2_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR2_1_SUB_CLASS 0x440802 |
| #define regBIFPLR2_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR2_1_BASE_CLASS 0x440802 |
| #define regBIFPLR2_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR2_1_CACHE_LINE 0x440803 |
| #define regBIFPLR2_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR2_1_LATENCY 0x440803 |
| #define regBIFPLR2_1_LATENCY_BASE_IDX 5 |
| #define regBIFPLR2_1_HEADER 0x440803 |
| #define regBIFPLR2_1_HEADER_BASE_IDX 5 |
| #define regBIFPLR2_1_BIST 0x440803 |
| #define regBIFPLR2_1_BIST_BASE_IDX 5 |
| #define regBIFPLR2_1_SUB_BUS_NUMBER_LATENCY 0x440806 |
| #define regBIFPLR2_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR2_1_IO_BASE_LIMIT 0x440807 |
| #define regBIFPLR2_1_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR2_1_SECONDARY_STATUS 0x440807 |
| #define regBIFPLR2_1_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_MEM_BASE_LIMIT 0x440808 |
| #define regBIFPLR2_1_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR2_1_PREF_BASE_LIMIT 0x440809 |
| #define regBIFPLR2_1_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR2_1_PREF_BASE_UPPER 0x44080a |
| #define regBIFPLR2_1_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR2_1_PREF_LIMIT_UPPER 0x44080b |
| #define regBIFPLR2_1_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR2_1_IO_BASE_LIMIT_HI 0x44080c |
| #define regBIFPLR2_1_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR2_1_CAP_PTR 0x44080d |
| #define regBIFPLR2_1_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR2_1_ROM_BASE_ADDR 0x44080e |
| #define regBIFPLR2_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIFPLR2_1_INTERRUPT_LINE 0x44080f |
| #define regBIFPLR2_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR2_1_INTERRUPT_PIN 0x44080f |
| #define regBIFPLR2_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR2_1_EXT_BRIDGE_CNTL 0x440810 |
| #define regBIFPLR2_1_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_VENDOR_CAP_LIST 0x440812 |
| #define regBIFPLR2_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_ADAPTER_ID_W 0x440813 |
| #define regBIFPLR2_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIFPLR2_1_PMI_CAP_LIST 0x440814 |
| #define regBIFPLR2_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PMI_CAP 0x440814 |
| #define regBIFPLR2_1_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_PMI_STATUS_CNTL 0x440815 |
| #define regBIFPLR2_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CAP_LIST 0x440816 |
| #define regBIFPLR2_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CAP 0x440816 |
| #define regBIFPLR2_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_DEVICE_CAP 0x440817 |
| #define regBIFPLR2_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_DEVICE_CNTL 0x440818 |
| #define regBIFPLR2_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_DEVICE_STATUS 0x440818 |
| #define regBIFPLR2_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LINK_CAP 0x440819 |
| #define regBIFPLR2_1_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_LINK_CNTL 0x44081a |
| #define regBIFPLR2_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LINK_STATUS 0x44081a |
| #define regBIFPLR2_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_SLOT_CAP 0x44081b |
| #define regBIFPLR2_1_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_SLOT_CNTL 0x44081c |
| #define regBIFPLR2_1_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_SLOT_STATUS 0x44081c |
| #define regBIFPLR2_1_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_ROOT_CNTL 0x44081d |
| #define regBIFPLR2_1_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_ROOT_CAP 0x44081d |
| #define regBIFPLR2_1_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_ROOT_STATUS 0x44081e |
| #define regBIFPLR2_1_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_DEVICE_CAP2 0x44081f |
| #define regBIFPLR2_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR2_1_DEVICE_CNTL2 0x440820 |
| #define regBIFPLR2_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_1_DEVICE_STATUS2 0x440820 |
| #define regBIFPLR2_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR2_1_LINK_CAP2 0x440821 |
| #define regBIFPLR2_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR2_1_LINK_CNTL2 0x440822 |
| #define regBIFPLR2_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_1_LINK_STATUS2 0x440822 |
| #define regBIFPLR2_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR2_1_SLOT_CAP2 0x440823 |
| #define regBIFPLR2_1_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR2_1_SLOT_CNTL2 0x440824 |
| #define regBIFPLR2_1_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_1_SLOT_STATUS2 0x440824 |
| #define regBIFPLR2_1_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR2_1_MSI_CAP_LIST 0x440828 |
| #define regBIFPLR2_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_MSI_MSG_CNTL 0x440828 |
| #define regBIFPLR2_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_MSI_MSG_ADDR_LO 0x440829 |
| #define regBIFPLR2_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR2_1_MSI_MSG_ADDR_HI 0x44082a |
| #define regBIFPLR2_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR2_1_MSI_MSG_DATA 0x44082a |
| #define regBIFPLR2_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR2_1_MSI_MSG_DATA_64 0x44082b |
| #define regBIFPLR2_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR2_1_SSID_CAP_LIST 0x440830 |
| #define regBIFPLR2_1_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_SSID_CAP 0x440831 |
| #define regBIFPLR2_1_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_MSI_MAP_CAP_LIST 0x440832 |
| #define regBIFPLR2_1_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_MSI_MAP_CAP 0x440832 |
| #define regBIFPLR2_1_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x440840 |
| #define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR 0x440841 |
| #define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC1 0x440842 |
| #define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC2 0x440843 |
| #define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_VC_ENH_CAP_LIST 0x440844 |
| #define regBIFPLR2_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_PORT_VC_CAP_REG1 0x440845 |
| #define regBIFPLR2_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_PORT_VC_CAP_REG2 0x440846 |
| #define regBIFPLR2_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_PORT_VC_CNTL 0x440847 |
| #define regBIFPLR2_1_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_PORT_VC_STATUS 0x440847 |
| #define regBIFPLR2_1_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_VC0_RESOURCE_CAP 0x440848 |
| #define regBIFPLR2_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_VC0_RESOURCE_CNTL 0x440849 |
| #define regBIFPLR2_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_VC0_RESOURCE_STATUS 0x44084a |
| #define regBIFPLR2_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_VC1_RESOURCE_CAP 0x44084b |
| #define regBIFPLR2_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_VC1_RESOURCE_CNTL 0x44084c |
| #define regBIFPLR2_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_VC1_RESOURCE_STATUS 0x44084d |
| #define regBIFPLR2_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x440850 |
| #define regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1 0x440851 |
| #define regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2 0x440852 |
| #define regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x440854 |
| #define regBIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_UNCORR_ERR_STATUS 0x440855 |
| #define regBIFPLR2_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_UNCORR_ERR_MASK 0x440856 |
| #define regBIFPLR2_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY 0x440857 |
| #define regBIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CORR_ERR_STATUS 0x440858 |
| #define regBIFPLR2_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CORR_ERR_MASK 0x440859 |
| #define regBIFPLR2_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL 0x44085a |
| #define regBIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_HDR_LOG0 0x44085b |
| #define regBIFPLR2_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_HDR_LOG1 0x44085c |
| #define regBIFPLR2_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_HDR_LOG2 0x44085d |
| #define regBIFPLR2_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_HDR_LOG3 0x44085e |
| #define regBIFPLR2_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ROOT_ERR_CMD 0x44085f |
| #define regBIFPLR2_1_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ROOT_ERR_STATUS 0x440860 |
| #define regBIFPLR2_1_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ERR_SRC_ID 0x440861 |
| #define regBIFPLR2_1_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG0 0x440862 |
| #define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG1 0x440863 |
| #define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG2 0x440864 |
| #define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG3 0x440865 |
| #define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST 0x44089c |
| #define regBIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LINK_CNTL3 0x44089d |
| #define regBIFPLR2_1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_ERROR_STATUS 0x44089e |
| #define regBIFPLR2_1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x44089f |
| #define regBIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x44089f |
| #define regBIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x4408a0 |
| #define regBIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x4408a0 |
| #define regBIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x4408a1 |
| #define regBIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x4408a1 |
| #define regBIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x4408a2 |
| #define regBIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x4408a2 |
| #define regBIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x4408a3 |
| #define regBIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x4408a3 |
| #define regBIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x4408a4 |
| #define regBIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x4408a4 |
| #define regBIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x4408a5 |
| #define regBIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x4408a5 |
| #define regBIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x4408a6 |
| #define regBIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x4408a6 |
| #define regBIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ACS_ENH_CAP_LIST 0x4408a8 |
| #define regBIFPLR2_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ACS_CAP 0x4408a9 |
| #define regBIFPLR2_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ACS_CNTL 0x4408a9 |
| #define regBIFPLR2_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_ENH_CAP_LIST 0x4408bc |
| #define regBIFPLR2_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_CAP 0x4408bd |
| #define regBIFPLR2_1_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_CNTL 0x4408bd |
| #define regBIFPLR2_1_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_ADDR0 0x4408be |
| #define regBIFPLR2_1_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_ADDR1 0x4408bf |
| #define regBIFPLR2_1_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_RCV0 0x4408c0 |
| #define regBIFPLR2_1_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_RCV1 0x4408c1 |
| #define regBIFPLR2_1_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_BLOCK_ALL0 0x4408c2 |
| #define regBIFPLR2_1_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_BLOCK_ALL1 0x4408c3 |
| #define regBIFPLR2_1_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x4408c4 |
| #define regBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x4408c5 |
| #define regBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_OVERLAY_BAR0 0x4408c6 |
| #define regBIFPLR2_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MC_OVERLAY_BAR1 0x4408c7 |
| #define regBIFPLR2_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST 0x4408dc |
| #define regBIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_L1_PM_SUB_CAP 0x4408dd |
| #define regBIFPLR2_1_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_L1_PM_SUB_CNTL 0x4408de |
| #define regBIFPLR2_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_L1_PM_SUB_CNTL2 0x4408df |
| #define regBIFPLR2_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_DPC_ENH_CAP_LIST 0x4408e0 |
| #define regBIFPLR2_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_DPC_CAP_LIST 0x4408e1 |
| #define regBIFPLR2_1_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_DPC_CNTL 0x4408e1 |
| #define regBIFPLR2_1_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_DPC_STATUS 0x4408e2 |
| #define regBIFPLR2_1_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID 0x4408e2 |
| #define regBIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_STATUS 0x4408e3 |
| #define regBIFPLR2_1_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_MASK 0x4408e4 |
| #define regBIFPLR2_1_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_SEVERITY 0x4408e5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_SYSERROR 0x4408e6 |
| #define regBIFPLR2_1_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_EXCEPTION 0x4408e7 |
| #define regBIFPLR2_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG0 0x4408e8 |
| #define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG1 0x4408e9 |
| #define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG2 0x4408ea |
| #define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG3 0x4408eb |
| #define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0 0x4408ed |
| #define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1 0x4408ee |
| #define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2 0x4408ef |
| #define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3 0x4408f0 |
| #define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_LIST 0x4408f1 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ESM_HEADER_1 0x4408f2 |
| #define regBIFPLR2_1_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ESM_HEADER_2 0x4408f3 |
| #define regBIFPLR2_1_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ESM_STATUS 0x4408f3 |
| #define regBIFPLR2_1_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ESM_CTRL 0x4408f4 |
| #define regBIFPLR2_1_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_1 0x4408f5 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_2 0x4408f6 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_3 0x4408f7 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_4 0x4408f8 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_5 0x4408f9 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_6 0x4408fa |
| #define regBIFPLR2_1_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_ESM_CAP_7 0x4408fb |
| #define regBIFPLR2_1_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_DLF_ENH_CAP_LIST 0x440900 |
| #define regBIFPLR2_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_DATA_LINK_FEATURE_CAP 0x440901 |
| #define regBIFPLR2_1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_DATA_LINK_FEATURE_STATUS 0x440902 |
| #define regBIFPLR2_1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x440904 |
| #define regBIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_LINK_CAP_16GT 0x440905 |
| #define regBIFPLR2_1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LINK_CNTL_16GT 0x440906 |
| #define regBIFPLR2_1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LINK_STATUS_16GT 0x440907 |
| #define regBIFPLR2_1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x440908 |
| #define regBIFPLR2_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x440909 |
| #define regBIFPLR2_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x44090a |
| #define regBIFPLR2_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT 0x44090c |
| #define regBIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT 0x44090c |
| #define regBIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT 0x44090c |
| #define regBIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT 0x44090c |
| #define regBIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT 0x44090d |
| #define regBIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT 0x44090d |
| #define regBIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT 0x44090d |
| #define regBIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT 0x44090d |
| #define regBIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT 0x44090e |
| #define regBIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT 0x44090e |
| #define regBIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT 0x44090e |
| #define regBIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT 0x44090e |
| #define regBIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT 0x44090f |
| #define regBIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT 0x44090f |
| #define regBIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT 0x44090f |
| #define regBIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT 0x44090f |
| #define regBIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST 0x440910 |
| #define regBIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_MARGINING_PORT_CAP 0x440911 |
| #define regBIFPLR2_1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_MARGINING_PORT_STATUS 0x440911 |
| #define regBIFPLR2_1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_0_MARGINING_LANE_CNTL 0x440912 |
| #define regBIFPLR2_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_0_MARGINING_LANE_STATUS 0x440912 |
| #define regBIFPLR2_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_1_MARGINING_LANE_CNTL 0x440913 |
| #define regBIFPLR2_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_1_MARGINING_LANE_STATUS 0x440913 |
| #define regBIFPLR2_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_2_MARGINING_LANE_CNTL 0x440914 |
| #define regBIFPLR2_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_2_MARGINING_LANE_STATUS 0x440914 |
| #define regBIFPLR2_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_3_MARGINING_LANE_CNTL 0x440915 |
| #define regBIFPLR2_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_3_MARGINING_LANE_STATUS 0x440915 |
| #define regBIFPLR2_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_4_MARGINING_LANE_CNTL 0x440916 |
| #define regBIFPLR2_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_4_MARGINING_LANE_STATUS 0x440916 |
| #define regBIFPLR2_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_5_MARGINING_LANE_CNTL 0x440917 |
| #define regBIFPLR2_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_5_MARGINING_LANE_STATUS 0x440917 |
| #define regBIFPLR2_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_6_MARGINING_LANE_CNTL 0x440918 |
| #define regBIFPLR2_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_6_MARGINING_LANE_STATUS 0x440918 |
| #define regBIFPLR2_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_7_MARGINING_LANE_CNTL 0x440919 |
| #define regBIFPLR2_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_7_MARGINING_LANE_STATUS 0x440919 |
| #define regBIFPLR2_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_8_MARGINING_LANE_CNTL 0x44091a |
| #define regBIFPLR2_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_8_MARGINING_LANE_STATUS 0x44091a |
| #define regBIFPLR2_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_9_MARGINING_LANE_CNTL 0x44091b |
| #define regBIFPLR2_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_9_MARGINING_LANE_STATUS 0x44091b |
| #define regBIFPLR2_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_10_MARGINING_LANE_CNTL 0x44091c |
| #define regBIFPLR2_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_10_MARGINING_LANE_STATUS 0x44091c |
| #define regBIFPLR2_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_11_MARGINING_LANE_CNTL 0x44091d |
| #define regBIFPLR2_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_11_MARGINING_LANE_STATUS 0x44091d |
| #define regBIFPLR2_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_12_MARGINING_LANE_CNTL 0x44091e |
| #define regBIFPLR2_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_12_MARGINING_LANE_STATUS 0x44091e |
| #define regBIFPLR2_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_13_MARGINING_LANE_CNTL 0x44091f |
| #define regBIFPLR2_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_13_MARGINING_LANE_STATUS 0x44091f |
| #define regBIFPLR2_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_14_MARGINING_LANE_CNTL 0x440920 |
| #define regBIFPLR2_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_14_MARGINING_LANE_STATUS 0x440920 |
| #define regBIFPLR2_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_15_MARGINING_LANE_CNTL 0x440921 |
| #define regBIFPLR2_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LANE_15_MARGINING_LANE_STATUS 0x440921 |
| #define regBIFPLR2_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CCIX_CAP_LIST 0x440922 |
| #define regBIFPLR2_1_PCIE_CCIX_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CCIX_HEADER_1 0x440923 |
| #define regBIFPLR2_1_PCIE_CCIX_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CCIX_HEADER_2 0x440924 |
| #define regBIFPLR2_1_PCIE_CCIX_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CCIX_CAP 0x440924 |
| #define regBIFPLR2_1_PCIE_CCIX_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP 0x440925 |
| #define regBIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CCIX_ESM_OPTL_CAP 0x440926 |
| #define regBIFPLR2_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CCIX_ESM_STATUS 0x440927 |
| #define regBIFPLR2_1_PCIE_CCIX_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CCIX_ESM_CNTL 0x440928 |
| #define regBIFPLR2_1_PCIE_CCIX_ESM_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x440929 |
| #define regBIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x440929 |
| #define regBIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x440929 |
| #define regBIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x440929 |
| #define regBIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x44092a |
| #define regBIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x44092a |
| #define regBIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x44092a |
| #define regBIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x44092a |
| #define regBIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x44092b |
| #define regBIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x44092b |
| #define regBIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x44092b |
| #define regBIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x44092b |
| #define regBIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x44092c |
| #define regBIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x44092c |
| #define regBIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x44092c |
| #define regBIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x44092c |
| #define regBIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x44092d |
| #define regBIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x44092d |
| #define regBIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x44092d |
| #define regBIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x44092d |
| #define regBIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x44092e |
| #define regBIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x44092e |
| #define regBIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x44092e |
| #define regBIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x44092e |
| #define regBIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x44092f |
| #define regBIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x44092f |
| #define regBIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x44092f |
| #define regBIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x44092f |
| #define regBIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x440930 |
| #define regBIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x440930 |
| #define regBIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x440930 |
| #define regBIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x440930 |
| #define regBIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CCIX_TRANS_CAP 0x440931 |
| #define regBIFPLR2_1_PCIE_CCIX_TRANS_CAP_BASE_IDX 5 |
| #define regBIFPLR2_1_PCIE_CCIX_TRANS_CNTL 0x440932 |
| #define regBIFPLR2_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_1_LINK_CAP_32GT 0x440941 |
| #define regBIFPLR2_1_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LINK_CNTL_32GT 0x440942 |
| #define regBIFPLR2_1_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR2_1_LINK_STATUS_32GT 0x440943 |
| #define regBIFPLR2_1_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifplr3_cfgdecp |
| // base address: 0x11203000 |
| #define regBIFPLR3_1_VENDOR_ID 0x440c00 |
| #define regBIFPLR3_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR3_1_DEVICE_ID 0x440c00 |
| #define regBIFPLR3_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR3_1_COMMAND 0x440c01 |
| #define regBIFPLR3_1_COMMAND_BASE_IDX 5 |
| #define regBIFPLR3_1_STATUS 0x440c01 |
| #define regBIFPLR3_1_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_REVISION_ID 0x440c02 |
| #define regBIFPLR3_1_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR3_1_PROG_INTERFACE 0x440c02 |
| #define regBIFPLR3_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR3_1_SUB_CLASS 0x440c02 |
| #define regBIFPLR3_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR3_1_BASE_CLASS 0x440c02 |
| #define regBIFPLR3_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR3_1_CACHE_LINE 0x440c03 |
| #define regBIFPLR3_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR3_1_LATENCY 0x440c03 |
| #define regBIFPLR3_1_LATENCY_BASE_IDX 5 |
| #define regBIFPLR3_1_HEADER 0x440c03 |
| #define regBIFPLR3_1_HEADER_BASE_IDX 5 |
| #define regBIFPLR3_1_BIST 0x440c03 |
| #define regBIFPLR3_1_BIST_BASE_IDX 5 |
| #define regBIFPLR3_1_SUB_BUS_NUMBER_LATENCY 0x440c06 |
| #define regBIFPLR3_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR3_1_IO_BASE_LIMIT 0x440c07 |
| #define regBIFPLR3_1_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR3_1_SECONDARY_STATUS 0x440c07 |
| #define regBIFPLR3_1_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_MEM_BASE_LIMIT 0x440c08 |
| #define regBIFPLR3_1_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR3_1_PREF_BASE_LIMIT 0x440c09 |
| #define regBIFPLR3_1_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR3_1_PREF_BASE_UPPER 0x440c0a |
| #define regBIFPLR3_1_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR3_1_PREF_LIMIT_UPPER 0x440c0b |
| #define regBIFPLR3_1_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR3_1_IO_BASE_LIMIT_HI 0x440c0c |
| #define regBIFPLR3_1_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR3_1_CAP_PTR 0x440c0d |
| #define regBIFPLR3_1_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR3_1_ROM_BASE_ADDR 0x440c0e |
| #define regBIFPLR3_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIFPLR3_1_INTERRUPT_LINE 0x440c0f |
| #define regBIFPLR3_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR3_1_INTERRUPT_PIN 0x440c0f |
| #define regBIFPLR3_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR3_1_EXT_BRIDGE_CNTL 0x440c10 |
| #define regBIFPLR3_1_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_VENDOR_CAP_LIST 0x440c12 |
| #define regBIFPLR3_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_ADAPTER_ID_W 0x440c13 |
| #define regBIFPLR3_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIFPLR3_1_PMI_CAP_LIST 0x440c14 |
| #define regBIFPLR3_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PMI_CAP 0x440c14 |
| #define regBIFPLR3_1_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_PMI_STATUS_CNTL 0x440c15 |
| #define regBIFPLR3_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CAP_LIST 0x440c16 |
| #define regBIFPLR3_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CAP 0x440c16 |
| #define regBIFPLR3_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_DEVICE_CAP 0x440c17 |
| #define regBIFPLR3_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_DEVICE_CNTL 0x440c18 |
| #define regBIFPLR3_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_DEVICE_STATUS 0x440c18 |
| #define regBIFPLR3_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LINK_CAP 0x440c19 |
| #define regBIFPLR3_1_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_LINK_CNTL 0x440c1a |
| #define regBIFPLR3_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LINK_STATUS 0x440c1a |
| #define regBIFPLR3_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_SLOT_CAP 0x440c1b |
| #define regBIFPLR3_1_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_SLOT_CNTL 0x440c1c |
| #define regBIFPLR3_1_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_SLOT_STATUS 0x440c1c |
| #define regBIFPLR3_1_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_ROOT_CNTL 0x440c1d |
| #define regBIFPLR3_1_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_ROOT_CAP 0x440c1d |
| #define regBIFPLR3_1_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_ROOT_STATUS 0x440c1e |
| #define regBIFPLR3_1_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_DEVICE_CAP2 0x440c1f |
| #define regBIFPLR3_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR3_1_DEVICE_CNTL2 0x440c20 |
| #define regBIFPLR3_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_1_DEVICE_STATUS2 0x440c20 |
| #define regBIFPLR3_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR3_1_LINK_CAP2 0x440c21 |
| #define regBIFPLR3_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR3_1_LINK_CNTL2 0x440c22 |
| #define regBIFPLR3_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_1_LINK_STATUS2 0x440c22 |
| #define regBIFPLR3_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR3_1_SLOT_CAP2 0x440c23 |
| #define regBIFPLR3_1_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR3_1_SLOT_CNTL2 0x440c24 |
| #define regBIFPLR3_1_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_1_SLOT_STATUS2 0x440c24 |
| #define regBIFPLR3_1_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR3_1_MSI_CAP_LIST 0x440c28 |
| #define regBIFPLR3_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_MSI_MSG_CNTL 0x440c28 |
| #define regBIFPLR3_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_MSI_MSG_ADDR_LO 0x440c29 |
| #define regBIFPLR3_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR3_1_MSI_MSG_ADDR_HI 0x440c2a |
| #define regBIFPLR3_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR3_1_MSI_MSG_DATA 0x440c2a |
| #define regBIFPLR3_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR3_1_MSI_MSG_DATA_64 0x440c2b |
| #define regBIFPLR3_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR3_1_SSID_CAP_LIST 0x440c30 |
| #define regBIFPLR3_1_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_SSID_CAP 0x440c31 |
| #define regBIFPLR3_1_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_MSI_MAP_CAP_LIST 0x440c32 |
| #define regBIFPLR3_1_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_MSI_MAP_CAP 0x440c32 |
| #define regBIFPLR3_1_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x440c40 |
| #define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR 0x440c41 |
| #define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC1 0x440c42 |
| #define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC2 0x440c43 |
| #define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_VC_ENH_CAP_LIST 0x440c44 |
| #define regBIFPLR3_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_PORT_VC_CAP_REG1 0x440c45 |
| #define regBIFPLR3_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_PORT_VC_CAP_REG2 0x440c46 |
| #define regBIFPLR3_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_PORT_VC_CNTL 0x440c47 |
| #define regBIFPLR3_1_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_PORT_VC_STATUS 0x440c47 |
| #define regBIFPLR3_1_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_VC0_RESOURCE_CAP 0x440c48 |
| #define regBIFPLR3_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_VC0_RESOURCE_CNTL 0x440c49 |
| #define regBIFPLR3_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_VC0_RESOURCE_STATUS 0x440c4a |
| #define regBIFPLR3_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_VC1_RESOURCE_CAP 0x440c4b |
| #define regBIFPLR3_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_VC1_RESOURCE_CNTL 0x440c4c |
| #define regBIFPLR3_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_VC1_RESOURCE_STATUS 0x440c4d |
| #define regBIFPLR3_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x440c50 |
| #define regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1 0x440c51 |
| #define regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2 0x440c52 |
| #define regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x440c54 |
| #define regBIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_UNCORR_ERR_STATUS 0x440c55 |
| #define regBIFPLR3_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_UNCORR_ERR_MASK 0x440c56 |
| #define regBIFPLR3_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY 0x440c57 |
| #define regBIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CORR_ERR_STATUS 0x440c58 |
| #define regBIFPLR3_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CORR_ERR_MASK 0x440c59 |
| #define regBIFPLR3_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL 0x440c5a |
| #define regBIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_HDR_LOG0 0x440c5b |
| #define regBIFPLR3_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_HDR_LOG1 0x440c5c |
| #define regBIFPLR3_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_HDR_LOG2 0x440c5d |
| #define regBIFPLR3_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_HDR_LOG3 0x440c5e |
| #define regBIFPLR3_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ROOT_ERR_CMD 0x440c5f |
| #define regBIFPLR3_1_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ROOT_ERR_STATUS 0x440c60 |
| #define regBIFPLR3_1_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ERR_SRC_ID 0x440c61 |
| #define regBIFPLR3_1_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG0 0x440c62 |
| #define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG1 0x440c63 |
| #define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG2 0x440c64 |
| #define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG3 0x440c65 |
| #define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST 0x440c9c |
| #define regBIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LINK_CNTL3 0x440c9d |
| #define regBIFPLR3_1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_ERROR_STATUS 0x440c9e |
| #define regBIFPLR3_1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x440c9f |
| #define regBIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x440c9f |
| #define regBIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x440ca0 |
| #define regBIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x440ca0 |
| #define regBIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x440ca1 |
| #define regBIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x440ca1 |
| #define regBIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x440ca2 |
| #define regBIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x440ca2 |
| #define regBIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x440ca3 |
| #define regBIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x440ca3 |
| #define regBIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x440ca4 |
| #define regBIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x440ca4 |
| #define regBIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x440ca5 |
| #define regBIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x440ca5 |
| #define regBIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x440ca6 |
| #define regBIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x440ca6 |
| #define regBIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ACS_ENH_CAP_LIST 0x440ca8 |
| #define regBIFPLR3_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ACS_CAP 0x440ca9 |
| #define regBIFPLR3_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ACS_CNTL 0x440ca9 |
| #define regBIFPLR3_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_ENH_CAP_LIST 0x440cbc |
| #define regBIFPLR3_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_CAP 0x440cbd |
| #define regBIFPLR3_1_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_CNTL 0x440cbd |
| #define regBIFPLR3_1_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_ADDR0 0x440cbe |
| #define regBIFPLR3_1_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_ADDR1 0x440cbf |
| #define regBIFPLR3_1_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_RCV0 0x440cc0 |
| #define regBIFPLR3_1_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_RCV1 0x440cc1 |
| #define regBIFPLR3_1_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_BLOCK_ALL0 0x440cc2 |
| #define regBIFPLR3_1_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_BLOCK_ALL1 0x440cc3 |
| #define regBIFPLR3_1_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x440cc4 |
| #define regBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x440cc5 |
| #define regBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_OVERLAY_BAR0 0x440cc6 |
| #define regBIFPLR3_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MC_OVERLAY_BAR1 0x440cc7 |
| #define regBIFPLR3_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST 0x440cdc |
| #define regBIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_L1_PM_SUB_CAP 0x440cdd |
| #define regBIFPLR3_1_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_L1_PM_SUB_CNTL 0x440cde |
| #define regBIFPLR3_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_L1_PM_SUB_CNTL2 0x440cdf |
| #define regBIFPLR3_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_DPC_ENH_CAP_LIST 0x440ce0 |
| #define regBIFPLR3_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_DPC_CAP_LIST 0x440ce1 |
| #define regBIFPLR3_1_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_DPC_CNTL 0x440ce1 |
| #define regBIFPLR3_1_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_DPC_STATUS 0x440ce2 |
| #define regBIFPLR3_1_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID 0x440ce2 |
| #define regBIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_STATUS 0x440ce3 |
| #define regBIFPLR3_1_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_MASK 0x440ce4 |
| #define regBIFPLR3_1_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_SEVERITY 0x440ce5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_SYSERROR 0x440ce6 |
| #define regBIFPLR3_1_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_EXCEPTION 0x440ce7 |
| #define regBIFPLR3_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG0 0x440ce8 |
| #define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG1 0x440ce9 |
| #define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG2 0x440cea |
| #define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG3 0x440ceb |
| #define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0 0x440ced |
| #define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1 0x440cee |
| #define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2 0x440cef |
| #define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3 0x440cf0 |
| #define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_LIST 0x440cf1 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ESM_HEADER_1 0x440cf2 |
| #define regBIFPLR3_1_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ESM_HEADER_2 0x440cf3 |
| #define regBIFPLR3_1_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ESM_STATUS 0x440cf3 |
| #define regBIFPLR3_1_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ESM_CTRL 0x440cf4 |
| #define regBIFPLR3_1_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_1 0x440cf5 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_2 0x440cf6 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_3 0x440cf7 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_4 0x440cf8 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_5 0x440cf9 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_6 0x440cfa |
| #define regBIFPLR3_1_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_ESM_CAP_7 0x440cfb |
| #define regBIFPLR3_1_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_DLF_ENH_CAP_LIST 0x440d00 |
| #define regBIFPLR3_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_DATA_LINK_FEATURE_CAP 0x440d01 |
| #define regBIFPLR3_1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_DATA_LINK_FEATURE_STATUS 0x440d02 |
| #define regBIFPLR3_1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x440d04 |
| #define regBIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_LINK_CAP_16GT 0x440d05 |
| #define regBIFPLR3_1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LINK_CNTL_16GT 0x440d06 |
| #define regBIFPLR3_1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LINK_STATUS_16GT 0x440d07 |
| #define regBIFPLR3_1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x440d08 |
| #define regBIFPLR3_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x440d09 |
| #define regBIFPLR3_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x440d0a |
| #define regBIFPLR3_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT 0x440d0c |
| #define regBIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT 0x440d0c |
| #define regBIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT 0x440d0c |
| #define regBIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT 0x440d0c |
| #define regBIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT 0x440d0d |
| #define regBIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT 0x440d0d |
| #define regBIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT 0x440d0d |
| #define regBIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT 0x440d0d |
| #define regBIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT 0x440d0e |
| #define regBIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT 0x440d0e |
| #define regBIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT 0x440d0e |
| #define regBIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT 0x440d0e |
| #define regBIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT 0x440d0f |
| #define regBIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT 0x440d0f |
| #define regBIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT 0x440d0f |
| #define regBIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT 0x440d0f |
| #define regBIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST 0x440d10 |
| #define regBIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_MARGINING_PORT_CAP 0x440d11 |
| #define regBIFPLR3_1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_MARGINING_PORT_STATUS 0x440d11 |
| #define regBIFPLR3_1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_0_MARGINING_LANE_CNTL 0x440d12 |
| #define regBIFPLR3_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_0_MARGINING_LANE_STATUS 0x440d12 |
| #define regBIFPLR3_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_1_MARGINING_LANE_CNTL 0x440d13 |
| #define regBIFPLR3_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_1_MARGINING_LANE_STATUS 0x440d13 |
| #define regBIFPLR3_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_2_MARGINING_LANE_CNTL 0x440d14 |
| #define regBIFPLR3_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_2_MARGINING_LANE_STATUS 0x440d14 |
| #define regBIFPLR3_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_3_MARGINING_LANE_CNTL 0x440d15 |
| #define regBIFPLR3_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_3_MARGINING_LANE_STATUS 0x440d15 |
| #define regBIFPLR3_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_4_MARGINING_LANE_CNTL 0x440d16 |
| #define regBIFPLR3_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_4_MARGINING_LANE_STATUS 0x440d16 |
| #define regBIFPLR3_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_5_MARGINING_LANE_CNTL 0x440d17 |
| #define regBIFPLR3_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_5_MARGINING_LANE_STATUS 0x440d17 |
| #define regBIFPLR3_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_6_MARGINING_LANE_CNTL 0x440d18 |
| #define regBIFPLR3_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_6_MARGINING_LANE_STATUS 0x440d18 |
| #define regBIFPLR3_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_7_MARGINING_LANE_CNTL 0x440d19 |
| #define regBIFPLR3_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_7_MARGINING_LANE_STATUS 0x440d19 |
| #define regBIFPLR3_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_8_MARGINING_LANE_CNTL 0x440d1a |
| #define regBIFPLR3_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_8_MARGINING_LANE_STATUS 0x440d1a |
| #define regBIFPLR3_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_9_MARGINING_LANE_CNTL 0x440d1b |
| #define regBIFPLR3_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_9_MARGINING_LANE_STATUS 0x440d1b |
| #define regBIFPLR3_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_10_MARGINING_LANE_CNTL 0x440d1c |
| #define regBIFPLR3_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_10_MARGINING_LANE_STATUS 0x440d1c |
| #define regBIFPLR3_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_11_MARGINING_LANE_CNTL 0x440d1d |
| #define regBIFPLR3_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_11_MARGINING_LANE_STATUS 0x440d1d |
| #define regBIFPLR3_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_12_MARGINING_LANE_CNTL 0x440d1e |
| #define regBIFPLR3_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_12_MARGINING_LANE_STATUS 0x440d1e |
| #define regBIFPLR3_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_13_MARGINING_LANE_CNTL 0x440d1f |
| #define regBIFPLR3_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_13_MARGINING_LANE_STATUS 0x440d1f |
| #define regBIFPLR3_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_14_MARGINING_LANE_CNTL 0x440d20 |
| #define regBIFPLR3_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_14_MARGINING_LANE_STATUS 0x440d20 |
| #define regBIFPLR3_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_15_MARGINING_LANE_CNTL 0x440d21 |
| #define regBIFPLR3_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LANE_15_MARGINING_LANE_STATUS 0x440d21 |
| #define regBIFPLR3_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CCIX_CAP_LIST 0x440d22 |
| #define regBIFPLR3_1_PCIE_CCIX_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CCIX_HEADER_1 0x440d23 |
| #define regBIFPLR3_1_PCIE_CCIX_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CCIX_HEADER_2 0x440d24 |
| #define regBIFPLR3_1_PCIE_CCIX_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CCIX_CAP 0x440d24 |
| #define regBIFPLR3_1_PCIE_CCIX_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP 0x440d25 |
| #define regBIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CCIX_ESM_OPTL_CAP 0x440d26 |
| #define regBIFPLR3_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CCIX_ESM_STATUS 0x440d27 |
| #define regBIFPLR3_1_PCIE_CCIX_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CCIX_ESM_CNTL 0x440d28 |
| #define regBIFPLR3_1_PCIE_CCIX_ESM_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x440d29 |
| #define regBIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x440d29 |
| #define regBIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x440d29 |
| #define regBIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x440d29 |
| #define regBIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x440d2a |
| #define regBIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x440d2a |
| #define regBIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x440d2a |
| #define regBIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x440d2a |
| #define regBIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x440d2b |
| #define regBIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x440d2b |
| #define regBIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x440d2b |
| #define regBIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x440d2b |
| #define regBIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x440d2c |
| #define regBIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x440d2c |
| #define regBIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x440d2c |
| #define regBIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x440d2c |
| #define regBIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x440d2d |
| #define regBIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x440d2d |
| #define regBIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x440d2d |
| #define regBIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x440d2d |
| #define regBIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x440d2e |
| #define regBIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x440d2e |
| #define regBIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x440d2e |
| #define regBIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x440d2e |
| #define regBIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x440d2f |
| #define regBIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x440d2f |
| #define regBIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x440d2f |
| #define regBIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x440d2f |
| #define regBIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x440d30 |
| #define regBIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x440d30 |
| #define regBIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x440d30 |
| #define regBIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x440d30 |
| #define regBIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CCIX_TRANS_CAP 0x440d31 |
| #define regBIFPLR3_1_PCIE_CCIX_TRANS_CAP_BASE_IDX 5 |
| #define regBIFPLR3_1_PCIE_CCIX_TRANS_CNTL 0x440d32 |
| #define regBIFPLR3_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_1_LINK_CAP_32GT 0x440d41 |
| #define regBIFPLR3_1_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LINK_CNTL_32GT 0x440d42 |
| #define regBIFPLR3_1_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR3_1_LINK_STATUS_32GT 0x440d43 |
| #define regBIFPLR3_1_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifplr4_cfgdecp |
| // base address: 0x11204000 |
| #define regBIFPLR4_1_VENDOR_ID 0x441000 |
| #define regBIFPLR4_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR4_1_DEVICE_ID 0x441000 |
| #define regBIFPLR4_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR4_1_COMMAND 0x441001 |
| #define regBIFPLR4_1_COMMAND_BASE_IDX 5 |
| #define regBIFPLR4_1_STATUS 0x441001 |
| #define regBIFPLR4_1_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_REVISION_ID 0x441002 |
| #define regBIFPLR4_1_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR4_1_PROG_INTERFACE 0x441002 |
| #define regBIFPLR4_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR4_1_SUB_CLASS 0x441002 |
| #define regBIFPLR4_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR4_1_BASE_CLASS 0x441002 |
| #define regBIFPLR4_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR4_1_CACHE_LINE 0x441003 |
| #define regBIFPLR4_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR4_1_LATENCY 0x441003 |
| #define regBIFPLR4_1_LATENCY_BASE_IDX 5 |
| #define regBIFPLR4_1_HEADER 0x441003 |
| #define regBIFPLR4_1_HEADER_BASE_IDX 5 |
| #define regBIFPLR4_1_BIST 0x441003 |
| #define regBIFPLR4_1_BIST_BASE_IDX 5 |
| #define regBIFPLR4_1_SUB_BUS_NUMBER_LATENCY 0x441006 |
| #define regBIFPLR4_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR4_1_IO_BASE_LIMIT 0x441007 |
| #define regBIFPLR4_1_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR4_1_SECONDARY_STATUS 0x441007 |
| #define regBIFPLR4_1_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_MEM_BASE_LIMIT 0x441008 |
| #define regBIFPLR4_1_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR4_1_PREF_BASE_LIMIT 0x441009 |
| #define regBIFPLR4_1_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR4_1_PREF_BASE_UPPER 0x44100a |
| #define regBIFPLR4_1_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR4_1_PREF_LIMIT_UPPER 0x44100b |
| #define regBIFPLR4_1_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR4_1_IO_BASE_LIMIT_HI 0x44100c |
| #define regBIFPLR4_1_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR4_1_CAP_PTR 0x44100d |
| #define regBIFPLR4_1_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR4_1_ROM_BASE_ADDR 0x44100e |
| #define regBIFPLR4_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIFPLR4_1_INTERRUPT_LINE 0x44100f |
| #define regBIFPLR4_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR4_1_INTERRUPT_PIN 0x44100f |
| #define regBIFPLR4_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR4_1_EXT_BRIDGE_CNTL 0x441010 |
| #define regBIFPLR4_1_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_VENDOR_CAP_LIST 0x441012 |
| #define regBIFPLR4_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_ADAPTER_ID_W 0x441013 |
| #define regBIFPLR4_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIFPLR4_1_PMI_CAP_LIST 0x441014 |
| #define regBIFPLR4_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PMI_CAP 0x441014 |
| #define regBIFPLR4_1_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_PMI_STATUS_CNTL 0x441015 |
| #define regBIFPLR4_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CAP_LIST 0x441016 |
| #define regBIFPLR4_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CAP 0x441016 |
| #define regBIFPLR4_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_DEVICE_CAP 0x441017 |
| #define regBIFPLR4_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_DEVICE_CNTL 0x441018 |
| #define regBIFPLR4_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_DEVICE_STATUS 0x441018 |
| #define regBIFPLR4_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LINK_CAP 0x441019 |
| #define regBIFPLR4_1_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_LINK_CNTL 0x44101a |
| #define regBIFPLR4_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LINK_STATUS 0x44101a |
| #define regBIFPLR4_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_SLOT_CAP 0x44101b |
| #define regBIFPLR4_1_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_SLOT_CNTL 0x44101c |
| #define regBIFPLR4_1_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_SLOT_STATUS 0x44101c |
| #define regBIFPLR4_1_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_ROOT_CNTL 0x44101d |
| #define regBIFPLR4_1_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_ROOT_CAP 0x44101d |
| #define regBIFPLR4_1_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_ROOT_STATUS 0x44101e |
| #define regBIFPLR4_1_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_DEVICE_CAP2 0x44101f |
| #define regBIFPLR4_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR4_1_DEVICE_CNTL2 0x441020 |
| #define regBIFPLR4_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_1_DEVICE_STATUS2 0x441020 |
| #define regBIFPLR4_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR4_1_LINK_CAP2 0x441021 |
| #define regBIFPLR4_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR4_1_LINK_CNTL2 0x441022 |
| #define regBIFPLR4_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_1_LINK_STATUS2 0x441022 |
| #define regBIFPLR4_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR4_1_SLOT_CAP2 0x441023 |
| #define regBIFPLR4_1_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR4_1_SLOT_CNTL2 0x441024 |
| #define regBIFPLR4_1_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_1_SLOT_STATUS2 0x441024 |
| #define regBIFPLR4_1_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR4_1_MSI_CAP_LIST 0x441028 |
| #define regBIFPLR4_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_MSI_MSG_CNTL 0x441028 |
| #define regBIFPLR4_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_MSI_MSG_ADDR_LO 0x441029 |
| #define regBIFPLR4_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR4_1_MSI_MSG_ADDR_HI 0x44102a |
| #define regBIFPLR4_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR4_1_MSI_MSG_DATA 0x44102a |
| #define regBIFPLR4_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR4_1_MSI_MSG_DATA_64 0x44102b |
| #define regBIFPLR4_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR4_1_SSID_CAP_LIST 0x441030 |
| #define regBIFPLR4_1_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_SSID_CAP 0x441031 |
| #define regBIFPLR4_1_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_MSI_MAP_CAP_LIST 0x441032 |
| #define regBIFPLR4_1_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_MSI_MAP_CAP 0x441032 |
| #define regBIFPLR4_1_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x441040 |
| #define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR 0x441041 |
| #define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC1 0x441042 |
| #define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC2 0x441043 |
| #define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_VC_ENH_CAP_LIST 0x441044 |
| #define regBIFPLR4_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_PORT_VC_CAP_REG1 0x441045 |
| #define regBIFPLR4_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_PORT_VC_CAP_REG2 0x441046 |
| #define regBIFPLR4_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_PORT_VC_CNTL 0x441047 |
| #define regBIFPLR4_1_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_PORT_VC_STATUS 0x441047 |
| #define regBIFPLR4_1_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_VC0_RESOURCE_CAP 0x441048 |
| #define regBIFPLR4_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_VC0_RESOURCE_CNTL 0x441049 |
| #define regBIFPLR4_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_VC0_RESOURCE_STATUS 0x44104a |
| #define regBIFPLR4_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_VC1_RESOURCE_CAP 0x44104b |
| #define regBIFPLR4_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_VC1_RESOURCE_CNTL 0x44104c |
| #define regBIFPLR4_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_VC1_RESOURCE_STATUS 0x44104d |
| #define regBIFPLR4_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x441050 |
| #define regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1 0x441051 |
| #define regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2 0x441052 |
| #define regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x441054 |
| #define regBIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_UNCORR_ERR_STATUS 0x441055 |
| #define regBIFPLR4_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_UNCORR_ERR_MASK 0x441056 |
| #define regBIFPLR4_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY 0x441057 |
| #define regBIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CORR_ERR_STATUS 0x441058 |
| #define regBIFPLR4_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CORR_ERR_MASK 0x441059 |
| #define regBIFPLR4_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL 0x44105a |
| #define regBIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_HDR_LOG0 0x44105b |
| #define regBIFPLR4_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_HDR_LOG1 0x44105c |
| #define regBIFPLR4_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_HDR_LOG2 0x44105d |
| #define regBIFPLR4_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_HDR_LOG3 0x44105e |
| #define regBIFPLR4_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ROOT_ERR_CMD 0x44105f |
| #define regBIFPLR4_1_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ROOT_ERR_STATUS 0x441060 |
| #define regBIFPLR4_1_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ERR_SRC_ID 0x441061 |
| #define regBIFPLR4_1_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG0 0x441062 |
| #define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG1 0x441063 |
| #define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG2 0x441064 |
| #define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG3 0x441065 |
| #define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST 0x44109c |
| #define regBIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LINK_CNTL3 0x44109d |
| #define regBIFPLR4_1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_ERROR_STATUS 0x44109e |
| #define regBIFPLR4_1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x44109f |
| #define regBIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x44109f |
| #define regBIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x4410a0 |
| #define regBIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x4410a0 |
| #define regBIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x4410a1 |
| #define regBIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x4410a1 |
| #define regBIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x4410a2 |
| #define regBIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x4410a2 |
| #define regBIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x4410a3 |
| #define regBIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x4410a3 |
| #define regBIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x4410a4 |
| #define regBIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x4410a4 |
| #define regBIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x4410a5 |
| #define regBIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x4410a5 |
| #define regBIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x4410a6 |
| #define regBIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x4410a6 |
| #define regBIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ACS_ENH_CAP_LIST 0x4410a8 |
| #define regBIFPLR4_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ACS_CAP 0x4410a9 |
| #define regBIFPLR4_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ACS_CNTL 0x4410a9 |
| #define regBIFPLR4_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_ENH_CAP_LIST 0x4410bc |
| #define regBIFPLR4_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_CAP 0x4410bd |
| #define regBIFPLR4_1_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_CNTL 0x4410bd |
| #define regBIFPLR4_1_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_ADDR0 0x4410be |
| #define regBIFPLR4_1_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_ADDR1 0x4410bf |
| #define regBIFPLR4_1_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_RCV0 0x4410c0 |
| #define regBIFPLR4_1_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_RCV1 0x4410c1 |
| #define regBIFPLR4_1_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_BLOCK_ALL0 0x4410c2 |
| #define regBIFPLR4_1_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_BLOCK_ALL1 0x4410c3 |
| #define regBIFPLR4_1_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x4410c4 |
| #define regBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x4410c5 |
| #define regBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_OVERLAY_BAR0 0x4410c6 |
| #define regBIFPLR4_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MC_OVERLAY_BAR1 0x4410c7 |
| #define regBIFPLR4_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST 0x4410dc |
| #define regBIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_L1_PM_SUB_CAP 0x4410dd |
| #define regBIFPLR4_1_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_L1_PM_SUB_CNTL 0x4410de |
| #define regBIFPLR4_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_L1_PM_SUB_CNTL2 0x4410df |
| #define regBIFPLR4_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_DPC_ENH_CAP_LIST 0x4410e0 |
| #define regBIFPLR4_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_DPC_CAP_LIST 0x4410e1 |
| #define regBIFPLR4_1_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_DPC_CNTL 0x4410e1 |
| #define regBIFPLR4_1_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_DPC_STATUS 0x4410e2 |
| #define regBIFPLR4_1_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID 0x4410e2 |
| #define regBIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_STATUS 0x4410e3 |
| #define regBIFPLR4_1_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_MASK 0x4410e4 |
| #define regBIFPLR4_1_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_SEVERITY 0x4410e5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_SYSERROR 0x4410e6 |
| #define regBIFPLR4_1_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_EXCEPTION 0x4410e7 |
| #define regBIFPLR4_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG0 0x4410e8 |
| #define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG1 0x4410e9 |
| #define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG2 0x4410ea |
| #define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG3 0x4410eb |
| #define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0 0x4410ed |
| #define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1 0x4410ee |
| #define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2 0x4410ef |
| #define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3 0x4410f0 |
| #define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_LIST 0x4410f1 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ESM_HEADER_1 0x4410f2 |
| #define regBIFPLR4_1_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ESM_HEADER_2 0x4410f3 |
| #define regBIFPLR4_1_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ESM_STATUS 0x4410f3 |
| #define regBIFPLR4_1_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ESM_CTRL 0x4410f4 |
| #define regBIFPLR4_1_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_1 0x4410f5 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_2 0x4410f6 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_3 0x4410f7 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_4 0x4410f8 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_5 0x4410f9 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_6 0x4410fa |
| #define regBIFPLR4_1_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_ESM_CAP_7 0x4410fb |
| #define regBIFPLR4_1_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_DLF_ENH_CAP_LIST 0x441100 |
| #define regBIFPLR4_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_DATA_LINK_FEATURE_CAP 0x441101 |
| #define regBIFPLR4_1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_DATA_LINK_FEATURE_STATUS 0x441102 |
| #define regBIFPLR4_1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x441104 |
| #define regBIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_LINK_CAP_16GT 0x441105 |
| #define regBIFPLR4_1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LINK_CNTL_16GT 0x441106 |
| #define regBIFPLR4_1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LINK_STATUS_16GT 0x441107 |
| #define regBIFPLR4_1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x441108 |
| #define regBIFPLR4_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x441109 |
| #define regBIFPLR4_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x44110a |
| #define regBIFPLR4_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT 0x44110c |
| #define regBIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT 0x44110c |
| #define regBIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT 0x44110c |
| #define regBIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT 0x44110c |
| #define regBIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT 0x44110d |
| #define regBIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT 0x44110d |
| #define regBIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT 0x44110d |
| #define regBIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT 0x44110d |
| #define regBIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT 0x44110e |
| #define regBIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT 0x44110e |
| #define regBIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT 0x44110e |
| #define regBIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT 0x44110e |
| #define regBIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT 0x44110f |
| #define regBIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT 0x44110f |
| #define regBIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT 0x44110f |
| #define regBIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT 0x44110f |
| #define regBIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST 0x441110 |
| #define regBIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_MARGINING_PORT_CAP 0x441111 |
| #define regBIFPLR4_1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_MARGINING_PORT_STATUS 0x441111 |
| #define regBIFPLR4_1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_0_MARGINING_LANE_CNTL 0x441112 |
| #define regBIFPLR4_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_0_MARGINING_LANE_STATUS 0x441112 |
| #define regBIFPLR4_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_1_MARGINING_LANE_CNTL 0x441113 |
| #define regBIFPLR4_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_1_MARGINING_LANE_STATUS 0x441113 |
| #define regBIFPLR4_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_2_MARGINING_LANE_CNTL 0x441114 |
| #define regBIFPLR4_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_2_MARGINING_LANE_STATUS 0x441114 |
| #define regBIFPLR4_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_3_MARGINING_LANE_CNTL 0x441115 |
| #define regBIFPLR4_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_3_MARGINING_LANE_STATUS 0x441115 |
| #define regBIFPLR4_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_4_MARGINING_LANE_CNTL 0x441116 |
| #define regBIFPLR4_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_4_MARGINING_LANE_STATUS 0x441116 |
| #define regBIFPLR4_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_5_MARGINING_LANE_CNTL 0x441117 |
| #define regBIFPLR4_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_5_MARGINING_LANE_STATUS 0x441117 |
| #define regBIFPLR4_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_6_MARGINING_LANE_CNTL 0x441118 |
| #define regBIFPLR4_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_6_MARGINING_LANE_STATUS 0x441118 |
| #define regBIFPLR4_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_7_MARGINING_LANE_CNTL 0x441119 |
| #define regBIFPLR4_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_7_MARGINING_LANE_STATUS 0x441119 |
| #define regBIFPLR4_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_8_MARGINING_LANE_CNTL 0x44111a |
| #define regBIFPLR4_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_8_MARGINING_LANE_STATUS 0x44111a |
| #define regBIFPLR4_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_9_MARGINING_LANE_CNTL 0x44111b |
| #define regBIFPLR4_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_9_MARGINING_LANE_STATUS 0x44111b |
| #define regBIFPLR4_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_10_MARGINING_LANE_CNTL 0x44111c |
| #define regBIFPLR4_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_10_MARGINING_LANE_STATUS 0x44111c |
| #define regBIFPLR4_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_11_MARGINING_LANE_CNTL 0x44111d |
| #define regBIFPLR4_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_11_MARGINING_LANE_STATUS 0x44111d |
| #define regBIFPLR4_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_12_MARGINING_LANE_CNTL 0x44111e |
| #define regBIFPLR4_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_12_MARGINING_LANE_STATUS 0x44111e |
| #define regBIFPLR4_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_13_MARGINING_LANE_CNTL 0x44111f |
| #define regBIFPLR4_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_13_MARGINING_LANE_STATUS 0x44111f |
| #define regBIFPLR4_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_14_MARGINING_LANE_CNTL 0x441120 |
| #define regBIFPLR4_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_14_MARGINING_LANE_STATUS 0x441120 |
| #define regBIFPLR4_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_15_MARGINING_LANE_CNTL 0x441121 |
| #define regBIFPLR4_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LANE_15_MARGINING_LANE_STATUS 0x441121 |
| #define regBIFPLR4_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CCIX_CAP_LIST 0x441122 |
| #define regBIFPLR4_1_PCIE_CCIX_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CCIX_HEADER_1 0x441123 |
| #define regBIFPLR4_1_PCIE_CCIX_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CCIX_HEADER_2 0x441124 |
| #define regBIFPLR4_1_PCIE_CCIX_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CCIX_CAP 0x441124 |
| #define regBIFPLR4_1_PCIE_CCIX_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP 0x441125 |
| #define regBIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CCIX_ESM_OPTL_CAP 0x441126 |
| #define regBIFPLR4_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CCIX_ESM_STATUS 0x441127 |
| #define regBIFPLR4_1_PCIE_CCIX_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CCIX_ESM_CNTL 0x441128 |
| #define regBIFPLR4_1_PCIE_CCIX_ESM_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x441129 |
| #define regBIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x441129 |
| #define regBIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x441129 |
| #define regBIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x441129 |
| #define regBIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x44112a |
| #define regBIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x44112a |
| #define regBIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x44112a |
| #define regBIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x44112a |
| #define regBIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x44112b |
| #define regBIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x44112b |
| #define regBIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x44112b |
| #define regBIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x44112b |
| #define regBIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x44112c |
| #define regBIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x44112c |
| #define regBIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x44112c |
| #define regBIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x44112c |
| #define regBIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x44112d |
| #define regBIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x44112d |
| #define regBIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x44112d |
| #define regBIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x44112d |
| #define regBIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x44112e |
| #define regBIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x44112e |
| #define regBIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x44112e |
| #define regBIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x44112e |
| #define regBIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x44112f |
| #define regBIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x44112f |
| #define regBIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x44112f |
| #define regBIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x44112f |
| #define regBIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x441130 |
| #define regBIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x441130 |
| #define regBIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x441130 |
| #define regBIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x441130 |
| #define regBIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CCIX_TRANS_CAP 0x441131 |
| #define regBIFPLR4_1_PCIE_CCIX_TRANS_CAP_BASE_IDX 5 |
| #define regBIFPLR4_1_PCIE_CCIX_TRANS_CNTL 0x441132 |
| #define regBIFPLR4_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_1_LINK_CAP_32GT 0x441141 |
| #define regBIFPLR4_1_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LINK_CNTL_32GT 0x441142 |
| #define regBIFPLR4_1_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR4_1_LINK_STATUS_32GT 0x441143 |
| #define regBIFPLR4_1_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifplr5_cfgdecp |
| // base address: 0x11205000 |
| #define regBIFPLR5_0_VENDOR_ID 0x441400 |
| #define regBIFPLR5_0_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR5_0_DEVICE_ID 0x441400 |
| #define regBIFPLR5_0_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR5_0_COMMAND 0x441401 |
| #define regBIFPLR5_0_COMMAND_BASE_IDX 5 |
| #define regBIFPLR5_0_STATUS 0x441401 |
| #define regBIFPLR5_0_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_REVISION_ID 0x441402 |
| #define regBIFPLR5_0_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR5_0_PROG_INTERFACE 0x441402 |
| #define regBIFPLR5_0_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR5_0_SUB_CLASS 0x441402 |
| #define regBIFPLR5_0_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR5_0_BASE_CLASS 0x441402 |
| #define regBIFPLR5_0_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR5_0_CACHE_LINE 0x441403 |
| #define regBIFPLR5_0_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR5_0_LATENCY 0x441403 |
| #define regBIFPLR5_0_LATENCY_BASE_IDX 5 |
| #define regBIFPLR5_0_HEADER 0x441403 |
| #define regBIFPLR5_0_HEADER_BASE_IDX 5 |
| #define regBIFPLR5_0_BIST 0x441403 |
| #define regBIFPLR5_0_BIST_BASE_IDX 5 |
| #define regBIFPLR5_0_SUB_BUS_NUMBER_LATENCY 0x441406 |
| #define regBIFPLR5_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR5_0_IO_BASE_LIMIT 0x441407 |
| #define regBIFPLR5_0_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR5_0_SECONDARY_STATUS 0x441407 |
| #define regBIFPLR5_0_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_MEM_BASE_LIMIT 0x441408 |
| #define regBIFPLR5_0_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR5_0_PREF_BASE_LIMIT 0x441409 |
| #define regBIFPLR5_0_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR5_0_PREF_BASE_UPPER 0x44140a |
| #define regBIFPLR5_0_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR5_0_PREF_LIMIT_UPPER 0x44140b |
| #define regBIFPLR5_0_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR5_0_IO_BASE_LIMIT_HI 0x44140c |
| #define regBIFPLR5_0_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR5_0_CAP_PTR 0x44140d |
| #define regBIFPLR5_0_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR5_0_ROM_BASE_ADDR 0x44140e |
| #define regBIFPLR5_0_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIFPLR5_0_INTERRUPT_LINE 0x44140f |
| #define regBIFPLR5_0_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR5_0_INTERRUPT_PIN 0x44140f |
| #define regBIFPLR5_0_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR5_0_EXT_BRIDGE_CNTL 0x441410 |
| #define regBIFPLR5_0_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_VENDOR_CAP_LIST 0x441412 |
| #define regBIFPLR5_0_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_ADAPTER_ID_W 0x441413 |
| #define regBIFPLR5_0_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIFPLR5_0_PMI_CAP_LIST 0x441414 |
| #define regBIFPLR5_0_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PMI_CAP 0x441414 |
| #define regBIFPLR5_0_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_PMI_STATUS_CNTL 0x441415 |
| #define regBIFPLR5_0_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CAP_LIST 0x441416 |
| #define regBIFPLR5_0_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CAP 0x441416 |
| #define regBIFPLR5_0_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_DEVICE_CAP 0x441417 |
| #define regBIFPLR5_0_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_DEVICE_CNTL 0x441418 |
| #define regBIFPLR5_0_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_DEVICE_STATUS 0x441418 |
| #define regBIFPLR5_0_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LINK_CAP 0x441419 |
| #define regBIFPLR5_0_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_LINK_CNTL 0x44141a |
| #define regBIFPLR5_0_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LINK_STATUS 0x44141a |
| #define regBIFPLR5_0_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_SLOT_CAP 0x44141b |
| #define regBIFPLR5_0_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_SLOT_CNTL 0x44141c |
| #define regBIFPLR5_0_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_SLOT_STATUS 0x44141c |
| #define regBIFPLR5_0_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_ROOT_CNTL 0x44141d |
| #define regBIFPLR5_0_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_ROOT_CAP 0x44141d |
| #define regBIFPLR5_0_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_ROOT_STATUS 0x44141e |
| #define regBIFPLR5_0_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_DEVICE_CAP2 0x44141f |
| #define regBIFPLR5_0_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR5_0_DEVICE_CNTL2 0x441420 |
| #define regBIFPLR5_0_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR5_0_DEVICE_STATUS2 0x441420 |
| #define regBIFPLR5_0_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR5_0_LINK_CAP2 0x441421 |
| #define regBIFPLR5_0_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR5_0_LINK_CNTL2 0x441422 |
| #define regBIFPLR5_0_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR5_0_LINK_STATUS2 0x441422 |
| #define regBIFPLR5_0_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR5_0_SLOT_CAP2 0x441423 |
| #define regBIFPLR5_0_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR5_0_SLOT_CNTL2 0x441424 |
| #define regBIFPLR5_0_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR5_0_SLOT_STATUS2 0x441424 |
| #define regBIFPLR5_0_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR5_0_MSI_CAP_LIST 0x441428 |
| #define regBIFPLR5_0_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_MSI_MSG_CNTL 0x441428 |
| #define regBIFPLR5_0_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_MSI_MSG_ADDR_LO 0x441429 |
| #define regBIFPLR5_0_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR5_0_MSI_MSG_ADDR_HI 0x44142a |
| #define regBIFPLR5_0_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR5_0_MSI_MSG_DATA 0x44142a |
| #define regBIFPLR5_0_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR5_0_MSI_MSG_DATA_64 0x44142b |
| #define regBIFPLR5_0_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR5_0_SSID_CAP_LIST 0x441430 |
| #define regBIFPLR5_0_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_SSID_CAP 0x441431 |
| #define regBIFPLR5_0_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_MSI_MAP_CAP_LIST 0x441432 |
| #define regBIFPLR5_0_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_MSI_MAP_CAP 0x441432 |
| #define regBIFPLR5_0_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x441440 |
| #define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR 0x441441 |
| #define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC1 0x441442 |
| #define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC2 0x441443 |
| #define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_VC_ENH_CAP_LIST 0x441444 |
| #define regBIFPLR5_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_PORT_VC_CAP_REG1 0x441445 |
| #define regBIFPLR5_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_PORT_VC_CAP_REG2 0x441446 |
| #define regBIFPLR5_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_PORT_VC_CNTL 0x441447 |
| #define regBIFPLR5_0_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_PORT_VC_STATUS 0x441447 |
| #define regBIFPLR5_0_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_VC0_RESOURCE_CAP 0x441448 |
| #define regBIFPLR5_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_VC0_RESOURCE_CNTL 0x441449 |
| #define regBIFPLR5_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_VC0_RESOURCE_STATUS 0x44144a |
| #define regBIFPLR5_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_VC1_RESOURCE_CAP 0x44144b |
| #define regBIFPLR5_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_VC1_RESOURCE_CNTL 0x44144c |
| #define regBIFPLR5_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_VC1_RESOURCE_STATUS 0x44144d |
| #define regBIFPLR5_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x441450 |
| #define regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1 0x441451 |
| #define regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2 0x441452 |
| #define regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x441454 |
| #define regBIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_UNCORR_ERR_STATUS 0x441455 |
| #define regBIFPLR5_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_UNCORR_ERR_MASK 0x441456 |
| #define regBIFPLR5_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY 0x441457 |
| #define regBIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CORR_ERR_STATUS 0x441458 |
| #define regBIFPLR5_0_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CORR_ERR_MASK 0x441459 |
| #define regBIFPLR5_0_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL 0x44145a |
| #define regBIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_HDR_LOG0 0x44145b |
| #define regBIFPLR5_0_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_HDR_LOG1 0x44145c |
| #define regBIFPLR5_0_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_HDR_LOG2 0x44145d |
| #define regBIFPLR5_0_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_HDR_LOG3 0x44145e |
| #define regBIFPLR5_0_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ROOT_ERR_CMD 0x44145f |
| #define regBIFPLR5_0_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ROOT_ERR_STATUS 0x441460 |
| #define regBIFPLR5_0_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ERR_SRC_ID 0x441461 |
| #define regBIFPLR5_0_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG0 0x441462 |
| #define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG1 0x441463 |
| #define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG2 0x441464 |
| #define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG3 0x441465 |
| #define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST 0x44149c |
| #define regBIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LINK_CNTL3 0x44149d |
| #define regBIFPLR5_0_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_ERROR_STATUS 0x44149e |
| #define regBIFPLR5_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x44149f |
| #define regBIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x44149f |
| #define regBIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x4414a0 |
| #define regBIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x4414a0 |
| #define regBIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x4414a1 |
| #define regBIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x4414a1 |
| #define regBIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x4414a2 |
| #define regBIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x4414a2 |
| #define regBIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x4414a3 |
| #define regBIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x4414a3 |
| #define regBIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x4414a4 |
| #define regBIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x4414a4 |
| #define regBIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x4414a5 |
| #define regBIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x4414a5 |
| #define regBIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x4414a6 |
| #define regBIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x4414a6 |
| #define regBIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ACS_ENH_CAP_LIST 0x4414a8 |
| #define regBIFPLR5_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ACS_CAP 0x4414a9 |
| #define regBIFPLR5_0_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ACS_CNTL 0x4414a9 |
| #define regBIFPLR5_0_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_ENH_CAP_LIST 0x4414bc |
| #define regBIFPLR5_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_CAP 0x4414bd |
| #define regBIFPLR5_0_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_CNTL 0x4414bd |
| #define regBIFPLR5_0_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_ADDR0 0x4414be |
| #define regBIFPLR5_0_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_ADDR1 0x4414bf |
| #define regBIFPLR5_0_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_RCV0 0x4414c0 |
| #define regBIFPLR5_0_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_RCV1 0x4414c1 |
| #define regBIFPLR5_0_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_BLOCK_ALL0 0x4414c2 |
| #define regBIFPLR5_0_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_BLOCK_ALL1 0x4414c3 |
| #define regBIFPLR5_0_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x4414c4 |
| #define regBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x4414c5 |
| #define regBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_OVERLAY_BAR0 0x4414c6 |
| #define regBIFPLR5_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MC_OVERLAY_BAR1 0x4414c7 |
| #define regBIFPLR5_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST 0x4414dc |
| #define regBIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_L1_PM_SUB_CAP 0x4414dd |
| #define regBIFPLR5_0_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_L1_PM_SUB_CNTL 0x4414de |
| #define regBIFPLR5_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_L1_PM_SUB_CNTL2 0x4414df |
| #define regBIFPLR5_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_DPC_ENH_CAP_LIST 0x4414e0 |
| #define regBIFPLR5_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_DPC_CAP_LIST 0x4414e1 |
| #define regBIFPLR5_0_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_DPC_CNTL 0x4414e1 |
| #define regBIFPLR5_0_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_DPC_STATUS 0x4414e2 |
| #define regBIFPLR5_0_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID 0x4414e2 |
| #define regBIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_STATUS 0x4414e3 |
| #define regBIFPLR5_0_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_MASK 0x4414e4 |
| #define regBIFPLR5_0_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_SEVERITY 0x4414e5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_SYSERROR 0x4414e6 |
| #define regBIFPLR5_0_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_EXCEPTION 0x4414e7 |
| #define regBIFPLR5_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG0 0x4414e8 |
| #define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG1 0x4414e9 |
| #define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG2 0x4414ea |
| #define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG3 0x4414eb |
| #define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0 0x4414ed |
| #define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1 0x4414ee |
| #define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2 0x4414ef |
| #define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3 0x4414f0 |
| #define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_LIST 0x4414f1 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ESM_HEADER_1 0x4414f2 |
| #define regBIFPLR5_0_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ESM_HEADER_2 0x4414f3 |
| #define regBIFPLR5_0_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ESM_STATUS 0x4414f3 |
| #define regBIFPLR5_0_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ESM_CTRL 0x4414f4 |
| #define regBIFPLR5_0_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_1 0x4414f5 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_2 0x4414f6 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_3 0x4414f7 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_4 0x4414f8 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_5 0x4414f9 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_6 0x4414fa |
| #define regBIFPLR5_0_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_ESM_CAP_7 0x4414fb |
| #define regBIFPLR5_0_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_DLF_ENH_CAP_LIST 0x441500 |
| #define regBIFPLR5_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_DATA_LINK_FEATURE_CAP 0x441501 |
| #define regBIFPLR5_0_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_DATA_LINK_FEATURE_STATUS 0x441502 |
| #define regBIFPLR5_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x441504 |
| #define regBIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_LINK_CAP_16GT 0x441505 |
| #define regBIFPLR5_0_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LINK_CNTL_16GT 0x441506 |
| #define regBIFPLR5_0_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LINK_STATUS_16GT 0x441507 |
| #define regBIFPLR5_0_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x441508 |
| #define regBIFPLR5_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x441509 |
| #define regBIFPLR5_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x44150a |
| #define regBIFPLR5_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT 0x44150c |
| #define regBIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT 0x44150c |
| #define regBIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT 0x44150c |
| #define regBIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT 0x44150c |
| #define regBIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT 0x44150d |
| #define regBIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT 0x44150d |
| #define regBIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT 0x44150d |
| #define regBIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT 0x44150d |
| #define regBIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT 0x44150e |
| #define regBIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT 0x44150e |
| #define regBIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT 0x44150e |
| #define regBIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT 0x44150e |
| #define regBIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT 0x44150f |
| #define regBIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT 0x44150f |
| #define regBIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT 0x44150f |
| #define regBIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT 0x44150f |
| #define regBIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST 0x441510 |
| #define regBIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_MARGINING_PORT_CAP 0x441511 |
| #define regBIFPLR5_0_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_MARGINING_PORT_STATUS 0x441511 |
| #define regBIFPLR5_0_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_0_MARGINING_LANE_CNTL 0x441512 |
| #define regBIFPLR5_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_0_MARGINING_LANE_STATUS 0x441512 |
| #define regBIFPLR5_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_1_MARGINING_LANE_CNTL 0x441513 |
| #define regBIFPLR5_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_1_MARGINING_LANE_STATUS 0x441513 |
| #define regBIFPLR5_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_2_MARGINING_LANE_CNTL 0x441514 |
| #define regBIFPLR5_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_2_MARGINING_LANE_STATUS 0x441514 |
| #define regBIFPLR5_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_3_MARGINING_LANE_CNTL 0x441515 |
| #define regBIFPLR5_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_3_MARGINING_LANE_STATUS 0x441515 |
| #define regBIFPLR5_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_4_MARGINING_LANE_CNTL 0x441516 |
| #define regBIFPLR5_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_4_MARGINING_LANE_STATUS 0x441516 |
| #define regBIFPLR5_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_5_MARGINING_LANE_CNTL 0x441517 |
| #define regBIFPLR5_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_5_MARGINING_LANE_STATUS 0x441517 |
| #define regBIFPLR5_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_6_MARGINING_LANE_CNTL 0x441518 |
| #define regBIFPLR5_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_6_MARGINING_LANE_STATUS 0x441518 |
| #define regBIFPLR5_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_7_MARGINING_LANE_CNTL 0x441519 |
| #define regBIFPLR5_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_7_MARGINING_LANE_STATUS 0x441519 |
| #define regBIFPLR5_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_8_MARGINING_LANE_CNTL 0x44151a |
| #define regBIFPLR5_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_8_MARGINING_LANE_STATUS 0x44151a |
| #define regBIFPLR5_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_9_MARGINING_LANE_CNTL 0x44151b |
| #define regBIFPLR5_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_9_MARGINING_LANE_STATUS 0x44151b |
| #define regBIFPLR5_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_10_MARGINING_LANE_CNTL 0x44151c |
| #define regBIFPLR5_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_10_MARGINING_LANE_STATUS 0x44151c |
| #define regBIFPLR5_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_11_MARGINING_LANE_CNTL 0x44151d |
| #define regBIFPLR5_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_11_MARGINING_LANE_STATUS 0x44151d |
| #define regBIFPLR5_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_12_MARGINING_LANE_CNTL 0x44151e |
| #define regBIFPLR5_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_12_MARGINING_LANE_STATUS 0x44151e |
| #define regBIFPLR5_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_13_MARGINING_LANE_CNTL 0x44151f |
| #define regBIFPLR5_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_13_MARGINING_LANE_STATUS 0x44151f |
| #define regBIFPLR5_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_14_MARGINING_LANE_CNTL 0x441520 |
| #define regBIFPLR5_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_14_MARGINING_LANE_STATUS 0x441520 |
| #define regBIFPLR5_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_15_MARGINING_LANE_CNTL 0x441521 |
| #define regBIFPLR5_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LANE_15_MARGINING_LANE_STATUS 0x441521 |
| #define regBIFPLR5_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CCIX_CAP_LIST 0x441522 |
| #define regBIFPLR5_0_PCIE_CCIX_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CCIX_HEADER_1 0x441523 |
| #define regBIFPLR5_0_PCIE_CCIX_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CCIX_HEADER_2 0x441524 |
| #define regBIFPLR5_0_PCIE_CCIX_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CCIX_CAP 0x441524 |
| #define regBIFPLR5_0_PCIE_CCIX_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP 0x441525 |
| #define regBIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CCIX_ESM_OPTL_CAP 0x441526 |
| #define regBIFPLR5_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CCIX_ESM_STATUS 0x441527 |
| #define regBIFPLR5_0_PCIE_CCIX_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CCIX_ESM_CNTL 0x441528 |
| #define regBIFPLR5_0_PCIE_CCIX_ESM_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x441529 |
| #define regBIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x441529 |
| #define regBIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x441529 |
| #define regBIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x441529 |
| #define regBIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x44152a |
| #define regBIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x44152a |
| #define regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x44152a |
| #define regBIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x44152a |
| #define regBIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x44152b |
| #define regBIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x44152b |
| #define regBIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x44152b |
| #define regBIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x44152b |
| #define regBIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x44152c |
| #define regBIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x44152c |
| #define regBIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x44152c |
| #define regBIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x44152c |
| #define regBIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x44152d |
| #define regBIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x44152d |
| #define regBIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x44152d |
| #define regBIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x44152d |
| #define regBIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x44152e |
| #define regBIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x44152e |
| #define regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x44152e |
| #define regBIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x44152e |
| #define regBIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x44152f |
| #define regBIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x44152f |
| #define regBIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x44152f |
| #define regBIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x44152f |
| #define regBIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x441530 |
| #define regBIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x441530 |
| #define regBIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x441530 |
| #define regBIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x441530 |
| #define regBIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CCIX_TRANS_CAP 0x441531 |
| #define regBIFPLR5_0_PCIE_CCIX_TRANS_CAP_BASE_IDX 5 |
| #define regBIFPLR5_0_PCIE_CCIX_TRANS_CNTL 0x441532 |
| #define regBIFPLR5_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_0_LINK_CAP_32GT 0x441541 |
| #define regBIFPLR5_0_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LINK_CNTL_32GT 0x441542 |
| #define regBIFPLR5_0_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR5_0_LINK_STATUS_32GT 0x441543 |
| #define regBIFPLR5_0_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifp0_pciedir_p |
| // base address: 0x11240000 |
| #define regBIFP0_1_PCIEP_RESERVED 0x450000 |
| #define regBIFP0_1_PCIEP_RESERVED_BASE_IDX 5 |
| #define regBIFP0_1_PCIEP_SCRATCH 0x450001 |
| #define regBIFP0_1_PCIEP_SCRATCH_BASE_IDX 5 |
| #define regBIFP0_1_PCIEP_PORT_CNTL 0x450010 |
| #define regBIFP0_1_PCIEP_PORT_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_REQUESTER_ID 0x450021 |
| #define regBIFP0_1_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_P_PORT_LANE_STATUS 0x450050 |
| #define regBIFP0_1_PCIE_P_PORT_LANE_STATUS_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_ERR_CNTL 0x45006a |
| #define regBIFP0_1_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_RX_CNTL 0x450070 |
| #define regBIFP0_1_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_RX_EXPECTED_SEQNUM 0x450071 |
| #define regBIFP0_1_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_RX_VENDOR_SPECIFIC 0x450072 |
| #define regBIFP0_1_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_RX_CNTL3 0x450074 |
| #define regBIFP0_1_PCIE_RX_CNTL3_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_RX_CREDITS_ALLOCATED_P 0x450080 |
| #define regBIFP0_1_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_RX_CREDITS_ALLOCATED_NP 0x450081 |
| #define regBIFP0_1_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x450082 |
| #define regBIFP0_1_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 |
| #define regBIFP0_1_PCIEP_ERROR_INJECT_PHYSICAL 0x450083 |
| #define regBIFP0_1_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 |
| #define regBIFP0_1_PCIEP_ERROR_INJECT_TRANSACTION 0x450084 |
| #define regBIFP0_1_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 |
| #define regBIFP0_1_PCIEP_NAK_COUNTER 0x450086 |
| #define regBIFP0_1_PCIEP_NAK_COUNTER_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CNTL 0x4500a0 |
| #define regBIFP0_1_PCIE_LC_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_TRAINING_CNTL 0x4500a1 |
| #define regBIFP0_1_PCIE_LC_TRAINING_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_LINK_WIDTH_CNTL 0x4500a2 |
| #define regBIFP0_1_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_N_FTS_CNTL 0x4500a3 |
| #define regBIFP0_1_PCIE_LC_N_FTS_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_SPEED_CNTL 0x4500a4 |
| #define regBIFP0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_STATE0 0x4500a5 |
| #define regBIFP0_1_PCIE_LC_STATE0_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_STATE1 0x4500a6 |
| #define regBIFP0_1_PCIE_LC_STATE1_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_STATE2 0x4500a7 |
| #define regBIFP0_1_PCIE_LC_STATE2_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_STATE3 0x4500a8 |
| #define regBIFP0_1_PCIE_LC_STATE3_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_STATE4 0x4500a9 |
| #define regBIFP0_1_PCIE_LC_STATE4_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_STATE5 0x4500aa |
| #define regBIFP0_1_PCIE_LC_STATE5_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CNTL2 0x4500b1 |
| #define regBIFP0_1_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_BW_CHANGE_CNTL 0x4500b2 |
| #define regBIFP0_1_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CDR_CNTL 0x4500b3 |
| #define regBIFP0_1_PCIE_LC_CDR_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_LANE_CNTL 0x4500b4 |
| #define regBIFP0_1_PCIE_LC_LANE_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CNTL3 0x4500b5 |
| #define regBIFP0_1_PCIE_LC_CNTL3_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CNTL4 0x4500b6 |
| #define regBIFP0_1_PCIE_LC_CNTL4_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CNTL5 0x4500b7 |
| #define regBIFP0_1_PCIE_LC_CNTL5_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_FORCE_COEFF 0x4500b8 |
| #define regBIFP0_1_PCIE_LC_FORCE_COEFF_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_BEST_EQ_SETTINGS 0x4500b9 |
| #define regBIFP0_1_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_FORCE_EQ_REQ_COEFF 0x4500ba |
| #define regBIFP0_1_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CNTL6 0x4500bb |
| #define regBIFP0_1_PCIE_LC_CNTL6_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CNTL7 0x4500bc |
| #define regBIFP0_1_PCIE_LC_CNTL7_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_LINK_MANAGEMENT_MASK 0x4500be |
| #define regBIFP0_1_PCIE_LC_LINK_MANAGEMENT_MASK_BASE_IDX 5 |
| #define regBIFP0_1_PCIEP_STRAP_LC 0x4500c0 |
| #define regBIFP0_1_PCIEP_STRAP_LC_BASE_IDX 5 |
| #define regBIFP0_1_PCIEP_STRAP_MISC 0x4500c1 |
| #define regBIFP0_1_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regBIFP0_1_PCIEP_STRAP_LC2 0x4500c2 |
| #define regBIFP0_1_PCIEP_STRAP_LC2_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_L1_PM_SUBSTATE 0x4500c6 |
| #define regBIFP0_1_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_L1_PM_SUBSTATE2 0x4500c7 |
| #define regBIFP0_1_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_L1_PM_SUBSTATE3 0x4500c8 |
| #define regBIFP0_1_PCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_L1_PM_SUBSTATE4 0x4500c9 |
| #define regBIFP0_1_PCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_L1_PM_SUBSTATE5 0x4500ca |
| #define regBIFP0_1_PCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 |
| #define regBIFP0_1_PCIEP_BCH_ECC_CNTL 0x4500d0 |
| #define regBIFP0_1_PCIEP_BCH_ECC_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CNTL8 0x4500dd |
| #define regBIFP0_1_PCIE_LC_CNTL8_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CNTL9 0x4500de |
| #define regBIFP0_1_PCIE_LC_CNTL9_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_FORCE_COEFF2 0x4500df |
| #define regBIFP0_1_PCIE_LC_FORCE_COEFF2_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_FORCE_EQ_REQ_COEFF2 0x4500e0 |
| #define regBIFP0_1_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x4500e2 |
| #define regBIFP0_1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CNTL10 0x4500e3 |
| #define regBIFP0_1_PCIE_LC_CNTL10_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_SAVE_RESTORE_1 0x4500e6 |
| #define regBIFP0_1_PCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_SAVE_RESTORE_2 0x4500e7 |
| #define regBIFP0_1_PCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CNTL11 0x450103 |
| #define regBIFP0_1_PCIE_LC_CNTL11_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_CNTL12 0x450104 |
| #define regBIFP0_1_PCIE_LC_CNTL12_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_SPEED_CNTL2 0x450105 |
| #define regBIFP0_1_PCIE_LC_SPEED_CNTL2_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_FORCE_COEFF3 0x450106 |
| #define regBIFP0_1_PCIE_LC_FORCE_COEFF3_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_LC_FORCE_EQ_REQ_COEFF3 0x450107 |
| #define regBIFP0_1_PCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_SEQ 0x450188 |
| #define regBIFP0_1_PCIE_TX_SEQ_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_REPLAY 0x450189 |
| #define regBIFP0_1_PCIE_TX_REPLAY_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_ACK_LATENCY_LIMIT 0x45018c |
| #define regBIFP0_1_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x450190 |
| #define regBIFP0_1_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_VENDOR_SPECIFIC 0x450194 |
| #define regBIFP0_1_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_NOP_DLLP 0x450195 |
| #define regBIFP0_1_PCIE_TX_NOP_DLLP_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_REQUEST_NUM_CNTL 0x450198 |
| #define regBIFP0_1_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_CREDITS_ADVT_P 0x4501a0 |
| #define regBIFP0_1_PCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_CREDITS_ADVT_NP 0x4501a1 |
| #define regBIFP0_1_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_CREDITS_ADVT_CPL 0x4501a2 |
| #define regBIFP0_1_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_CREDITS_INIT_P 0x4501a3 |
| #define regBIFP0_1_PCIE_TX_CREDITS_INIT_P_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_CREDITS_INIT_NP 0x4501a4 |
| #define regBIFP0_1_PCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_CREDITS_INIT_CPL 0x4501a5 |
| #define regBIFP0_1_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_TX_CREDITS_STATUS 0x4501a6 |
| #define regBIFP0_1_PCIE_TX_CREDITS_STATUS_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_FC_P 0x4501a8 |
| #define regBIFP0_1_PCIE_FC_P_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_FC_NP 0x4501a9 |
| #define regBIFP0_1_PCIE_FC_NP_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_FC_CPL 0x4501aa |
| #define regBIFP0_1_PCIE_FC_CPL_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_FC_P_VC1 0x4501ab |
| #define regBIFP0_1_PCIE_FC_P_VC1_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_FC_NP_VC1 0x4501ac |
| #define regBIFP0_1_PCIE_FC_NP_VC1_BASE_IDX 5 |
| #define regBIFP0_1_PCIE_FC_CPL_VC1 0x4501ad |
| #define regBIFP0_1_PCIE_FC_CPL_VC1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifp1_pciedir_p |
| // base address: 0x11241000 |
| #define regBIFP1_1_PCIEP_RESERVED 0x450400 |
| #define regBIFP1_1_PCIEP_RESERVED_BASE_IDX 5 |
| #define regBIFP1_1_PCIEP_SCRATCH 0x450401 |
| #define regBIFP1_1_PCIEP_SCRATCH_BASE_IDX 5 |
| #define regBIFP1_1_PCIEP_PORT_CNTL 0x450410 |
| #define regBIFP1_1_PCIEP_PORT_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_REQUESTER_ID 0x450421 |
| #define regBIFP1_1_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_P_PORT_LANE_STATUS 0x450450 |
| #define regBIFP1_1_PCIE_P_PORT_LANE_STATUS_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_ERR_CNTL 0x45046a |
| #define regBIFP1_1_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_RX_CNTL 0x450470 |
| #define regBIFP1_1_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_RX_EXPECTED_SEQNUM 0x450471 |
| #define regBIFP1_1_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_RX_VENDOR_SPECIFIC 0x450472 |
| #define regBIFP1_1_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_RX_CNTL3 0x450474 |
| #define regBIFP1_1_PCIE_RX_CNTL3_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_RX_CREDITS_ALLOCATED_P 0x450480 |
| #define regBIFP1_1_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_RX_CREDITS_ALLOCATED_NP 0x450481 |
| #define regBIFP1_1_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x450482 |
| #define regBIFP1_1_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 |
| #define regBIFP1_1_PCIEP_ERROR_INJECT_PHYSICAL 0x450483 |
| #define regBIFP1_1_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 |
| #define regBIFP1_1_PCIEP_ERROR_INJECT_TRANSACTION 0x450484 |
| #define regBIFP1_1_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 |
| #define regBIFP1_1_PCIEP_NAK_COUNTER 0x450486 |
| #define regBIFP1_1_PCIEP_NAK_COUNTER_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CNTL 0x4504a0 |
| #define regBIFP1_1_PCIE_LC_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_TRAINING_CNTL 0x4504a1 |
| #define regBIFP1_1_PCIE_LC_TRAINING_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_LINK_WIDTH_CNTL 0x4504a2 |
| #define regBIFP1_1_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_N_FTS_CNTL 0x4504a3 |
| #define regBIFP1_1_PCIE_LC_N_FTS_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_SPEED_CNTL 0x4504a4 |
| #define regBIFP1_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_STATE0 0x4504a5 |
| #define regBIFP1_1_PCIE_LC_STATE0_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_STATE1 0x4504a6 |
| #define regBIFP1_1_PCIE_LC_STATE1_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_STATE2 0x4504a7 |
| #define regBIFP1_1_PCIE_LC_STATE2_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_STATE3 0x4504a8 |
| #define regBIFP1_1_PCIE_LC_STATE3_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_STATE4 0x4504a9 |
| #define regBIFP1_1_PCIE_LC_STATE4_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_STATE5 0x4504aa |
| #define regBIFP1_1_PCIE_LC_STATE5_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CNTL2 0x4504b1 |
| #define regBIFP1_1_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_BW_CHANGE_CNTL 0x4504b2 |
| #define regBIFP1_1_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CDR_CNTL 0x4504b3 |
| #define regBIFP1_1_PCIE_LC_CDR_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_LANE_CNTL 0x4504b4 |
| #define regBIFP1_1_PCIE_LC_LANE_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CNTL3 0x4504b5 |
| #define regBIFP1_1_PCIE_LC_CNTL3_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CNTL4 0x4504b6 |
| #define regBIFP1_1_PCIE_LC_CNTL4_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CNTL5 0x4504b7 |
| #define regBIFP1_1_PCIE_LC_CNTL5_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_FORCE_COEFF 0x4504b8 |
| #define regBIFP1_1_PCIE_LC_FORCE_COEFF_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_BEST_EQ_SETTINGS 0x4504b9 |
| #define regBIFP1_1_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_FORCE_EQ_REQ_COEFF 0x4504ba |
| #define regBIFP1_1_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CNTL6 0x4504bb |
| #define regBIFP1_1_PCIE_LC_CNTL6_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CNTL7 0x4504bc |
| #define regBIFP1_1_PCIE_LC_CNTL7_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_LINK_MANAGEMENT_MASK 0x4504be |
| #define regBIFP1_1_PCIE_LC_LINK_MANAGEMENT_MASK_BASE_IDX 5 |
| #define regBIFP1_1_PCIEP_STRAP_LC 0x4504c0 |
| #define regBIFP1_1_PCIEP_STRAP_LC_BASE_IDX 5 |
| #define regBIFP1_1_PCIEP_STRAP_MISC 0x4504c1 |
| #define regBIFP1_1_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regBIFP1_1_PCIEP_STRAP_LC2 0x4504c2 |
| #define regBIFP1_1_PCIEP_STRAP_LC2_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_L1_PM_SUBSTATE 0x4504c6 |
| #define regBIFP1_1_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_L1_PM_SUBSTATE2 0x4504c7 |
| #define regBIFP1_1_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_L1_PM_SUBSTATE3 0x4504c8 |
| #define regBIFP1_1_PCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_L1_PM_SUBSTATE4 0x4504c9 |
| #define regBIFP1_1_PCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_L1_PM_SUBSTATE5 0x4504ca |
| #define regBIFP1_1_PCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 |
| #define regBIFP1_1_PCIEP_BCH_ECC_CNTL 0x4504d0 |
| #define regBIFP1_1_PCIEP_BCH_ECC_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CNTL8 0x4504dd |
| #define regBIFP1_1_PCIE_LC_CNTL8_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CNTL9 0x4504de |
| #define regBIFP1_1_PCIE_LC_CNTL9_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_FORCE_COEFF2 0x4504df |
| #define regBIFP1_1_PCIE_LC_FORCE_COEFF2_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_FORCE_EQ_REQ_COEFF2 0x4504e0 |
| #define regBIFP1_1_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x4504e2 |
| #define regBIFP1_1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CNTL10 0x4504e3 |
| #define regBIFP1_1_PCIE_LC_CNTL10_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_SAVE_RESTORE_1 0x4504e6 |
| #define regBIFP1_1_PCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_SAVE_RESTORE_2 0x4504e7 |
| #define regBIFP1_1_PCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CNTL11 0x450503 |
| #define regBIFP1_1_PCIE_LC_CNTL11_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_CNTL12 0x450504 |
| #define regBIFP1_1_PCIE_LC_CNTL12_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_SPEED_CNTL2 0x450505 |
| #define regBIFP1_1_PCIE_LC_SPEED_CNTL2_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_FORCE_COEFF3 0x450506 |
| #define regBIFP1_1_PCIE_LC_FORCE_COEFF3_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_LC_FORCE_EQ_REQ_COEFF3 0x450507 |
| #define regBIFP1_1_PCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_SEQ 0x450588 |
| #define regBIFP1_1_PCIE_TX_SEQ_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_REPLAY 0x450589 |
| #define regBIFP1_1_PCIE_TX_REPLAY_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_ACK_LATENCY_LIMIT 0x45058c |
| #define regBIFP1_1_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x450590 |
| #define regBIFP1_1_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_VENDOR_SPECIFIC 0x450594 |
| #define regBIFP1_1_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_NOP_DLLP 0x450595 |
| #define regBIFP1_1_PCIE_TX_NOP_DLLP_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_REQUEST_NUM_CNTL 0x450598 |
| #define regBIFP1_1_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_CREDITS_ADVT_P 0x4505a0 |
| #define regBIFP1_1_PCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_CREDITS_ADVT_NP 0x4505a1 |
| #define regBIFP1_1_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_CREDITS_ADVT_CPL 0x4505a2 |
| #define regBIFP1_1_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_CREDITS_INIT_P 0x4505a3 |
| #define regBIFP1_1_PCIE_TX_CREDITS_INIT_P_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_CREDITS_INIT_NP 0x4505a4 |
| #define regBIFP1_1_PCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_CREDITS_INIT_CPL 0x4505a5 |
| #define regBIFP1_1_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_TX_CREDITS_STATUS 0x4505a6 |
| #define regBIFP1_1_PCIE_TX_CREDITS_STATUS_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_FC_P 0x4505a8 |
| #define regBIFP1_1_PCIE_FC_P_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_FC_NP 0x4505a9 |
| #define regBIFP1_1_PCIE_FC_NP_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_FC_CPL 0x4505aa |
| #define regBIFP1_1_PCIE_FC_CPL_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_FC_P_VC1 0x4505ab |
| #define regBIFP1_1_PCIE_FC_P_VC1_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_FC_NP_VC1 0x4505ac |
| #define regBIFP1_1_PCIE_FC_NP_VC1_BASE_IDX 5 |
| #define regBIFP1_1_PCIE_FC_CPL_VC1 0x4505ad |
| #define regBIFP1_1_PCIE_FC_CPL_VC1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifp2_pciedir_p |
| // base address: 0x11242000 |
| #define regBIFP2_1_PCIEP_RESERVED 0x450800 |
| #define regBIFP2_1_PCIEP_RESERVED_BASE_IDX 5 |
| #define regBIFP2_1_PCIEP_SCRATCH 0x450801 |
| #define regBIFP2_1_PCIEP_SCRATCH_BASE_IDX 5 |
| #define regBIFP2_1_PCIEP_PORT_CNTL 0x450810 |
| #define regBIFP2_1_PCIEP_PORT_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_REQUESTER_ID 0x450821 |
| #define regBIFP2_1_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_P_PORT_LANE_STATUS 0x450850 |
| #define regBIFP2_1_PCIE_P_PORT_LANE_STATUS_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_ERR_CNTL 0x45086a |
| #define regBIFP2_1_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_RX_CNTL 0x450870 |
| #define regBIFP2_1_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_RX_EXPECTED_SEQNUM 0x450871 |
| #define regBIFP2_1_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_RX_VENDOR_SPECIFIC 0x450872 |
| #define regBIFP2_1_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_RX_CNTL3 0x450874 |
| #define regBIFP2_1_PCIE_RX_CNTL3_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_RX_CREDITS_ALLOCATED_P 0x450880 |
| #define regBIFP2_1_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_RX_CREDITS_ALLOCATED_NP 0x450881 |
| #define regBIFP2_1_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x450882 |
| #define regBIFP2_1_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 |
| #define regBIFP2_1_PCIEP_ERROR_INJECT_PHYSICAL 0x450883 |
| #define regBIFP2_1_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 |
| #define regBIFP2_1_PCIEP_ERROR_INJECT_TRANSACTION 0x450884 |
| #define regBIFP2_1_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 |
| #define regBIFP2_1_PCIEP_NAK_COUNTER 0x450886 |
| #define regBIFP2_1_PCIEP_NAK_COUNTER_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CNTL 0x4508a0 |
| #define regBIFP2_1_PCIE_LC_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_TRAINING_CNTL 0x4508a1 |
| #define regBIFP2_1_PCIE_LC_TRAINING_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_LINK_WIDTH_CNTL 0x4508a2 |
| #define regBIFP2_1_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_N_FTS_CNTL 0x4508a3 |
| #define regBIFP2_1_PCIE_LC_N_FTS_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_SPEED_CNTL 0x4508a4 |
| #define regBIFP2_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_STATE0 0x4508a5 |
| #define regBIFP2_1_PCIE_LC_STATE0_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_STATE1 0x4508a6 |
| #define regBIFP2_1_PCIE_LC_STATE1_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_STATE2 0x4508a7 |
| #define regBIFP2_1_PCIE_LC_STATE2_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_STATE3 0x4508a8 |
| #define regBIFP2_1_PCIE_LC_STATE3_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_STATE4 0x4508a9 |
| #define regBIFP2_1_PCIE_LC_STATE4_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_STATE5 0x4508aa |
| #define regBIFP2_1_PCIE_LC_STATE5_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CNTL2 0x4508b1 |
| #define regBIFP2_1_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_BW_CHANGE_CNTL 0x4508b2 |
| #define regBIFP2_1_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CDR_CNTL 0x4508b3 |
| #define regBIFP2_1_PCIE_LC_CDR_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_LANE_CNTL 0x4508b4 |
| #define regBIFP2_1_PCIE_LC_LANE_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CNTL3 0x4508b5 |
| #define regBIFP2_1_PCIE_LC_CNTL3_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CNTL4 0x4508b6 |
| #define regBIFP2_1_PCIE_LC_CNTL4_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CNTL5 0x4508b7 |
| #define regBIFP2_1_PCIE_LC_CNTL5_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_FORCE_COEFF 0x4508b8 |
| #define regBIFP2_1_PCIE_LC_FORCE_COEFF_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_BEST_EQ_SETTINGS 0x4508b9 |
| #define regBIFP2_1_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_FORCE_EQ_REQ_COEFF 0x4508ba |
| #define regBIFP2_1_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CNTL6 0x4508bb |
| #define regBIFP2_1_PCIE_LC_CNTL6_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CNTL7 0x4508bc |
| #define regBIFP2_1_PCIE_LC_CNTL7_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_LINK_MANAGEMENT_MASK 0x4508be |
| #define regBIFP2_1_PCIE_LC_LINK_MANAGEMENT_MASK_BASE_IDX 5 |
| #define regBIFP2_1_PCIEP_STRAP_LC 0x4508c0 |
| #define regBIFP2_1_PCIEP_STRAP_LC_BASE_IDX 5 |
| #define regBIFP2_1_PCIEP_STRAP_MISC 0x4508c1 |
| #define regBIFP2_1_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regBIFP2_1_PCIEP_STRAP_LC2 0x4508c2 |
| #define regBIFP2_1_PCIEP_STRAP_LC2_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_L1_PM_SUBSTATE 0x4508c6 |
| #define regBIFP2_1_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_L1_PM_SUBSTATE2 0x4508c7 |
| #define regBIFP2_1_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_L1_PM_SUBSTATE3 0x4508c8 |
| #define regBIFP2_1_PCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_L1_PM_SUBSTATE4 0x4508c9 |
| #define regBIFP2_1_PCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_L1_PM_SUBSTATE5 0x4508ca |
| #define regBIFP2_1_PCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 |
| #define regBIFP2_1_PCIEP_BCH_ECC_CNTL 0x4508d0 |
| #define regBIFP2_1_PCIEP_BCH_ECC_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CNTL8 0x4508dd |
| #define regBIFP2_1_PCIE_LC_CNTL8_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CNTL9 0x4508de |
| #define regBIFP2_1_PCIE_LC_CNTL9_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_FORCE_COEFF2 0x4508df |
| #define regBIFP2_1_PCIE_LC_FORCE_COEFF2_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_FORCE_EQ_REQ_COEFF2 0x4508e0 |
| #define regBIFP2_1_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x4508e2 |
| #define regBIFP2_1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CNTL10 0x4508e3 |
| #define regBIFP2_1_PCIE_LC_CNTL10_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_SAVE_RESTORE_1 0x4508e6 |
| #define regBIFP2_1_PCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_SAVE_RESTORE_2 0x4508e7 |
| #define regBIFP2_1_PCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CNTL11 0x450903 |
| #define regBIFP2_1_PCIE_LC_CNTL11_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_CNTL12 0x450904 |
| #define regBIFP2_1_PCIE_LC_CNTL12_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_SPEED_CNTL2 0x450905 |
| #define regBIFP2_1_PCIE_LC_SPEED_CNTL2_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_FORCE_COEFF3 0x450906 |
| #define regBIFP2_1_PCIE_LC_FORCE_COEFF3_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_LC_FORCE_EQ_REQ_COEFF3 0x450907 |
| #define regBIFP2_1_PCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_SEQ 0x450988 |
| #define regBIFP2_1_PCIE_TX_SEQ_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_REPLAY 0x450989 |
| #define regBIFP2_1_PCIE_TX_REPLAY_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_ACK_LATENCY_LIMIT 0x45098c |
| #define regBIFP2_1_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x450990 |
| #define regBIFP2_1_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_VENDOR_SPECIFIC 0x450994 |
| #define regBIFP2_1_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_NOP_DLLP 0x450995 |
| #define regBIFP2_1_PCIE_TX_NOP_DLLP_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_REQUEST_NUM_CNTL 0x450998 |
| #define regBIFP2_1_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_CREDITS_ADVT_P 0x4509a0 |
| #define regBIFP2_1_PCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_CREDITS_ADVT_NP 0x4509a1 |
| #define regBIFP2_1_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_CREDITS_ADVT_CPL 0x4509a2 |
| #define regBIFP2_1_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_CREDITS_INIT_P 0x4509a3 |
| #define regBIFP2_1_PCIE_TX_CREDITS_INIT_P_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_CREDITS_INIT_NP 0x4509a4 |
| #define regBIFP2_1_PCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_CREDITS_INIT_CPL 0x4509a5 |
| #define regBIFP2_1_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_TX_CREDITS_STATUS 0x4509a6 |
| #define regBIFP2_1_PCIE_TX_CREDITS_STATUS_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_FC_P 0x4509a8 |
| #define regBIFP2_1_PCIE_FC_P_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_FC_NP 0x4509a9 |
| #define regBIFP2_1_PCIE_FC_NP_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_FC_CPL 0x4509aa |
| #define regBIFP2_1_PCIE_FC_CPL_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_FC_P_VC1 0x4509ab |
| #define regBIFP2_1_PCIE_FC_P_VC1_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_FC_NP_VC1 0x4509ac |
| #define regBIFP2_1_PCIE_FC_NP_VC1_BASE_IDX 5 |
| #define regBIFP2_1_PCIE_FC_CPL_VC1 0x4509ad |
| #define regBIFP2_1_PCIE_FC_CPL_VC1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifp3_pciedir_p |
| // base address: 0x11243000 |
| #define regBIFP3_1_PCIEP_RESERVED 0x450c00 |
| #define regBIFP3_1_PCIEP_RESERVED_BASE_IDX 5 |
| #define regBIFP3_1_PCIEP_SCRATCH 0x450c01 |
| #define regBIFP3_1_PCIEP_SCRATCH_BASE_IDX 5 |
| #define regBIFP3_1_PCIEP_PORT_CNTL 0x450c10 |
| #define regBIFP3_1_PCIEP_PORT_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_REQUESTER_ID 0x450c21 |
| #define regBIFP3_1_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_P_PORT_LANE_STATUS 0x450c50 |
| #define regBIFP3_1_PCIE_P_PORT_LANE_STATUS_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_ERR_CNTL 0x450c6a |
| #define regBIFP3_1_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_RX_CNTL 0x450c70 |
| #define regBIFP3_1_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_RX_EXPECTED_SEQNUM 0x450c71 |
| #define regBIFP3_1_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_RX_VENDOR_SPECIFIC 0x450c72 |
| #define regBIFP3_1_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_RX_CNTL3 0x450c74 |
| #define regBIFP3_1_PCIE_RX_CNTL3_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_RX_CREDITS_ALLOCATED_P 0x450c80 |
| #define regBIFP3_1_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_RX_CREDITS_ALLOCATED_NP 0x450c81 |
| #define regBIFP3_1_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x450c82 |
| #define regBIFP3_1_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 |
| #define regBIFP3_1_PCIEP_ERROR_INJECT_PHYSICAL 0x450c83 |
| #define regBIFP3_1_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 |
| #define regBIFP3_1_PCIEP_ERROR_INJECT_TRANSACTION 0x450c84 |
| #define regBIFP3_1_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 |
| #define regBIFP3_1_PCIEP_NAK_COUNTER 0x450c86 |
| #define regBIFP3_1_PCIEP_NAK_COUNTER_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CNTL 0x450ca0 |
| #define regBIFP3_1_PCIE_LC_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_TRAINING_CNTL 0x450ca1 |
| #define regBIFP3_1_PCIE_LC_TRAINING_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_LINK_WIDTH_CNTL 0x450ca2 |
| #define regBIFP3_1_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_N_FTS_CNTL 0x450ca3 |
| #define regBIFP3_1_PCIE_LC_N_FTS_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_SPEED_CNTL 0x450ca4 |
| #define regBIFP3_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_STATE0 0x450ca5 |
| #define regBIFP3_1_PCIE_LC_STATE0_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_STATE1 0x450ca6 |
| #define regBIFP3_1_PCIE_LC_STATE1_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_STATE2 0x450ca7 |
| #define regBIFP3_1_PCIE_LC_STATE2_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_STATE3 0x450ca8 |
| #define regBIFP3_1_PCIE_LC_STATE3_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_STATE4 0x450ca9 |
| #define regBIFP3_1_PCIE_LC_STATE4_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_STATE5 0x450caa |
| #define regBIFP3_1_PCIE_LC_STATE5_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CNTL2 0x450cb1 |
| #define regBIFP3_1_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_BW_CHANGE_CNTL 0x450cb2 |
| #define regBIFP3_1_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CDR_CNTL 0x450cb3 |
| #define regBIFP3_1_PCIE_LC_CDR_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_LANE_CNTL 0x450cb4 |
| #define regBIFP3_1_PCIE_LC_LANE_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CNTL3 0x450cb5 |
| #define regBIFP3_1_PCIE_LC_CNTL3_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CNTL4 0x450cb6 |
| #define regBIFP3_1_PCIE_LC_CNTL4_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CNTL5 0x450cb7 |
| #define regBIFP3_1_PCIE_LC_CNTL5_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_FORCE_COEFF 0x450cb8 |
| #define regBIFP3_1_PCIE_LC_FORCE_COEFF_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_BEST_EQ_SETTINGS 0x450cb9 |
| #define regBIFP3_1_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_FORCE_EQ_REQ_COEFF 0x450cba |
| #define regBIFP3_1_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CNTL6 0x450cbb |
| #define regBIFP3_1_PCIE_LC_CNTL6_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CNTL7 0x450cbc |
| #define regBIFP3_1_PCIE_LC_CNTL7_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_LINK_MANAGEMENT_MASK 0x450cbe |
| #define regBIFP3_1_PCIE_LC_LINK_MANAGEMENT_MASK_BASE_IDX 5 |
| #define regBIFP3_1_PCIEP_STRAP_LC 0x450cc0 |
| #define regBIFP3_1_PCIEP_STRAP_LC_BASE_IDX 5 |
| #define regBIFP3_1_PCIEP_STRAP_MISC 0x450cc1 |
| #define regBIFP3_1_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regBIFP3_1_PCIEP_STRAP_LC2 0x450cc2 |
| #define regBIFP3_1_PCIEP_STRAP_LC2_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_L1_PM_SUBSTATE 0x450cc6 |
| #define regBIFP3_1_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_L1_PM_SUBSTATE2 0x450cc7 |
| #define regBIFP3_1_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_L1_PM_SUBSTATE3 0x450cc8 |
| #define regBIFP3_1_PCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_L1_PM_SUBSTATE4 0x450cc9 |
| #define regBIFP3_1_PCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_L1_PM_SUBSTATE5 0x450cca |
| #define regBIFP3_1_PCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 |
| #define regBIFP3_1_PCIEP_BCH_ECC_CNTL 0x450cd0 |
| #define regBIFP3_1_PCIEP_BCH_ECC_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CNTL8 0x450cdd |
| #define regBIFP3_1_PCIE_LC_CNTL8_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CNTL9 0x450cde |
| #define regBIFP3_1_PCIE_LC_CNTL9_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_FORCE_COEFF2 0x450cdf |
| #define regBIFP3_1_PCIE_LC_FORCE_COEFF2_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_FORCE_EQ_REQ_COEFF2 0x450ce0 |
| #define regBIFP3_1_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x450ce2 |
| #define regBIFP3_1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CNTL10 0x450ce3 |
| #define regBIFP3_1_PCIE_LC_CNTL10_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_SAVE_RESTORE_1 0x450ce6 |
| #define regBIFP3_1_PCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_SAVE_RESTORE_2 0x450ce7 |
| #define regBIFP3_1_PCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CNTL11 0x450d03 |
| #define regBIFP3_1_PCIE_LC_CNTL11_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_CNTL12 0x450d04 |
| #define regBIFP3_1_PCIE_LC_CNTL12_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_SPEED_CNTL2 0x450d05 |
| #define regBIFP3_1_PCIE_LC_SPEED_CNTL2_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_FORCE_COEFF3 0x450d06 |
| #define regBIFP3_1_PCIE_LC_FORCE_COEFF3_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_LC_FORCE_EQ_REQ_COEFF3 0x450d07 |
| #define regBIFP3_1_PCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_SEQ 0x450d88 |
| #define regBIFP3_1_PCIE_TX_SEQ_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_REPLAY 0x450d89 |
| #define regBIFP3_1_PCIE_TX_REPLAY_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_ACK_LATENCY_LIMIT 0x450d8c |
| #define regBIFP3_1_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x450d90 |
| #define regBIFP3_1_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_VENDOR_SPECIFIC 0x450d94 |
| #define regBIFP3_1_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_NOP_DLLP 0x450d95 |
| #define regBIFP3_1_PCIE_TX_NOP_DLLP_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_REQUEST_NUM_CNTL 0x450d98 |
| #define regBIFP3_1_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_CREDITS_ADVT_P 0x450da0 |
| #define regBIFP3_1_PCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_CREDITS_ADVT_NP 0x450da1 |
| #define regBIFP3_1_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_CREDITS_ADVT_CPL 0x450da2 |
| #define regBIFP3_1_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_CREDITS_INIT_P 0x450da3 |
| #define regBIFP3_1_PCIE_TX_CREDITS_INIT_P_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_CREDITS_INIT_NP 0x450da4 |
| #define regBIFP3_1_PCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_CREDITS_INIT_CPL 0x450da5 |
| #define regBIFP3_1_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_TX_CREDITS_STATUS 0x450da6 |
| #define regBIFP3_1_PCIE_TX_CREDITS_STATUS_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_FC_P 0x450da8 |
| #define regBIFP3_1_PCIE_FC_P_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_FC_NP 0x450da9 |
| #define regBIFP3_1_PCIE_FC_NP_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_FC_CPL 0x450daa |
| #define regBIFP3_1_PCIE_FC_CPL_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_FC_P_VC1 0x450dab |
| #define regBIFP3_1_PCIE_FC_P_VC1_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_FC_NP_VC1 0x450dac |
| #define regBIFP3_1_PCIE_FC_NP_VC1_BASE_IDX 5 |
| #define regBIFP3_1_PCIE_FC_CPL_VC1 0x450dad |
| #define regBIFP3_1_PCIE_FC_CPL_VC1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifp4_pciedir_p |
| // base address: 0x11244000 |
| #define regBIFP4_1_PCIEP_RESERVED 0x451000 |
| #define regBIFP4_1_PCIEP_RESERVED_BASE_IDX 5 |
| #define regBIFP4_1_PCIEP_SCRATCH 0x451001 |
| #define regBIFP4_1_PCIEP_SCRATCH_BASE_IDX 5 |
| #define regBIFP4_1_PCIEP_PORT_CNTL 0x451010 |
| #define regBIFP4_1_PCIEP_PORT_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_REQUESTER_ID 0x451021 |
| #define regBIFP4_1_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_P_PORT_LANE_STATUS 0x451050 |
| #define regBIFP4_1_PCIE_P_PORT_LANE_STATUS_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_ERR_CNTL 0x45106a |
| #define regBIFP4_1_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_RX_CNTL 0x451070 |
| #define regBIFP4_1_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_RX_EXPECTED_SEQNUM 0x451071 |
| #define regBIFP4_1_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_RX_VENDOR_SPECIFIC 0x451072 |
| #define regBIFP4_1_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_RX_CNTL3 0x451074 |
| #define regBIFP4_1_PCIE_RX_CNTL3_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_RX_CREDITS_ALLOCATED_P 0x451080 |
| #define regBIFP4_1_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_RX_CREDITS_ALLOCATED_NP 0x451081 |
| #define regBIFP4_1_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x451082 |
| #define regBIFP4_1_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 |
| #define regBIFP4_1_PCIEP_ERROR_INJECT_PHYSICAL 0x451083 |
| #define regBIFP4_1_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 |
| #define regBIFP4_1_PCIEP_ERROR_INJECT_TRANSACTION 0x451084 |
| #define regBIFP4_1_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 |
| #define regBIFP4_1_PCIEP_NAK_COUNTER 0x451086 |
| #define regBIFP4_1_PCIEP_NAK_COUNTER_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CNTL 0x4510a0 |
| #define regBIFP4_1_PCIE_LC_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_TRAINING_CNTL 0x4510a1 |
| #define regBIFP4_1_PCIE_LC_TRAINING_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_LINK_WIDTH_CNTL 0x4510a2 |
| #define regBIFP4_1_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_N_FTS_CNTL 0x4510a3 |
| #define regBIFP4_1_PCIE_LC_N_FTS_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_SPEED_CNTL 0x4510a4 |
| #define regBIFP4_1_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_STATE0 0x4510a5 |
| #define regBIFP4_1_PCIE_LC_STATE0_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_STATE1 0x4510a6 |
| #define regBIFP4_1_PCIE_LC_STATE1_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_STATE2 0x4510a7 |
| #define regBIFP4_1_PCIE_LC_STATE2_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_STATE3 0x4510a8 |
| #define regBIFP4_1_PCIE_LC_STATE3_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_STATE4 0x4510a9 |
| #define regBIFP4_1_PCIE_LC_STATE4_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_STATE5 0x4510aa |
| #define regBIFP4_1_PCIE_LC_STATE5_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CNTL2 0x4510b1 |
| #define regBIFP4_1_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_BW_CHANGE_CNTL 0x4510b2 |
| #define regBIFP4_1_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CDR_CNTL 0x4510b3 |
| #define regBIFP4_1_PCIE_LC_CDR_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_LANE_CNTL 0x4510b4 |
| #define regBIFP4_1_PCIE_LC_LANE_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CNTL3 0x4510b5 |
| #define regBIFP4_1_PCIE_LC_CNTL3_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CNTL4 0x4510b6 |
| #define regBIFP4_1_PCIE_LC_CNTL4_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CNTL5 0x4510b7 |
| #define regBIFP4_1_PCIE_LC_CNTL5_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_FORCE_COEFF 0x4510b8 |
| #define regBIFP4_1_PCIE_LC_FORCE_COEFF_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_BEST_EQ_SETTINGS 0x4510b9 |
| #define regBIFP4_1_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_FORCE_EQ_REQ_COEFF 0x4510ba |
| #define regBIFP4_1_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CNTL6 0x4510bb |
| #define regBIFP4_1_PCIE_LC_CNTL6_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CNTL7 0x4510bc |
| #define regBIFP4_1_PCIE_LC_CNTL7_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_LINK_MANAGEMENT_MASK 0x4510be |
| #define regBIFP4_1_PCIE_LC_LINK_MANAGEMENT_MASK_BASE_IDX 5 |
| #define regBIFP4_1_PCIEP_STRAP_LC 0x4510c0 |
| #define regBIFP4_1_PCIEP_STRAP_LC_BASE_IDX 5 |
| #define regBIFP4_1_PCIEP_STRAP_MISC 0x4510c1 |
| #define regBIFP4_1_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regBIFP4_1_PCIEP_STRAP_LC2 0x4510c2 |
| #define regBIFP4_1_PCIEP_STRAP_LC2_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_L1_PM_SUBSTATE 0x4510c6 |
| #define regBIFP4_1_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_L1_PM_SUBSTATE2 0x4510c7 |
| #define regBIFP4_1_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_L1_PM_SUBSTATE3 0x4510c8 |
| #define regBIFP4_1_PCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_L1_PM_SUBSTATE4 0x4510c9 |
| #define regBIFP4_1_PCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_L1_PM_SUBSTATE5 0x4510ca |
| #define regBIFP4_1_PCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 |
| #define regBIFP4_1_PCIEP_BCH_ECC_CNTL 0x4510d0 |
| #define regBIFP4_1_PCIEP_BCH_ECC_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CNTL8 0x4510dd |
| #define regBIFP4_1_PCIE_LC_CNTL8_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CNTL9 0x4510de |
| #define regBIFP4_1_PCIE_LC_CNTL9_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_FORCE_COEFF2 0x4510df |
| #define regBIFP4_1_PCIE_LC_FORCE_COEFF2_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_FORCE_EQ_REQ_COEFF2 0x4510e0 |
| #define regBIFP4_1_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x4510e2 |
| #define regBIFP4_1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CNTL10 0x4510e3 |
| #define regBIFP4_1_PCIE_LC_CNTL10_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_SAVE_RESTORE_1 0x4510e6 |
| #define regBIFP4_1_PCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_SAVE_RESTORE_2 0x4510e7 |
| #define regBIFP4_1_PCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CNTL11 0x451103 |
| #define regBIFP4_1_PCIE_LC_CNTL11_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_CNTL12 0x451104 |
| #define regBIFP4_1_PCIE_LC_CNTL12_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_SPEED_CNTL2 0x451105 |
| #define regBIFP4_1_PCIE_LC_SPEED_CNTL2_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_FORCE_COEFF3 0x451106 |
| #define regBIFP4_1_PCIE_LC_FORCE_COEFF3_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_LC_FORCE_EQ_REQ_COEFF3 0x451107 |
| #define regBIFP4_1_PCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_SEQ 0x451188 |
| #define regBIFP4_1_PCIE_TX_SEQ_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_REPLAY 0x451189 |
| #define regBIFP4_1_PCIE_TX_REPLAY_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_ACK_LATENCY_LIMIT 0x45118c |
| #define regBIFP4_1_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x451190 |
| #define regBIFP4_1_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_VENDOR_SPECIFIC 0x451194 |
| #define regBIFP4_1_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_NOP_DLLP 0x451195 |
| #define regBIFP4_1_PCIE_TX_NOP_DLLP_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_REQUEST_NUM_CNTL 0x451198 |
| #define regBIFP4_1_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_CREDITS_ADVT_P 0x4511a0 |
| #define regBIFP4_1_PCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_CREDITS_ADVT_NP 0x4511a1 |
| #define regBIFP4_1_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_CREDITS_ADVT_CPL 0x4511a2 |
| #define regBIFP4_1_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_CREDITS_INIT_P 0x4511a3 |
| #define regBIFP4_1_PCIE_TX_CREDITS_INIT_P_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_CREDITS_INIT_NP 0x4511a4 |
| #define regBIFP4_1_PCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_CREDITS_INIT_CPL 0x4511a5 |
| #define regBIFP4_1_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_TX_CREDITS_STATUS 0x4511a6 |
| #define regBIFP4_1_PCIE_TX_CREDITS_STATUS_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_FC_P 0x4511a8 |
| #define regBIFP4_1_PCIE_FC_P_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_FC_NP 0x4511a9 |
| #define regBIFP4_1_PCIE_FC_NP_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_FC_CPL 0x4511aa |
| #define regBIFP4_1_PCIE_FC_CPL_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_FC_P_VC1 0x4511ab |
| #define regBIFP4_1_PCIE_FC_P_VC1_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_FC_NP_VC1 0x4511ac |
| #define regBIFP4_1_PCIE_FC_NP_VC1_BASE_IDX 5 |
| #define regBIFP4_1_PCIE_FC_CPL_VC1 0x4511ad |
| #define regBIFP4_1_PCIE_FC_CPL_VC1_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifp5_pciedir_p |
| // base address: 0x11245000 |
| #define regBIFP5_PCIEP_RESERVED 0x451400 |
| #define regBIFP5_PCIEP_RESERVED_BASE_IDX 5 |
| #define regBIFP5_PCIEP_SCRATCH 0x451401 |
| #define regBIFP5_PCIEP_SCRATCH_BASE_IDX 5 |
| #define regBIFP5_PCIEP_PORT_CNTL 0x451410 |
| #define regBIFP5_PCIEP_PORT_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_REQUESTER_ID 0x451421 |
| #define regBIFP5_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_SKID_CTRL 0x45142f |
| #define regBIFP5_PCIE_TX_SKID_CTRL_BASE_IDX 5 |
| #define regBIFP5_PCIE_P_PORT_LANE_STATUS 0x451450 |
| #define regBIFP5_PCIE_P_PORT_LANE_STATUS_BASE_IDX 5 |
| #define regBIFP5_PCIE_ERR_CNTL 0x45146a |
| #define regBIFP5_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIE_RX_CNTL 0x451470 |
| #define regBIFP5_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIE_RX_EXPECTED_SEQNUM 0x451471 |
| #define regBIFP5_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX 5 |
| #define regBIFP5_PCIE_RX_VENDOR_SPECIFIC 0x451472 |
| #define regBIFP5_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP5_PCIE_RX_CNTL3 0x451474 |
| #define regBIFP5_PCIE_RX_CNTL3_BASE_IDX 5 |
| #define regBIFP5_PCIE_RX_CREDITS_ALLOCATED_P 0x451480 |
| #define regBIFP5_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX 5 |
| #define regBIFP5_PCIE_RX_CREDITS_ALLOCATED_NP 0x451481 |
| #define regBIFP5_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX 5 |
| #define regBIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL 0x451482 |
| #define regBIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX 5 |
| #define regBIFP5_PCIEP_ERROR_INJECT_PHYSICAL 0x451483 |
| #define regBIFP5_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX 5 |
| #define regBIFP5_PCIEP_ERROR_INJECT_TRANSACTION 0x451484 |
| #define regBIFP5_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX 5 |
| #define regBIFP5_PCIEP_NAK_COUNTER 0x451486 |
| #define regBIFP5_PCIEP_NAK_COUNTER_BASE_IDX 5 |
| #define regBIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS 0x451488 |
| #define regBIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_BASE_IDX 5 |
| #define regBIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES 0x451489 |
| #define regBIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_BASE_IDX 5 |
| #define regBIFP5_PCIE_AER_PRIV_UNCORRECTABLE_MASK 0x45148c |
| #define regBIFP5_PCIE_AER_PRIV_UNCORRECTABLE_MASK_BASE_IDX 5 |
| #define regBIFP5_PCIE_AER_PRIV_TRIGGER 0x45148d |
| #define regBIFP5_PCIE_AER_PRIV_TRIGGER_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CNTL 0x4514a0 |
| #define regBIFP5_PCIE_LC_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_TRAINING_CNTL 0x4514a1 |
| #define regBIFP5_PCIE_LC_TRAINING_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_LINK_WIDTH_CNTL 0x4514a2 |
| #define regBIFP5_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_N_FTS_CNTL 0x4514a3 |
| #define regBIFP5_PCIE_LC_N_FTS_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_SPEED_CNTL 0x4514a4 |
| #define regBIFP5_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_STATE0 0x4514a5 |
| #define regBIFP5_PCIE_LC_STATE0_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_STATE1 0x4514a6 |
| #define regBIFP5_PCIE_LC_STATE1_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_STATE2 0x4514a7 |
| #define regBIFP5_PCIE_LC_STATE2_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_STATE3 0x4514a8 |
| #define regBIFP5_PCIE_LC_STATE3_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_STATE4 0x4514a9 |
| #define regBIFP5_PCIE_LC_STATE4_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_STATE5 0x4514aa |
| #define regBIFP5_PCIE_LC_STATE5_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CNTL2 0x4514b1 |
| #define regBIFP5_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_BW_CHANGE_CNTL 0x4514b2 |
| #define regBIFP5_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CDR_CNTL 0x4514b3 |
| #define regBIFP5_PCIE_LC_CDR_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_LANE_CNTL 0x4514b4 |
| #define regBIFP5_PCIE_LC_LANE_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CNTL3 0x4514b5 |
| #define regBIFP5_PCIE_LC_CNTL3_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CNTL4 0x4514b6 |
| #define regBIFP5_PCIE_LC_CNTL4_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CNTL5 0x4514b7 |
| #define regBIFP5_PCIE_LC_CNTL5_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_FORCE_COEFF 0x4514b8 |
| #define regBIFP5_PCIE_LC_FORCE_COEFF_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_BEST_EQ_SETTINGS 0x4514b9 |
| #define regBIFP5_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF 0x4514ba |
| #define regBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CNTL6 0x4514bb |
| #define regBIFP5_PCIE_LC_CNTL6_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CNTL7 0x4514bc |
| #define regBIFP5_PCIE_LC_CNTL7_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_LINK_MANAGEMENT_MASK 0x4514be |
| #define regBIFP5_PCIE_LC_LINK_MANAGEMENT_MASK_BASE_IDX 5 |
| #define regBIFP5_PCIEP_STRAP_LC 0x4514c0 |
| #define regBIFP5_PCIEP_STRAP_LC_BASE_IDX 5 |
| #define regBIFP5_PCIEP_STRAP_MISC 0x4514c1 |
| #define regBIFP5_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regBIFP5_PCIEP_STRAP_LC2 0x4514c2 |
| #define regBIFP5_PCIEP_STRAP_LC2_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_L1_PM_SUBSTATE 0x4514c6 |
| #define regBIFP5_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_L1_PM_SUBSTATE2 0x4514c7 |
| #define regBIFP5_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_L1_PM_SUBSTATE3 0x4514c8 |
| #define regBIFP5_PCIE_LC_L1_PM_SUBSTATE3_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_L1_PM_SUBSTATE4 0x4514c9 |
| #define regBIFP5_PCIE_LC_L1_PM_SUBSTATE4_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_L1_PM_SUBSTATE5 0x4514ca |
| #define regBIFP5_PCIE_LC_L1_PM_SUBSTATE5_BASE_IDX 5 |
| #define regBIFP5_PCIEP_BCH_ECC_CNTL 0x4514d0 |
| #define regBIFP5_PCIEP_BCH_ECC_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIEP_HPGI_PRIVATE 0x4514d2 |
| #define regBIFP5_PCIEP_HPGI_PRIVATE_BASE_IDX 5 |
| #define regBIFP5_PCIEP_HPGI 0x4514da |
| #define regBIFP5_PCIEP_HPGI_BASE_IDX 5 |
| #define regBIFP5_PCIEP_HCNT_DESCRIPTOR 0x4514db |
| #define regBIFP5_PCIEP_HCNT_DESCRIPTOR_BASE_IDX 5 |
| #define regBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK 0x4514dc |
| #define regBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CNTL8 0x4514dd |
| #define regBIFP5_PCIE_LC_CNTL8_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CNTL9 0x4514de |
| #define regBIFP5_PCIE_LC_CNTL9_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_FORCE_COEFF2 0x4514df |
| #define regBIFP5_PCIE_LC_FORCE_COEFF2_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2 0x4514e0 |
| #define regBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX 5 |
| #define regBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC 0x4514e1 |
| #define regBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0x4514e2 |
| #define regBIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CNTL10 0x4514e3 |
| #define regBIFP5_PCIE_LC_CNTL10_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_SAVE_RESTORE_1 0x4514e6 |
| #define regBIFP5_PCIE_LC_SAVE_RESTORE_1_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_SAVE_RESTORE_2 0x4514e7 |
| #define regBIFP5_PCIE_LC_SAVE_RESTORE_2_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_SAVE_RESTORE_3 0x4514e8 |
| #define regBIFP5_PCIE_LC_SAVE_RESTORE_3_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CNTL11 0x451503 |
| #define regBIFP5_PCIE_LC_CNTL11_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_CNTL12 0x451504 |
| #define regBIFP5_PCIE_LC_CNTL12_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_SPEED_CNTL2 0x451505 |
| #define regBIFP5_PCIE_LC_SPEED_CNTL2_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_FORCE_COEFF3 0x451506 |
| #define regBIFP5_PCIE_LC_FORCE_COEFF3_BASE_IDX 5 |
| #define regBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF3 0x451507 |
| #define regBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF3_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_SEQ 0x451588 |
| #define regBIFP5_PCIE_TX_SEQ_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_REPLAY 0x451589 |
| #define regBIFP5_PCIE_TX_REPLAY_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_ACK_LATENCY_LIMIT 0x45158c |
| #define regBIFP5_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD 0x451590 |
| #define regBIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_VENDOR_SPECIFIC 0x451594 |
| #define regBIFP5_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_NOP_DLLP 0x451595 |
| #define regBIFP5_PCIE_TX_NOP_DLLP_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_REQUEST_NUM_CNTL 0x451598 |
| #define regBIFP5_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_CREDITS_ADVT_P 0x4515a0 |
| #define regBIFP5_PCIE_TX_CREDITS_ADVT_P_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_CREDITS_ADVT_NP 0x4515a1 |
| #define regBIFP5_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_CREDITS_ADVT_CPL 0x4515a2 |
| #define regBIFP5_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_CREDITS_INIT_P 0x4515a3 |
| #define regBIFP5_PCIE_TX_CREDITS_INIT_P_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_CREDITS_INIT_NP 0x4515a4 |
| #define regBIFP5_PCIE_TX_CREDITS_INIT_NP_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_CREDITS_INIT_CPL 0x4515a5 |
| #define regBIFP5_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX 5 |
| #define regBIFP5_PCIE_TX_CREDITS_STATUS 0x4515a6 |
| #define regBIFP5_PCIE_TX_CREDITS_STATUS_BASE_IDX 5 |
| #define regBIFP5_PCIE_FC_P 0x4515a8 |
| #define regBIFP5_PCIE_FC_P_BASE_IDX 5 |
| #define regBIFP5_PCIE_FC_NP 0x4515a9 |
| #define regBIFP5_PCIE_FC_NP_BASE_IDX 5 |
| #define regBIFP5_PCIE_FC_CPL 0x4515aa |
| #define regBIFP5_PCIE_FC_CPL_BASE_IDX 5 |
| #define regBIFP5_PCIE_FC_P_VC1 0x4515ab |
| #define regBIFP5_PCIE_FC_P_VC1_BASE_IDX 5 |
| #define regBIFP5_PCIE_FC_NP_VC1 0x4515ac |
| #define regBIFP5_PCIE_FC_NP_VC1_BASE_IDX 5 |
| #define regBIFP5_PCIE_FC_CPL_VC1 0x4515ad |
| #define regBIFP5_PCIE_FC_CPL_VC1_BASE_IDX 5 |
| #define regBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_TX 0x4515bd |
| #define regBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_TX_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_pciedir |
| // base address: 0x11280000 |
| #define regBIF1_PCIE_RESERVED 0x460000 |
| #define regBIF1_PCIE_RESERVED_BASE_IDX 5 |
| #define regBIF1_PCIE_SCRATCH 0x460001 |
| #define regBIF1_PCIE_SCRATCH_BASE_IDX 5 |
| #define regBIF1_PCIE_RX_NUM_NAK 0x46000e |
| #define regBIF1_PCIE_RX_NUM_NAK_BASE_IDX 5 |
| #define regBIF1_PCIE_RX_NUM_NAK_GENERATED 0x46000f |
| #define regBIF1_PCIE_RX_NUM_NAK_GENERATED_BASE_IDX 5 |
| #define regBIF1_PCIE_CNTL 0x460010 |
| #define regBIF1_PCIE_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_CONFIG_CNTL 0x460011 |
| #define regBIF1_PCIE_CONFIG_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_DEBUG_CNTL 0x460012 |
| #define regBIF1_PCIE_DEBUG_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_RX_CNTL5 0x460018 |
| #define regBIF1_PCIE_RX_CNTL5_BASE_IDX 5 |
| #define regBIF1_PCIE_RX_CNTL4 0x460019 |
| #define regBIF1_PCIE_RX_CNTL4_BASE_IDX 5 |
| #define regBIF1_PCIE_COMMON_AER_MASK 0x46001a |
| #define regBIF1_PCIE_COMMON_AER_MASK_BASE_IDX 5 |
| #define regBIF1_PCIE_CNTL2 0x46001c |
| #define regBIF1_PCIE_CNTL2_BASE_IDX 5 |
| #define regBIF1_PCIE_RX_CNTL2 0x46001d |
| #define regBIF1_PCIE_RX_CNTL2_BASE_IDX 5 |
| #define regBIF1_PCIE_CI_CNTL 0x460020 |
| #define regBIF1_PCIE_CI_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_BUS_CNTL 0x460021 |
| #define regBIF1_PCIE_BUS_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_LC_STATE6 0x460022 |
| #define regBIF1_PCIE_LC_STATE6_BASE_IDX 5 |
| #define regBIF1_PCIE_LC_STATE7 0x460023 |
| #define regBIF1_PCIE_LC_STATE7_BASE_IDX 5 |
| #define regBIF1_PCIE_LC_STATE8 0x460024 |
| #define regBIF1_PCIE_LC_STATE8_BASE_IDX 5 |
| #define regBIF1_PCIE_LC_STATE9 0x460025 |
| #define regBIF1_PCIE_LC_STATE9_BASE_IDX 5 |
| #define regBIF1_PCIE_LC_STATE10 0x460026 |
| #define regBIF1_PCIE_LC_STATE10_BASE_IDX 5 |
| #define regBIF1_PCIE_LC_STATE11 0x460027 |
| #define regBIF1_PCIE_LC_STATE11_BASE_IDX 5 |
| #define regBIF1_PCIE_LC_STATUS1 0x460028 |
| #define regBIF1_PCIE_LC_STATUS1_BASE_IDX 5 |
| #define regBIF1_PCIE_LC_STATUS2 0x460029 |
| #define regBIF1_PCIE_LC_STATUS2_BASE_IDX 5 |
| #define regBIF1_PCIE_WPR_CNTL 0x460030 |
| #define regBIF1_PCIE_WPR_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_RX_LAST_TLP0 0x460031 |
| #define regBIF1_PCIE_RX_LAST_TLP0_BASE_IDX 5 |
| #define regBIF1_PCIE_RX_LAST_TLP1 0x460032 |
| #define regBIF1_PCIE_RX_LAST_TLP1_BASE_IDX 5 |
| #define regBIF1_PCIE_RX_LAST_TLP2 0x460033 |
| #define regBIF1_PCIE_RX_LAST_TLP2_BASE_IDX 5 |
| #define regBIF1_PCIE_RX_LAST_TLP3 0x460034 |
| #define regBIF1_PCIE_RX_LAST_TLP3_BASE_IDX 5 |
| #define regBIF1_PCIE_I2C_REG_ADDR_EXPAND 0x46003a |
| #define regBIF1_PCIE_I2C_REG_ADDR_EXPAND_BASE_IDX 5 |
| #define regBIF1_PCIE_I2C_REG_DATA 0x46003b |
| #define regBIF1_PCIE_I2C_REG_DATA_BASE_IDX 5 |
| #define regBIF1_PCIE_CFG_CNTL 0x46003c |
| #define regBIF1_PCIE_CFG_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_LC_PM_CNTL 0x46003d |
| #define regBIF1_PCIE_LC_PM_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_LC_PM_CNTL2 0x46003e |
| #define regBIF1_PCIE_LC_PM_CNTL2_BASE_IDX 5 |
| #define regBIF1_PCIE_P_CNTL 0x460040 |
| #define regBIF1_PCIE_P_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_P_BUF_STATUS 0x460041 |
| #define regBIF1_PCIE_P_BUF_STATUS_BASE_IDX 5 |
| #define regBIF1_PCIE_P_DECODER_STATUS 0x460042 |
| #define regBIF1_PCIE_P_DECODER_STATUS_BASE_IDX 5 |
| #define regBIF1_PCIE_P_MISC_STATUS 0x460043 |
| #define regBIF1_PCIE_P_MISC_STATUS_BASE_IDX 5 |
| #define regBIF1_PCIE_P_RCV_L0S_FTS_DET 0x460050 |
| #define regBIF1_PCIE_P_RCV_L0S_FTS_DET_BASE_IDX 5 |
| #define regBIF1_PCIE_RX_AD 0x460062 |
| #define regBIF1_PCIE_RX_AD_BASE_IDX 5 |
| #define regBIF1_PCIE_SDP_CTRL 0x460063 |
| #define regBIF1_PCIE_SDP_CTRL_BASE_IDX 5 |
| #define regBIF1_NBIO_CLKREQb_MAP_CNTL 0x460064 |
| #define regBIF1_NBIO_CLKREQb_MAP_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_SDP_SWUS_SLV_ATTR_CTRL 0x460065 |
| #define regBIF1_PCIE_SDP_SWUS_SLV_ATTR_CTRL_BASE_IDX 5 |
| #define regBIF1_PCIE_SDP_RC_SLV_ATTR_CTRL 0x460066 |
| #define regBIF1_PCIE_SDP_RC_SLV_ATTR_CTRL_BASE_IDX 5 |
| #define regBIF1_NBIO_CLKREQb_MAP_CNTL2 0x460067 |
| #define regBIF1_NBIO_CLKREQb_MAP_CNTL2_BASE_IDX 5 |
| #define regBIF1_PCIE_SDP_CTRL2 0x460068 |
| #define regBIF1_PCIE_SDP_CTRL2_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT_CNTL 0x460080 |
| #define regBIF1_PCIE_PERF_COUNT_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK1 0x460081 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK1_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK1 0x460082 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK1_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK1 0x460083 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK1_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK2 0x460084 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK2_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK2 0x460085 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK2_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK2 0x460086 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK2_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK3 0x460087 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK3_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK3 0x460088 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK3_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK3 0x460089 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK3_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK4 0x46008a |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK4_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK4 0x46008b |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK4_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK4 0x46008c |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK4_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_CNTL_EVENT_LC_PORT_SEL 0x460093 |
| #define regBIF1_PCIE_PERF_CNTL_EVENT_LC_PORT_SEL_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_CNTL_EVENT_CI_PORT_SEL 0x460094 |
| #define regBIF1_PCIE_PERF_CNTL_EVENT_CI_PORT_SEL_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK5 0x460096 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK5_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK5 0x460097 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK5_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK5 0x460098 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK5_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK6 0x460099 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK6_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK6 0x46009a |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK6_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK6 0x46009b |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK6_BASE_IDX 5 |
| #define regBIF1_PCIE_STRAP_F0 0x4600b0 |
| #define regBIF1_PCIE_STRAP_F0_BASE_IDX 5 |
| #define regBIF1_PCIE_STRAP_NTB 0x4600b1 |
| #define regBIF1_PCIE_STRAP_NTB_BASE_IDX 5 |
| #define regBIF1_PCIE_STRAP_MISC 0x4600c0 |
| #define regBIF1_PCIE_STRAP_MISC_BASE_IDX 5 |
| #define regBIF1_PCIE_STRAP_MISC2 0x4600c1 |
| #define regBIF1_PCIE_STRAP_MISC2_BASE_IDX 5 |
| #define regBIF1_PCIE_STRAP_PI 0x4600c2 |
| #define regBIF1_PCIE_STRAP_PI_BASE_IDX 5 |
| #define regBIF1_PCIE_STRAP_I2C_BD 0x4600c4 |
| #define regBIF1_PCIE_STRAP_I2C_BD_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_CLR 0x4600c8 |
| #define regBIF1_PCIE_PRBS_CLR_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_STATUS1 0x4600c9 |
| #define regBIF1_PCIE_PRBS_STATUS1_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_STATUS2 0x4600ca |
| #define regBIF1_PCIE_PRBS_STATUS2_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_FREERUN 0x4600cb |
| #define regBIF1_PCIE_PRBS_FREERUN_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_MISC 0x4600cc |
| #define regBIF1_PCIE_PRBS_MISC_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_USER_PATTERN 0x4600cd |
| #define regBIF1_PCIE_PRBS_USER_PATTERN_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_LO_BITCNT 0x4600ce |
| #define regBIF1_PCIE_PRBS_LO_BITCNT_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_HI_BITCNT 0x4600cf |
| #define regBIF1_PCIE_PRBS_HI_BITCNT_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_0 0x4600d0 |
| #define regBIF1_PCIE_PRBS_ERRCNT_0_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_1 0x4600d1 |
| #define regBIF1_PCIE_PRBS_ERRCNT_1_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_2 0x4600d2 |
| #define regBIF1_PCIE_PRBS_ERRCNT_2_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_3 0x4600d3 |
| #define regBIF1_PCIE_PRBS_ERRCNT_3_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_4 0x4600d4 |
| #define regBIF1_PCIE_PRBS_ERRCNT_4_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_5 0x4600d5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_5_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_6 0x4600d6 |
| #define regBIF1_PCIE_PRBS_ERRCNT_6_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_7 0x4600d7 |
| #define regBIF1_PCIE_PRBS_ERRCNT_7_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_8 0x4600d8 |
| #define regBIF1_PCIE_PRBS_ERRCNT_8_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_9 0x4600d9 |
| #define regBIF1_PCIE_PRBS_ERRCNT_9_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_10 0x4600da |
| #define regBIF1_PCIE_PRBS_ERRCNT_10_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_11 0x4600db |
| #define regBIF1_PCIE_PRBS_ERRCNT_11_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_12 0x4600dc |
| #define regBIF1_PCIE_PRBS_ERRCNT_12_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_13 0x4600dd |
| #define regBIF1_PCIE_PRBS_ERRCNT_13_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_14 0x4600de |
| #define regBIF1_PCIE_PRBS_ERRCNT_14_BASE_IDX 5 |
| #define regBIF1_PCIE_PRBS_ERRCNT_15 0x4600df |
| #define regBIF1_PCIE_PRBS_ERRCNT_15_BASE_IDX 5 |
| #define regBIF1_SWRST_COMMAND_STATUS 0x460100 |
| #define regBIF1_SWRST_COMMAND_STATUS_BASE_IDX 5 |
| #define regBIF1_SWRST_GENERAL_CONTROL 0x460101 |
| #define regBIF1_SWRST_GENERAL_CONTROL_BASE_IDX 5 |
| #define regBIF1_SWRST_COMMAND_0 0x460102 |
| #define regBIF1_SWRST_COMMAND_0_BASE_IDX 5 |
| #define regBIF1_SWRST_COMMAND_1 0x460103 |
| #define regBIF1_SWRST_COMMAND_1_BASE_IDX 5 |
| #define regBIF1_SWRST_CONTROL_0 0x460104 |
| #define regBIF1_SWRST_CONTROL_0_BASE_IDX 5 |
| #define regBIF1_SWRST_CONTROL_1 0x460105 |
| #define regBIF1_SWRST_CONTROL_1_BASE_IDX 5 |
| #define regBIF1_SWRST_CONTROL_2 0x460106 |
| #define regBIF1_SWRST_CONTROL_2_BASE_IDX 5 |
| #define regBIF1_SWRST_CONTROL_3 0x460107 |
| #define regBIF1_SWRST_CONTROL_3_BASE_IDX 5 |
| #define regBIF1_SWRST_CONTROL_4 0x460108 |
| #define regBIF1_SWRST_CONTROL_4_BASE_IDX 5 |
| #define regBIF1_SWRST_CONTROL_5 0x460109 |
| #define regBIF1_SWRST_CONTROL_5_BASE_IDX 5 |
| #define regBIF1_SWRST_CONTROL_6 0x46010a |
| #define regBIF1_SWRST_CONTROL_6_BASE_IDX 5 |
| #define regBIF1_SWRST_EP_COMMAND_0 0x46010b |
| #define regBIF1_SWRST_EP_COMMAND_0_BASE_IDX 5 |
| #define regBIF1_SWRST_EP_CONTROL_0 0x46010c |
| #define regBIF1_SWRST_EP_CONTROL_0_BASE_IDX 5 |
| #define regBIF1_CPM_CONTROL 0x460118 |
| #define regBIF1_CPM_CONTROL_BASE_IDX 5 |
| #define regBIF1_CPM_SPLIT_CONTROL 0x460119 |
| #define regBIF1_CPM_SPLIT_CONTROL_BASE_IDX 5 |
| #define regBIF1_CPM_CONTROL_EXT 0x46011a |
| #define regBIF1_CPM_CONTROL_EXT_BASE_IDX 5 |
| #define regBIF1_SMN_APERTURE_ID_A 0x46011d |
| #define regBIF1_SMN_APERTURE_ID_A_BASE_IDX 5 |
| #define regBIF1_SMN_APERTURE_ID_B 0x46011e |
| #define regBIF1_SMN_APERTURE_ID_B_BASE_IDX 5 |
| #define regBIF1_LNCNT_CONTROL 0x460125 |
| #define regBIF1_LNCNT_CONTROL_BASE_IDX 5 |
| #define regBIF1_SMU_HP_STATUS_UPDATE 0x46012c |
| #define regBIF1_SMU_HP_STATUS_UPDATE_BASE_IDX 5 |
| #define regBIF1_HP_SMU_COMMAND_UPDATE 0x46012d |
| #define regBIF1_HP_SMU_COMMAND_UPDATE_BASE_IDX 5 |
| #define regBIF1_SMU_HP_END_OF_INTERRUPT 0x46012e |
| #define regBIF1_SMU_HP_END_OF_INTERRUPT_BASE_IDX 5 |
| #define regBIF1_SMU_INT_PIN_SHARING_PORT_INDICATOR 0x46012f |
| #define regBIF1_SMU_INT_PIN_SHARING_PORT_INDICATOR_BASE_IDX 5 |
| #define regBIF1_PCIE_PGMST_CNTL 0x460130 |
| #define regBIF1_PCIE_PGMST_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_PGSLV_CNTL 0x460131 |
| #define regBIF1_PCIE_PGSLV_CNTL_BASE_IDX 5 |
| #define regBIF1_LC_CPM_CONTROL_0 0x460133 |
| #define regBIF1_LC_CPM_CONTROL_0_BASE_IDX 5 |
| #define regBIF1_LC_CPM_CONTROL_1 0x460134 |
| #define regBIF1_LC_CPM_CONTROL_1_BASE_IDX 5 |
| #define regBIF1_PCIE_RXMARGIN_CONTROL_CAPABILITIES 0x460135 |
| #define regBIF1_PCIE_RXMARGIN_CONTROL_CAPABILITIES_BASE_IDX 5 |
| #define regBIF1_PCIE_RXMARGIN_1_SETTINGS 0x460136 |
| #define regBIF1_PCIE_RXMARGIN_1_SETTINGS_BASE_IDX 5 |
| #define regBIF1_PCIE_RXMARGIN_2_SETTINGS 0x460137 |
| #define regBIF1_PCIE_RXMARGIN_2_SETTINGS_BASE_IDX 5 |
| #define regBIF1_PCIE_PRESENCE_DETECT_SELECT 0x460138 |
| #define regBIF1_PCIE_PRESENCE_DETECT_SELECT_BASE_IDX 5 |
| #define regBIF1_PCIE_LC_DEBUG_CNTL 0x460139 |
| #define regBIF1_PCIE_LC_DEBUG_CNTL_BASE_IDX 5 |
| #define regBIF1_SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO 0x46013a |
| #define regBIF1_SMU_INT_PIN_SHARING_PORT_INDICATOR_TWO_BASE_IDX 5 |
| #define regBIF1_PCIE_TX_LAST_TLP0 0x460180 |
| #define regBIF1_PCIE_TX_LAST_TLP0_BASE_IDX 5 |
| #define regBIF1_PCIE_TX_LAST_TLP1 0x460181 |
| #define regBIF1_PCIE_TX_LAST_TLP1_BASE_IDX 5 |
| #define regBIF1_PCIE_TX_LAST_TLP2 0x460182 |
| #define regBIF1_PCIE_TX_LAST_TLP2_BASE_IDX 5 |
| #define regBIF1_PCIE_TX_LAST_TLP3 0x460183 |
| #define regBIF1_PCIE_TX_LAST_TLP3_BASE_IDX 5 |
| #define regBIF1_PCIE_TX_TRACKING_ADDR_LO 0x460184 |
| #define regBIF1_PCIE_TX_TRACKING_ADDR_LO_BASE_IDX 5 |
| #define regBIF1_PCIE_TX_TRACKING_ADDR_HI 0x460185 |
| #define regBIF1_PCIE_TX_TRACKING_ADDR_HI_BASE_IDX 5 |
| #define regBIF1_PCIE_TX_TRACKING_CTRL_STATUS 0x460186 |
| #define regBIF1_PCIE_TX_TRACKING_CTRL_STATUS_BASE_IDX 5 |
| #define regBIF1_PCIE_TX_CTRL_4 0x46018b |
| #define regBIF1_PCIE_TX_CTRL_4_BASE_IDX 5 |
| #define regBIF1_PCIE_TX_STATUS 0x460194 |
| #define regBIF1_PCIE_TX_STATUS_BASE_IDX 5 |
| #define regBIF1_PCIE_TX_F0_ATTR_CNTL 0x46019c |
| #define regBIF1_PCIE_TX_F0_ATTR_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_TX_SWUS_ATTR_CNTL 0x46019d |
| #define regBIF1_PCIE_TX_SWUS_ATTR_CNTL_BASE_IDX 5 |
| #define regBIF1_PCIE_BW_BY_UNITID 0x4601c0 |
| #define regBIF1_PCIE_BW_BY_UNITID_BASE_IDX 5 |
| #define regBIF1_PCIE_MST_CTRL_1 0x4601c4 |
| #define regBIF1_PCIE_MST_CTRL_1_BASE_IDX 5 |
| #define regBIF1_PCIE_HIP_REG0 0x4601e0 |
| #define regBIF1_PCIE_HIP_REG0_BASE_IDX 5 |
| #define regBIF1_PCIE_HIP_REG1 0x4601e1 |
| #define regBIF1_PCIE_HIP_REG1_BASE_IDX 5 |
| #define regBIF1_PCIE_HIP_REG2 0x4601e2 |
| #define regBIF1_PCIE_HIP_REG2_BASE_IDX 5 |
| #define regBIF1_PCIE_HIP_REG3 0x4601e3 |
| #define regBIF1_PCIE_HIP_REG3_BASE_IDX 5 |
| #define regBIF1_PCIE_HIP_REG4 0x4601e4 |
| #define regBIF1_PCIE_HIP_REG4_BASE_IDX 5 |
| #define regBIF1_PCIE_HIP_REG5 0x4601e5 |
| #define regBIF1_PCIE_HIP_REG5_BASE_IDX 5 |
| #define regBIF1_PCIE_HIP_REG6 0x4601e6 |
| #define regBIF1_PCIE_HIP_REG6_BASE_IDX 5 |
| #define regBIF1_PCIE_HIP_REG7 0x4601e7 |
| #define regBIF1_PCIE_HIP_REG7_BASE_IDX 5 |
| #define regBIF1_PCIE_HIP_REG8 0x4601e8 |
| #define regBIF1_PCIE_HIP_REG8_BASE_IDX 5 |
| #define regBIF1_SMU_PCIE_FENCED1_REG 0x460200 |
| #define regBIF1_SMU_PCIE_FENCED1_REG_BASE_IDX 5 |
| #define regBIF1_SMU_PCIE_FENCED2_REG 0x460201 |
| #define regBIF1_SMU_PCIE_FENCED2_REG_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK7 0x460222 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK7_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK7 0x460223 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK7_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK7 0x460224 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK7_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK8 0x460225 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK8_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK8 0x460226 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK8_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK8 0x460227 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK8_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK9 0x460228 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK9_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK9 0x460229 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK9_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK9 0x46022a |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK9_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK10 0x46022b |
| #define regBIF1_PCIE_PERF_CNTL_TXCLK10_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK10 0x46022c |
| #define regBIF1_PCIE_PERF_COUNT0_TXCLK10_BASE_IDX 5 |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK10 0x46022d |
| #define regBIF1_PCIE_PERF_COUNT1_TXCLK10_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec |
| // base address: 0x13b00000 |
| #define regNB_NBCFG0_NBCFG_SCRATCH_4 0xe8001e |
| #define regNB_NBCFG0_NBCFG_SCRATCH_4_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_iohub_nb_fastreg_fastreg_cfgdec |
| // base address: 0x13b07000 |
| #define regFASTREG_APERTURE 0xe81c00 |
| #define regFASTREG_APERTURE_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_iohub_nb_misc_misc_cfgdec |
| // base address: 0x13b10000 |
| #define regNB_CNTL 0xe84000 |
| #define regNB_CNTL_BASE_IDX 5 |
| #define regNB_SPARE1 0xe84003 |
| #define regNB_SPARE1_BASE_IDX 5 |
| #define regNB_SPARE2 0xe84004 |
| #define regNB_SPARE2_BASE_IDX 5 |
| #define regNB_REVID 0xe84005 |
| #define regNB_REVID_BASE_IDX 5 |
| #define regNBIO_LCLK_DS_MASK 0xe84009 |
| #define regNBIO_LCLK_DS_MASK_BASE_IDX 5 |
| #define regNB_BUS_NUM_CNTL 0xe84011 |
| #define regNB_BUS_NUM_CNTL_BASE_IDX 5 |
| #define regNB_MMIOBASE 0xe84017 |
| #define regNB_MMIOBASE_BASE_IDX 5 |
| #define regNB_MMIOLIMIT 0xe84018 |
| #define regNB_MMIOLIMIT_BASE_IDX 5 |
| #define regNB_LOWER_TOP_OF_DRAM2 0xe84019 |
| #define regNB_LOWER_TOP_OF_DRAM2_BASE_IDX 5 |
| #define regNB_UPPER_TOP_OF_DRAM2 0xe8401a |
| #define regNB_UPPER_TOP_OF_DRAM2_BASE_IDX 5 |
| #define regNB_LOWER_DRAM2_BASE 0xe8401b |
| #define regNB_LOWER_DRAM2_BASE_BASE_IDX 5 |
| #define regNB_UPPER_DRAM2_BASE 0xe8401c |
| #define regNB_UPPER_DRAM2_BASE_BASE_IDX 5 |
| #define regSB_LOCATION 0xe8401f |
| #define regSB_LOCATION_BASE_IDX 5 |
| #define regSW_US_LOCATION 0xe84020 |
| #define regSW_US_LOCATION_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr0 0xe8402e |
| #define regNB_PROG_DEVICE_REMAP_PBr0_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr1 0xe8402f |
| #define regNB_PROG_DEVICE_REMAP_PBr1_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr2 0xe84030 |
| #define regNB_PROG_DEVICE_REMAP_PBr2_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr3 0xe84031 |
| #define regNB_PROG_DEVICE_REMAP_PBr3_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr4 0xe84032 |
| #define regNB_PROG_DEVICE_REMAP_PBr4_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr5 0xe84033 |
| #define regNB_PROG_DEVICE_REMAP_PBr5_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr6 0xe84034 |
| #define regNB_PROG_DEVICE_REMAP_PBr6_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr7 0xe84035 |
| #define regNB_PROG_DEVICE_REMAP_PBr7_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr8 0xe84036 |
| #define regNB_PROG_DEVICE_REMAP_PBr8_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr10 0xe84038 |
| #define regNB_PROG_DEVICE_REMAP_PBr10_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr11 0xe84039 |
| #define regNB_PROG_DEVICE_REMAP_PBr11_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr12 0xe8403a |
| #define regNB_PROG_DEVICE_REMAP_PBr12_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr13 0xe8403b |
| #define regNB_PROG_DEVICE_REMAP_PBr13_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr14 0xe8403c |
| #define regNB_PROG_DEVICE_REMAP_PBr14_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr15 0xe8403d |
| #define regNB_PROG_DEVICE_REMAP_PBr15_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr16 0xe8403e |
| #define regNB_PROG_DEVICE_REMAP_PBr16_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr17 0xe8403f |
| #define regNB_PROG_DEVICE_REMAP_PBr17_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr18 0xe84040 |
| #define regNB_PROG_DEVICE_REMAP_PBr18_BASE_IDX 5 |
| #define regNB_PROG_DEVICE_REMAP_PBr19 0xe84041 |
| #define regNB_PROG_DEVICE_REMAP_PBr19_BASE_IDX 5 |
| #define regSW_NMI_CNTL 0xe84042 |
| #define regSW_NMI_CNTL_BASE_IDX 5 |
| #define regSW_SMI_CNTL 0xe84043 |
| #define regSW_SMI_CNTL_BASE_IDX 5 |
| #define regSW_SCI_CNTL 0xe84044 |
| #define regSW_SCI_CNTL_BASE_IDX 5 |
| #define regAPML_SW_STATUS 0xe84045 |
| #define regAPML_SW_STATUS_BASE_IDX 5 |
| #define regSW_GIC_SPI_CNTL 0xe84047 |
| #define regSW_GIC_SPI_CNTL_BASE_IDX 5 |
| #define regSW_SYNCFLOOD_CNTL 0xe84049 |
| #define regSW_SYNCFLOOD_CNTL_BASE_IDX 5 |
| #define regNB_TOP_OF_DRAM3 0xe8404e |
| #define regNB_TOP_OF_DRAM3_BASE_IDX 5 |
| #define regCAM_CONTROL 0xe84052 |
| #define regCAM_CONTROL_BASE_IDX 5 |
| #define regCAM_TARGET_INDEX_ADDR_BOTTOM 0xe84053 |
| #define regCAM_TARGET_INDEX_ADDR_BOTTOM_BASE_IDX 5 |
| #define regCAM_TARGET_INDEX_ADDR_TOP 0xe84054 |
| #define regCAM_TARGET_INDEX_ADDR_TOP_BASE_IDX 5 |
| #define regCAM_TARGET_INDEX_DATA 0xe84055 |
| #define regCAM_TARGET_INDEX_DATA_BASE_IDX 5 |
| #define regCAM_TARGET_INDEX_DATA_MASK 0xe84056 |
| #define regCAM_TARGET_INDEX_DATA_MASK_BASE_IDX 5 |
| #define regCAM_TARGET_DATA_ADDR_BOTTOM 0xe84057 |
| #define regCAM_TARGET_DATA_ADDR_BOTTOM_BASE_IDX 5 |
| #define regCAM_TARGET_DATA_ADDR_TOP 0xe84059 |
| #define regCAM_TARGET_DATA_ADDR_TOP_BASE_IDX 5 |
| #define regCAM_TARGET_DATA 0xe8405a |
| #define regCAM_TARGET_DATA_BASE_IDX 5 |
| #define regCAM_TARGET_DATA_MASK 0xe8405b |
| #define regCAM_TARGET_DATA_MASK_BASE_IDX 5 |
| #define regP_DMA_DROPPED_LOG_LOWER 0xe84060 |
| #define regP_DMA_DROPPED_LOG_LOWER_BASE_IDX 5 |
| #define regP_DMA_DROPPED_LOG_UPPER 0xe84061 |
| #define regP_DMA_DROPPED_LOG_UPPER_BASE_IDX 5 |
| #define regNP_DMA_DROPPED_LOG_LOWER 0xe84062 |
| #define regNP_DMA_DROPPED_LOG_LOWER_BASE_IDX 5 |
| #define regNP_DMA_DROPPED_LOG_UPPER 0xe84063 |
| #define regNP_DMA_DROPPED_LOG_UPPER_BASE_IDX 5 |
| #define regPCIE_VDM_NODE0_CTRL4 0xe84064 |
| #define regPCIE_VDM_NODE0_CTRL4_BASE_IDX 5 |
| #define regPCIE_VDM_CNTL2 0xe8408c |
| #define regPCIE_VDM_CNTL2_BASE_IDX 5 |
| #define regPCIE_VDM_CNTL3 0xe8408d |
| #define regPCIE_VDM_CNTL3_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT0_0 0xe84090 |
| #define regSTALL_CONTROL_XBARPORT0_0_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT0_1 0xe84091 |
| #define regSTALL_CONTROL_XBARPORT0_1_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT1_0 0xe84093 |
| #define regSTALL_CONTROL_XBARPORT1_0_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT1_1 0xe84094 |
| #define regSTALL_CONTROL_XBARPORT1_1_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT2_0 0xe84096 |
| #define regSTALL_CONTROL_XBARPORT2_0_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT2_1 0xe84097 |
| #define regSTALL_CONTROL_XBARPORT2_1_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT3_0 0xe84099 |
| #define regSTALL_CONTROL_XBARPORT3_0_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT3_1 0xe8409a |
| #define regSTALL_CONTROL_XBARPORT3_1_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT4_0 0xe8409c |
| #define regSTALL_CONTROL_XBARPORT4_0_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT4_1 0xe8409d |
| #define regSTALL_CONTROL_XBARPORT4_1_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT5_0 0xe8409f |
| #define regSTALL_CONTROL_XBARPORT5_0_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT5_1 0xe840a0 |
| #define regSTALL_CONTROL_XBARPORT5_1_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT6_0 0xe840a2 |
| #define regSTALL_CONTROL_XBARPORT6_0_BASE_IDX 5 |
| #define regSTALL_CONTROL_XBARPORT6_1 0xe840a3 |
| #define regSTALL_CONTROL_XBARPORT6_1_BASE_IDX 5 |
| #define regNB_DRAM3_BASE 0xe840b1 |
| #define regNB_DRAM3_BASE_BASE_IDX 5 |
| #define regSMU_BASE_ADDR_LO 0xe840ba |
| #define regSMU_BASE_ADDR_LO_BASE_IDX 5 |
| #define regSMU_BASE_ADDR_HI 0xe840bb |
| #define regSMU_BASE_ADDR_HI_BASE_IDX 5 |
| #define regFASTREG_BASE_ADDR_LO 0xe840c0 |
| #define regFASTREG_BASE_ADDR_LO_BASE_IDX 5 |
| #define regFASTREG_BASE_ADDR_HI 0xe840c1 |
| #define regFASTREG_BASE_ADDR_HI_BASE_IDX 5 |
| #define regFASTREGCNTL_BASE_ADDR_LO 0xe840c2 |
| #define regFASTREGCNTL_BASE_ADDR_LO_BASE_IDX 5 |
| #define regFASTREGCNTL_BASE_ADDR_HI 0xe840c3 |
| #define regFASTREGCNTL_BASE_ADDR_HI_BASE_IDX 5 |
| #define regSCRATCH_4 0xe840fc |
| #define regSCRATCH_4_BASE_IDX 5 |
| #define regSCRATCH_5 0xe840fd |
| #define regSCRATCH_5_BASE_IDX 5 |
| #define regSMU_BLOCK_CPU 0xe840fe |
| #define regSMU_BLOCK_CPU_BASE_IDX 5 |
| #define regSMU_BLOCK_CPU_STATUS 0xe840ff |
| #define regSMU_BLOCK_CPU_STATUS_BASE_IDX 5 |
| #define regTRAP_STATUS 0xe84100 |
| #define regTRAP_STATUS_BASE_IDX 5 |
| #define regTRAP_REQUEST0 0xe84101 |
| #define regTRAP_REQUEST0_BASE_IDX 5 |
| #define regTRAP_REQUEST1 0xe84102 |
| #define regTRAP_REQUEST1_BASE_IDX 5 |
| #define regTRAP_REQUEST2 0xe84103 |
| #define regTRAP_REQUEST2_BASE_IDX 5 |
| #define regTRAP_REQUEST3 0xe84104 |
| #define regTRAP_REQUEST3_BASE_IDX 5 |
| #define regTRAP_REQUEST4 0xe84105 |
| #define regTRAP_REQUEST4_BASE_IDX 5 |
| #define regTRAP_REQUEST5 0xe84106 |
| #define regTRAP_REQUEST5_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATASTRB0 0xe84108 |
| #define regTRAP_REQUEST_DATASTRB0_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATASTRB1 0xe84109 |
| #define regTRAP_REQUEST_DATASTRB1_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA0 0xe84110 |
| #define regTRAP_REQUEST_DATA0_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA1 0xe84111 |
| #define regTRAP_REQUEST_DATA1_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA2 0xe84112 |
| #define regTRAP_REQUEST_DATA2_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA3 0xe84113 |
| #define regTRAP_REQUEST_DATA3_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA4 0xe84114 |
| #define regTRAP_REQUEST_DATA4_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA5 0xe84115 |
| #define regTRAP_REQUEST_DATA5_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA6 0xe84116 |
| #define regTRAP_REQUEST_DATA6_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA7 0xe84117 |
| #define regTRAP_REQUEST_DATA7_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA8 0xe84118 |
| #define regTRAP_REQUEST_DATA8_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA9 0xe84119 |
| #define regTRAP_REQUEST_DATA9_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA10 0xe8411a |
| #define regTRAP_REQUEST_DATA10_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA11 0xe8411b |
| #define regTRAP_REQUEST_DATA11_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA12 0xe8411c |
| #define regTRAP_REQUEST_DATA12_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA13 0xe8411d |
| #define regTRAP_REQUEST_DATA13_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA14 0xe8411e |
| #define regTRAP_REQUEST_DATA14_BASE_IDX 5 |
| #define regTRAP_REQUEST_DATA15 0xe8411f |
| #define regTRAP_REQUEST_DATA15_BASE_IDX 5 |
| #define regTRAP_RESPONSE_CONTROL 0xe84130 |
| #define regTRAP_RESPONSE_CONTROL_BASE_IDX 5 |
| #define regTRAP_RESPONSE0 0xe84131 |
| #define regTRAP_RESPONSE0_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA0 0xe84140 |
| #define regTRAP_RESPONSE_DATA0_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA1 0xe84141 |
| #define regTRAP_RESPONSE_DATA1_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA2 0xe84142 |
| #define regTRAP_RESPONSE_DATA2_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA3 0xe84143 |
| #define regTRAP_RESPONSE_DATA3_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA4 0xe84144 |
| #define regTRAP_RESPONSE_DATA4_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA5 0xe84145 |
| #define regTRAP_RESPONSE_DATA5_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA6 0xe84146 |
| #define regTRAP_RESPONSE_DATA6_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA7 0xe84147 |
| #define regTRAP_RESPONSE_DATA7_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA8 0xe84148 |
| #define regTRAP_RESPONSE_DATA8_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA9 0xe84149 |
| #define regTRAP_RESPONSE_DATA9_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA10 0xe8414a |
| #define regTRAP_RESPONSE_DATA10_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA11 0xe8414b |
| #define regTRAP_RESPONSE_DATA11_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA12 0xe8414c |
| #define regTRAP_RESPONSE_DATA12_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA13 0xe8414d |
| #define regTRAP_RESPONSE_DATA13_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA14 0xe8414e |
| #define regTRAP_RESPONSE_DATA14_BASE_IDX 5 |
| #define regTRAP_RESPONSE_DATA15 0xe8414f |
| #define regTRAP_RESPONSE_DATA15_BASE_IDX 5 |
| #define regTRAP0_CONTROL0 0xe84200 |
| #define regTRAP0_CONTROL0_BASE_IDX 5 |
| #define regTRAP0_ADDRESS_LO 0xe84202 |
| #define regTRAP0_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP0_ADDRESS_HI 0xe84203 |
| #define regTRAP0_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP0_COMMAND 0xe84204 |
| #define regTRAP0_COMMAND_BASE_IDX 5 |
| #define regTRAP0_ADDRESS_LO_MASK 0xe84206 |
| #define regTRAP0_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP0_ADDRESS_HI_MASK 0xe84207 |
| #define regTRAP0_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP0_COMMAND_MASK 0xe84208 |
| #define regTRAP0_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP1_CONTROL0 0xe84210 |
| #define regTRAP1_CONTROL0_BASE_IDX 5 |
| #define regTRAP1_ADDRESS_LO 0xe84212 |
| #define regTRAP1_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP1_ADDRESS_HI 0xe84213 |
| #define regTRAP1_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP1_COMMAND 0xe84214 |
| #define regTRAP1_COMMAND_BASE_IDX 5 |
| #define regTRAP1_ADDRESS_LO_MASK 0xe84216 |
| #define regTRAP1_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP1_ADDRESS_HI_MASK 0xe84217 |
| #define regTRAP1_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP1_COMMAND_MASK 0xe84218 |
| #define regTRAP1_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP2_CONTROL0 0xe84220 |
| #define regTRAP2_CONTROL0_BASE_IDX 5 |
| #define regTRAP2_ADDRESS_LO 0xe84222 |
| #define regTRAP2_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP2_ADDRESS_HI 0xe84223 |
| #define regTRAP2_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP2_COMMAND 0xe84224 |
| #define regTRAP2_COMMAND_BASE_IDX 5 |
| #define regTRAP2_ADDRESS_LO_MASK 0xe84226 |
| #define regTRAP2_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP2_ADDRESS_HI_MASK 0xe84227 |
| #define regTRAP2_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP2_COMMAND_MASK 0xe84228 |
| #define regTRAP2_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP3_CONTROL0 0xe84230 |
| #define regTRAP3_CONTROL0_BASE_IDX 5 |
| #define regTRAP3_ADDRESS_LO 0xe84232 |
| #define regTRAP3_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP3_ADDRESS_HI 0xe84233 |
| #define regTRAP3_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP3_COMMAND 0xe84234 |
| #define regTRAP3_COMMAND_BASE_IDX 5 |
| #define regTRAP3_ADDRESS_LO_MASK 0xe84236 |
| #define regTRAP3_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP3_ADDRESS_HI_MASK 0xe84237 |
| #define regTRAP3_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP3_COMMAND_MASK 0xe84238 |
| #define regTRAP3_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP4_CONTROL0 0xe84240 |
| #define regTRAP4_CONTROL0_BASE_IDX 5 |
| #define regTRAP4_ADDRESS_LO 0xe84242 |
| #define regTRAP4_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP4_ADDRESS_HI 0xe84243 |
| #define regTRAP4_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP4_COMMAND 0xe84244 |
| #define regTRAP4_COMMAND_BASE_IDX 5 |
| #define regTRAP4_ADDRESS_LO_MASK 0xe84246 |
| #define regTRAP4_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP4_ADDRESS_HI_MASK 0xe84247 |
| #define regTRAP4_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP4_COMMAND_MASK 0xe84248 |
| #define regTRAP4_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP5_CONTROL0 0xe84250 |
| #define regTRAP5_CONTROL0_BASE_IDX 5 |
| #define regTRAP5_ADDRESS_LO 0xe84252 |
| #define regTRAP5_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP5_ADDRESS_HI 0xe84253 |
| #define regTRAP5_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP5_COMMAND 0xe84254 |
| #define regTRAP5_COMMAND_BASE_IDX 5 |
| #define regTRAP5_ADDRESS_LO_MASK 0xe84256 |
| #define regTRAP5_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP5_ADDRESS_HI_MASK 0xe84257 |
| #define regTRAP5_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP5_COMMAND_MASK 0xe84258 |
| #define regTRAP5_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP6_CONTROL0 0xe84260 |
| #define regTRAP6_CONTROL0_BASE_IDX 5 |
| #define regTRAP6_ADDRESS_LO 0xe84262 |
| #define regTRAP6_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP6_ADDRESS_HI 0xe84263 |
| #define regTRAP6_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP6_COMMAND 0xe84264 |
| #define regTRAP6_COMMAND_BASE_IDX 5 |
| #define regTRAP6_ADDRESS_LO_MASK 0xe84266 |
| #define regTRAP6_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP6_ADDRESS_HI_MASK 0xe84267 |
| #define regTRAP6_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP6_COMMAND_MASK 0xe84268 |
| #define regTRAP6_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP7_CONTROL0 0xe84270 |
| #define regTRAP7_CONTROL0_BASE_IDX 5 |
| #define regTRAP7_ADDRESS_LO 0xe84272 |
| #define regTRAP7_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP7_ADDRESS_HI 0xe84273 |
| #define regTRAP7_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP7_COMMAND 0xe84274 |
| #define regTRAP7_COMMAND_BASE_IDX 5 |
| #define regTRAP7_ADDRESS_LO_MASK 0xe84276 |
| #define regTRAP7_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP7_ADDRESS_HI_MASK 0xe84277 |
| #define regTRAP7_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP7_COMMAND_MASK 0xe84278 |
| #define regTRAP7_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP8_CONTROL0 0xe84280 |
| #define regTRAP8_CONTROL0_BASE_IDX 5 |
| #define regTRAP8_ADDRESS_LO 0xe84282 |
| #define regTRAP8_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP8_ADDRESS_HI 0xe84283 |
| #define regTRAP8_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP8_COMMAND 0xe84284 |
| #define regTRAP8_COMMAND_BASE_IDX 5 |
| #define regTRAP8_ADDRESS_LO_MASK 0xe84286 |
| #define regTRAP8_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP8_ADDRESS_HI_MASK 0xe84287 |
| #define regTRAP8_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP8_COMMAND_MASK 0xe84288 |
| #define regTRAP8_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP9_CONTROL0 0xe84290 |
| #define regTRAP9_CONTROL0_BASE_IDX 5 |
| #define regTRAP9_ADDRESS_LO 0xe84292 |
| #define regTRAP9_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP9_ADDRESS_HI 0xe84293 |
| #define regTRAP9_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP9_COMMAND 0xe84294 |
| #define regTRAP9_COMMAND_BASE_IDX 5 |
| #define regTRAP9_ADDRESS_LO_MASK 0xe84296 |
| #define regTRAP9_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP9_ADDRESS_HI_MASK 0xe84297 |
| #define regTRAP9_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP9_COMMAND_MASK 0xe84298 |
| #define regTRAP9_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP10_CONTROL0 0xe842a0 |
| #define regTRAP10_CONTROL0_BASE_IDX 5 |
| #define regTRAP10_ADDRESS_LO 0xe842a2 |
| #define regTRAP10_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP10_ADDRESS_HI 0xe842a3 |
| #define regTRAP10_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP10_COMMAND 0xe842a4 |
| #define regTRAP10_COMMAND_BASE_IDX 5 |
| #define regTRAP10_ADDRESS_LO_MASK 0xe842a6 |
| #define regTRAP10_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP10_ADDRESS_HI_MASK 0xe842a7 |
| #define regTRAP10_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP10_COMMAND_MASK 0xe842a8 |
| #define regTRAP10_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP11_CONTROL0 0xe842b0 |
| #define regTRAP11_CONTROL0_BASE_IDX 5 |
| #define regTRAP11_ADDRESS_LO 0xe842b2 |
| #define regTRAP11_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP11_ADDRESS_HI 0xe842b3 |
| #define regTRAP11_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP11_COMMAND 0xe842b4 |
| #define regTRAP11_COMMAND_BASE_IDX 5 |
| #define regTRAP11_ADDRESS_LO_MASK 0xe842b6 |
| #define regTRAP11_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP11_ADDRESS_HI_MASK 0xe842b7 |
| #define regTRAP11_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP11_COMMAND_MASK 0xe842b8 |
| #define regTRAP11_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP12_CONTROL0 0xe842c0 |
| #define regTRAP12_CONTROL0_BASE_IDX 5 |
| #define regTRAP12_ADDRESS_LO 0xe842c2 |
| #define regTRAP12_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP12_ADDRESS_HI 0xe842c3 |
| #define regTRAP12_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP12_COMMAND 0xe842c4 |
| #define regTRAP12_COMMAND_BASE_IDX 5 |
| #define regTRAP12_ADDRESS_LO_MASK 0xe842c6 |
| #define regTRAP12_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP12_ADDRESS_HI_MASK 0xe842c7 |
| #define regTRAP12_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP12_COMMAND_MASK 0xe842c8 |
| #define regTRAP12_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP13_CONTROL0 0xe842d0 |
| #define regTRAP13_CONTROL0_BASE_IDX 5 |
| #define regTRAP13_ADDRESS_LO 0xe842d2 |
| #define regTRAP13_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP13_ADDRESS_HI 0xe842d3 |
| #define regTRAP13_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP13_COMMAND 0xe842d4 |
| #define regTRAP13_COMMAND_BASE_IDX 5 |
| #define regTRAP13_ADDRESS_LO_MASK 0xe842d6 |
| #define regTRAP13_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP13_ADDRESS_HI_MASK 0xe842d7 |
| #define regTRAP13_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP13_COMMAND_MASK 0xe842d8 |
| #define regTRAP13_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP14_CONTROL0 0xe842e0 |
| #define regTRAP14_CONTROL0_BASE_IDX 5 |
| #define regTRAP14_ADDRESS_LO 0xe842e2 |
| #define regTRAP14_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP14_ADDRESS_HI 0xe842e3 |
| #define regTRAP14_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP14_COMMAND 0xe842e4 |
| #define regTRAP14_COMMAND_BASE_IDX 5 |
| #define regTRAP14_ADDRESS_LO_MASK 0xe842e6 |
| #define regTRAP14_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP14_ADDRESS_HI_MASK 0xe842e7 |
| #define regTRAP14_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP14_COMMAND_MASK 0xe842e8 |
| #define regTRAP14_COMMAND_MASK_BASE_IDX 5 |
| #define regTRAP15_CONTROL0 0xe842f0 |
| #define regTRAP15_CONTROL0_BASE_IDX 5 |
| #define regTRAP15_ADDRESS_LO 0xe842f2 |
| #define regTRAP15_ADDRESS_LO_BASE_IDX 5 |
| #define regTRAP15_ADDRESS_HI 0xe842f3 |
| #define regTRAP15_ADDRESS_HI_BASE_IDX 5 |
| #define regTRAP15_COMMAND 0xe842f4 |
| #define regTRAP15_COMMAND_BASE_IDX 5 |
| #define regTRAP15_ADDRESS_LO_MASK 0xe842f6 |
| #define regTRAP15_ADDRESS_LO_MASK_BASE_IDX 5 |
| #define regTRAP15_ADDRESS_HI_MASK 0xe842f7 |
| #define regTRAP15_ADDRESS_HI_MASK_BASE_IDX 5 |
| #define regTRAP15_COMMAND_MASK 0xe842f8 |
| #define regTRAP15_COMMAND_MASK_BASE_IDX 5 |
| #define regSB_COMMAND 0xe85000 |
| #define regSB_COMMAND_BASE_IDX 5 |
| #define regSB_SUB_BUS_NUMBER_LATENCY 0xe85001 |
| #define regSB_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regSB_IO_BASE_LIMIT 0xe85002 |
| #define regSB_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regSB_MEM_BASE_LIMIT 0xe85003 |
| #define regSB_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regSB_PREF_BASE_LIMIT 0xe85004 |
| #define regSB_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regSB_PREF_BASE_UPPER 0xe85005 |
| #define regSB_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regSB_PREF_LIMIT_UPPER 0xe85006 |
| #define regSB_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regSB_IO_BASE_LIMIT_HI 0xe85007 |
| #define regSB_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regSB_IRQ_BRIDGE_CNTL 0xe85008 |
| #define regSB_IRQ_BRIDGE_CNTL_BASE_IDX 5 |
| #define regSB_EXT_BRIDGE_CNTL 0xe85009 |
| #define regSB_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regSB_PMI_STATUS_CNTL 0xe8500a |
| #define regSB_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regSB_SLOT_CAP 0xe8500b |
| #define regSB_SLOT_CAP_BASE_IDX 5 |
| #define regSB_ROOT_CNTL 0xe8500c |
| #define regSB_ROOT_CNTL_BASE_IDX 5 |
| #define regSB_DEVICE_CNTL2 0xe8500d |
| #define regSB_DEVICE_CNTL2_BASE_IDX 5 |
| #define regMCA_SMN_INT_REQ_ADDR 0xe85020 |
| #define regMCA_SMN_INT_REQ_ADDR_BASE_IDX 5 |
| #define regMCA_SMN_INT_MCM_ADDR 0xe85021 |
| #define regMCA_SMN_INT_MCM_ADDR_BASE_IDX 5 |
| #define regMCA_SMN_INT_APERTUREID 0xe85022 |
| #define regMCA_SMN_INT_APERTUREID_BASE_IDX 5 |
| #define regMCA_SMN_INT_CONTROL 0xe85023 |
| #define regMCA_SMN_INT_CONTROL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec |
| // base address: 0x13b20000 |
| #define regPARITY_CONTROL_0 0xe88000 |
| #define regPARITY_CONTROL_0_BASE_IDX 5 |
| #define regPARITY_CONTROL_1 0xe88001 |
| #define regPARITY_CONTROL_1_BASE_IDX 5 |
| #define regPARITY_SEVERITY_CONTROL_UNCORR_0 0xe88002 |
| #define regPARITY_SEVERITY_CONTROL_UNCORR_0_BASE_IDX 5 |
| #define regPARITY_SEVERITY_CONTROL_CORR_0 0xe88004 |
| #define regPARITY_SEVERITY_CONTROL_CORR_0_BASE_IDX 5 |
| #define regPARITY_SEVERITY_CONTROL_UCP_0 0xe88006 |
| #define regPARITY_SEVERITY_CONTROL_UCP_0_BASE_IDX 5 |
| #define regRAS_GLOBAL_STATUS_LO 0xe88008 |
| #define regRAS_GLOBAL_STATUS_LO_BASE_IDX 5 |
| #define regRAS_GLOBAL_STATUS_HI 0xe88009 |
| #define regRAS_GLOBAL_STATUS_HI_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP0 0xe8800a |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP0_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP1 0xe8800b |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP1_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP2 0xe8800c |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP2_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP3 0xe8800d |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP3_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP4 0xe8800e |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP4_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP5 0xe8800f |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP5_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP6 0xe88010 |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP6_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP7 0xe88011 |
| #define regPARITY_ERROR_STATUS_UNCORR_GRP7_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_CORR_GRP0 0xe88014 |
| #define regPARITY_ERROR_STATUS_CORR_GRP0_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_CORR_GRP1 0xe88015 |
| #define regPARITY_ERROR_STATUS_CORR_GRP1_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_CORR_GRP2 0xe88016 |
| #define regPARITY_ERROR_STATUS_CORR_GRP2_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_CORR_GRP3 0xe88017 |
| #define regPARITY_ERROR_STATUS_CORR_GRP3_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_CORR_GRP4 0xe88018 |
| #define regPARITY_ERROR_STATUS_CORR_GRP4_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_CORR_GRP5 0xe88019 |
| #define regPARITY_ERROR_STATUS_CORR_GRP5_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_CORR_GRP6 0xe8801a |
| #define regPARITY_ERROR_STATUS_CORR_GRP6_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_CORR_GRP7 0xe8801b |
| #define regPARITY_ERROR_STATUS_CORR_GRP7_BASE_IDX 5 |
| #define regPARITY_COUNTER_CORR_GRP0 0xe8801e |
| #define regPARITY_COUNTER_CORR_GRP0_BASE_IDX 5 |
| #define regPARITY_COUNTER_CORR_GRP1 0xe8801f |
| #define regPARITY_COUNTER_CORR_GRP1_BASE_IDX 5 |
| #define regPARITY_COUNTER_CORR_GRP2 0xe88020 |
| #define regPARITY_COUNTER_CORR_GRP2_BASE_IDX 5 |
| #define regPARITY_COUNTER_CORR_GRP3 0xe88021 |
| #define regPARITY_COUNTER_CORR_GRP3_BASE_IDX 5 |
| #define regPARITY_COUNTER_CORR_GRP4 0xe88022 |
| #define regPARITY_COUNTER_CORR_GRP4_BASE_IDX 5 |
| #define regPARITY_COUNTER_CORR_GRP5 0xe88023 |
| #define regPARITY_COUNTER_CORR_GRP5_BASE_IDX 5 |
| #define regPARITY_COUNTER_CORR_GRP6 0xe88024 |
| #define regPARITY_COUNTER_CORR_GRP6_BASE_IDX 5 |
| #define regPARITY_COUNTER_CORR_GRP7 0xe88025 |
| #define regPARITY_COUNTER_CORR_GRP7_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UCP_GRP0 0xe88028 |
| #define regPARITY_ERROR_STATUS_UCP_GRP0_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UCP_GRP1 0xe88029 |
| #define regPARITY_ERROR_STATUS_UCP_GRP1_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UCP_GRP2 0xe8802a |
| #define regPARITY_ERROR_STATUS_UCP_GRP2_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UCP_GRP3 0xe8802b |
| #define regPARITY_ERROR_STATUS_UCP_GRP3_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UCP_GRP4 0xe8802c |
| #define regPARITY_ERROR_STATUS_UCP_GRP4_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UCP_GRP5 0xe8802d |
| #define regPARITY_ERROR_STATUS_UCP_GRP5_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UCP_GRP6 0xe8802e |
| #define regPARITY_ERROR_STATUS_UCP_GRP6_BASE_IDX 5 |
| #define regPARITY_ERROR_STATUS_UCP_GRP7 0xe8802f |
| #define regPARITY_ERROR_STATUS_UCP_GRP7_BASE_IDX 5 |
| #define regPARITY_COUNTER_UCP_GRP0 0xe88032 |
| #define regPARITY_COUNTER_UCP_GRP0_BASE_IDX 5 |
| #define regPARITY_COUNTER_UCP_GRP1 0xe88033 |
| #define regPARITY_COUNTER_UCP_GRP1_BASE_IDX 5 |
| #define regPARITY_COUNTER_UCP_GRP2 0xe88034 |
| #define regPARITY_COUNTER_UCP_GRP2_BASE_IDX 5 |
| #define regPARITY_COUNTER_UCP_GRP3 0xe88035 |
| #define regPARITY_COUNTER_UCP_GRP3_BASE_IDX 5 |
| #define regPARITY_COUNTER_UCP_GRP4 0xe88036 |
| #define regPARITY_COUNTER_UCP_GRP4_BASE_IDX 5 |
| #define regPARITY_COUNTER_UCP_GRP5 0xe88037 |
| #define regPARITY_COUNTER_UCP_GRP5_BASE_IDX 5 |
| #define regPARITY_COUNTER_UCP_GRP6 0xe88038 |
| #define regPARITY_COUNTER_UCP_GRP6_BASE_IDX 5 |
| #define regPARITY_COUNTER_UCP_GRP7 0xe88039 |
| #define regPARITY_COUNTER_UCP_GRP7_BASE_IDX 5 |
| #define regMISC_SEVERITY_CONTROL 0xe8803c |
| #define regMISC_SEVERITY_CONTROL_BASE_IDX 5 |
| #define regMISC_RAS_CONTROL 0xe8803d |
| #define regMISC_RAS_CONTROL_BASE_IDX 5 |
| #define regRAS_SCRATCH_0 0xe8803e |
| #define regRAS_SCRATCH_0_BASE_IDX 5 |
| #define regRAS_SCRATCH_1 0xe8803f |
| #define regRAS_SCRATCH_1_BASE_IDX 5 |
| #define regErrEvent_ACTION_CONTROL 0xe88040 |
| #define regErrEvent_ACTION_CONTROL_BASE_IDX 5 |
| #define regParitySerr_ACTION_CONTROL 0xe88041 |
| #define regParitySerr_ACTION_CONTROL_BASE_IDX 5 |
| #define regParityFatal_ACTION_CONTROL 0xe88042 |
| #define regParityFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regParityNonFatal_ACTION_CONTROL 0xe88043 |
| #define regParityNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regParityCorr_ACTION_CONTROL 0xe88044 |
| #define regParityCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortASerr_ACTION_CONTROL 0xe88045 |
| #define regPCIE0PortASerr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortAIntFatal_ACTION_CONTROL 0xe88046 |
| #define regPCIE0PortAIntFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortAIntNonFatal_ACTION_CONTROL 0xe88047 |
| #define regPCIE0PortAIntNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortAIntCorr_ACTION_CONTROL 0xe88048 |
| #define regPCIE0PortAIntCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortAExtFatal_ACTION_CONTROL 0xe88049 |
| #define regPCIE0PortAExtFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortAExtNonFatal_ACTION_CONTROL 0xe8804a |
| #define regPCIE0PortAExtNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortAExtCorr_ACTION_CONTROL 0xe8804b |
| #define regPCIE0PortAExtCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortAParityErr_ACTION_CONTROL 0xe8804c |
| #define regPCIE0PortAParityErr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortBSerr_ACTION_CONTROL 0xe8804d |
| #define regPCIE0PortBSerr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortBIntFatal_ACTION_CONTROL 0xe8804e |
| #define regPCIE0PortBIntFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortBIntNonFatal_ACTION_CONTROL 0xe8804f |
| #define regPCIE0PortBIntNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortBIntCorr_ACTION_CONTROL 0xe88050 |
| #define regPCIE0PortBIntCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortBExtFatal_ACTION_CONTROL 0xe88051 |
| #define regPCIE0PortBExtFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortBExtNonFatal_ACTION_CONTROL 0xe88052 |
| #define regPCIE0PortBExtNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortBExtCorr_ACTION_CONTROL 0xe88053 |
| #define regPCIE0PortBExtCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortBParityErr_ACTION_CONTROL 0xe88054 |
| #define regPCIE0PortBParityErr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortCSerr_ACTION_CONTROL 0xe88055 |
| #define regPCIE0PortCSerr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortCIntFatal_ACTION_CONTROL 0xe88056 |
| #define regPCIE0PortCIntFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortCIntNonFatal_ACTION_CONTROL 0xe88057 |
| #define regPCIE0PortCIntNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortCIntCorr_ACTION_CONTROL 0xe88058 |
| #define regPCIE0PortCIntCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortCExtFatal_ACTION_CONTROL 0xe88059 |
| #define regPCIE0PortCExtFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortCExtNonFatal_ACTION_CONTROL 0xe8805a |
| #define regPCIE0PortCExtNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortCExtCorr_ACTION_CONTROL 0xe8805b |
| #define regPCIE0PortCExtCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortCParityErr_ACTION_CONTROL 0xe8805c |
| #define regPCIE0PortCParityErr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortDSerr_ACTION_CONTROL 0xe8805d |
| #define regPCIE0PortDSerr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortDIntFatal_ACTION_CONTROL 0xe8805e |
| #define regPCIE0PortDIntFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortDIntNonFatal_ACTION_CONTROL 0xe8805f |
| #define regPCIE0PortDIntNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortDIntCorr_ACTION_CONTROL 0xe88060 |
| #define regPCIE0PortDIntCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortDExtFatal_ACTION_CONTROL 0xe88061 |
| #define regPCIE0PortDExtFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortDExtNonFatal_ACTION_CONTROL 0xe88062 |
| #define regPCIE0PortDExtNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortDExtCorr_ACTION_CONTROL 0xe88063 |
| #define regPCIE0PortDExtCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortDParityErr_ACTION_CONTROL 0xe88064 |
| #define regPCIE0PortDParityErr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortESerr_ACTION_CONTROL 0xe88065 |
| #define regPCIE0PortESerr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortEIntFatal_ACTION_CONTROL 0xe88066 |
| #define regPCIE0PortEIntFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortEIntNonFatal_ACTION_CONTROL 0xe88067 |
| #define regPCIE0PortEIntNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortEIntCorr_ACTION_CONTROL 0xe88068 |
| #define regPCIE0PortEIntCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortEExtFatal_ACTION_CONTROL 0xe88069 |
| #define regPCIE0PortEExtFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortEExtNonFatal_ACTION_CONTROL 0xe8806a |
| #define regPCIE0PortEExtNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortEExtCorr_ACTION_CONTROL 0xe8806b |
| #define regPCIE0PortEExtCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortEParityErr_ACTION_CONTROL 0xe8806c |
| #define regPCIE0PortEParityErr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortFSerr_ACTION_CONTROL 0xe8806d |
| #define regPCIE0PortFSerr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortFIntFatal_ACTION_CONTROL 0xe8806e |
| #define regPCIE0PortFIntFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortFIntNonFatal_ACTION_CONTROL 0xe8806f |
| #define regPCIE0PortFIntNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortFIntCorr_ACTION_CONTROL 0xe88070 |
| #define regPCIE0PortFIntCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortFExtFatal_ACTION_CONTROL 0xe88071 |
| #define regPCIE0PortFExtFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortFExtNonFatal_ACTION_CONTROL 0xe88072 |
| #define regPCIE0PortFExtNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortFExtCorr_ACTION_CONTROL 0xe88073 |
| #define regPCIE0PortFExtCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regPCIE0PortFParityErr_ACTION_CONTROL 0xe88074 |
| #define regPCIE0PortFParityErr_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortASerr_ACTION_CONTROL 0xe880cd |
| #define regNBIF1PortASerr_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortAIntFatal_ACTION_CONTROL 0xe880ce |
| #define regNBIF1PortAIntFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortAIntNonFatal_ACTION_CONTROL 0xe880cf |
| #define regNBIF1PortAIntNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortAIntCorr_ACTION_CONTROL 0xe880d0 |
| #define regNBIF1PortAIntCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortAExtFatal_ACTION_CONTROL 0xe880d1 |
| #define regNBIF1PortAExtFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortAExtNonFatal_ACTION_CONTROL 0xe880d2 |
| #define regNBIF1PortAExtNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortAExtCorr_ACTION_CONTROL 0xe880d3 |
| #define regNBIF1PortAExtCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortAParityErr_ACTION_CONTROL 0xe880d4 |
| #define regNBIF1PortAParityErr_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortBSerr_ACTION_CONTROL 0xe880d5 |
| #define regNBIF1PortBSerr_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortBIntFatal_ACTION_CONTROL 0xe880d6 |
| #define regNBIF1PortBIntFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortBIntNonFatal_ACTION_CONTROL 0xe880d7 |
| #define regNBIF1PortBIntNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortBIntCorr_ACTION_CONTROL 0xe880d8 |
| #define regNBIF1PortBIntCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortBExtFatal_ACTION_CONTROL 0xe880d9 |
| #define regNBIF1PortBExtFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortBExtNonFatal_ACTION_CONTROL 0xe880da |
| #define regNBIF1PortBExtNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortBExtCorr_ACTION_CONTROL 0xe880db |
| #define regNBIF1PortBExtCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortBParityErr_ACTION_CONTROL 0xe880dc |
| #define regNBIF1PortBParityErr_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortCSerr_ACTION_CONTROL 0xe880dd |
| #define regNBIF1PortCSerr_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortCIntFatal_ACTION_CONTROL 0xe880de |
| #define regNBIF1PortCIntFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortCIntNonFatal_ACTION_CONTROL 0xe880df |
| #define regNBIF1PortCIntNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortCIntCorr_ACTION_CONTROL 0xe880e0 |
| #define regNBIF1PortCIntCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortCExtFatal_ACTION_CONTROL 0xe880e1 |
| #define regNBIF1PortCExtFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortCExtNonFatal_ACTION_CONTROL 0xe880e2 |
| #define regNBIF1PortCExtNonFatal_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortCExtCorr_ACTION_CONTROL 0xe880e3 |
| #define regNBIF1PortCExtCorr_ACTION_CONTROL_BASE_IDX 5 |
| #define regNBIF1PortCParityErr_ACTION_CONTROL 0xe880e4 |
| #define regNBIF1PortCParityErr_ACTION_CONTROL_BASE_IDX 5 |
| #define regSYNCFLOOD_STATUS 0xe88200 |
| #define regSYNCFLOOD_STATUS_BASE_IDX 5 |
| #define regNMI_STATUS 0xe88201 |
| #define regNMI_STATUS_BASE_IDX 5 |
| #define regPOISON_ACTION_CONTROL 0xe88205 |
| #define regPOISON_ACTION_CONTROL_BASE_IDX 5 |
| #define regINTERNAL_POISON_STATUS 0xe88206 |
| #define regINTERNAL_POISON_STATUS_BASE_IDX 5 |
| #define regINTERNAL_POISON_MASK 0xe88207 |
| #define regINTERNAL_POISON_MASK_BASE_IDX 5 |
| #define regEGRESS_POISON_STATUS_LO 0xe88208 |
| #define regEGRESS_POISON_STATUS_LO_BASE_IDX 5 |
| #define regEGRESS_POISON_STATUS_HI 0xe88209 |
| #define regEGRESS_POISON_STATUS_HI_BASE_IDX 5 |
| #define regEGRESS_POISON_MASK_LO 0xe8820a |
| #define regEGRESS_POISON_MASK_LO_BASE_IDX 5 |
| #define regEGRESS_POISON_MASK_HI 0xe8820b |
| #define regEGRESS_POISON_MASK_HI_BASE_IDX 5 |
| #define regEGRESS_POISON_SEVERITY_DOWN 0xe8820c |
| #define regEGRESS_POISON_SEVERITY_DOWN_BASE_IDX 5 |
| #define regEGRESS_POISON_SEVERITY_UPPER 0xe8820d |
| #define regEGRESS_POISON_SEVERITY_UPPER_BASE_IDX 5 |
| #define regAPML_STATUS 0xe88370 |
| #define regAPML_STATUS_BASE_IDX 5 |
| #define regAPML_CONTROL 0xe88371 |
| #define regAPML_CONTROL_BASE_IDX 5 |
| #define regAPML_TRIGGER 0xe88372 |
| #define regAPML_TRIGGER_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp |
| // base address: 0x13b3c000 |
| |
| |
| // addressBlock: nbio_iohub_nb_ioapiccfg_ioapic_cfgdec |
| // base address: 0x14300000 |
| #define regFEATURES_ENABLE 0x1080000 |
| #define regFEATURES_ENABLE_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_iohub_iommu_l2a_l2acfg |
| // base address: 0x15700000 |
| #define regL2_PERF_CNTL_0 0x1580000 |
| #define regL2_PERF_CNTL_0_BASE_IDX 5 |
| #define regL2_PERF_COUNT_0 0x1580001 |
| #define regL2_PERF_COUNT_0_BASE_IDX 5 |
| #define regL2_PERF_COUNT_1 0x1580002 |
| #define regL2_PERF_COUNT_1_BASE_IDX 5 |
| #define regL2_PERF_CNTL_1 0x1580003 |
| #define regL2_PERF_CNTL_1_BASE_IDX 5 |
| #define regL2_PERF_COUNT_2 0x1580004 |
| #define regL2_PERF_COUNT_2_BASE_IDX 5 |
| #define regL2_PERF_COUNT_3 0x1580005 |
| #define regL2_PERF_COUNT_3_BASE_IDX 5 |
| #define regL2_STATUS_0 0x1580008 |
| #define regL2_STATUS_0_BASE_IDX 5 |
| #define regL2_CONTROL_0 0x158000c |
| #define regL2_CONTROL_0_BASE_IDX 5 |
| #define regL2_CONTROL_1 0x158000d |
| #define regL2_CONTROL_1_BASE_IDX 5 |
| #define regL2_DTC_CONTROL 0x1580010 |
| #define regL2_DTC_CONTROL_BASE_IDX 5 |
| #define regL2_DTC_HASH_CONTROL 0x1580011 |
| #define regL2_DTC_HASH_CONTROL_BASE_IDX 5 |
| #define regL2_DTC_WAY_CONTROL 0x1580012 |
| #define regL2_DTC_WAY_CONTROL_BASE_IDX 5 |
| #define regL2_ITC_CONTROL 0x1580014 |
| #define regL2_ITC_CONTROL_BASE_IDX 5 |
| #define regL2_ITC_HASH_CONTROL 0x1580015 |
| #define regL2_ITC_HASH_CONTROL_BASE_IDX 5 |
| #define regL2_ITC_WAY_CONTROL 0x1580016 |
| #define regL2_ITC_WAY_CONTROL_BASE_IDX 5 |
| #define regL2_PTC_A_CONTROL 0x1580018 |
| #define regL2_PTC_A_CONTROL_BASE_IDX 5 |
| #define regL2_PTC_A_HASH_CONTROL 0x1580019 |
| #define regL2_PTC_A_HASH_CONTROL_BASE_IDX 5 |
| #define regL2_PTC_A_WAY_CONTROL 0x158001a |
| #define regL2_PTC_A_WAY_CONTROL_BASE_IDX 5 |
| #define regL2_CREDIT_CONTROL_2 0x1580020 |
| #define regL2_CREDIT_CONTROL_2_BASE_IDX 5 |
| #define regL2A_UPDATE_FILTER_CNTL 0x1580022 |
| #define regL2A_UPDATE_FILTER_CNTL_BASE_IDX 5 |
| #define regL2_ERR_RULE_CONTROL_3 0x1580030 |
| #define regL2_ERR_RULE_CONTROL_3_BASE_IDX 5 |
| #define regL2_ERR_RULE_CONTROL_4 0x1580031 |
| #define regL2_ERR_RULE_CONTROL_4_BASE_IDX 5 |
| #define regL2_ERR_RULE_CONTROL_5 0x1580032 |
| #define regL2_ERR_RULE_CONTROL_5_BASE_IDX 5 |
| #define regL2_L2A_CK_GATE_CONTROL 0x1580033 |
| #define regL2_L2A_CK_GATE_CONTROL_BASE_IDX 5 |
| #define regL2_L2A_PGSIZE_CONTROL 0x1580034 |
| #define regL2_L2A_PGSIZE_CONTROL_BASE_IDX 5 |
| #define regL2_L2A_MEMPWR_GATE_1 0x1580035 |
| #define regL2_L2A_MEMPWR_GATE_1_BASE_IDX 5 |
| #define regL2_L2A_MEMPWR_GATE_2 0x1580036 |
| #define regL2_L2A_MEMPWR_GATE_2_BASE_IDX 5 |
| #define regL2_L2A_MEMPWR_GATE_3 0x1580037 |
| #define regL2_L2A_MEMPWR_GATE_3_BASE_IDX 5 |
| #define regL2_L2A_MEMPWR_GATE_4 0x1580038 |
| #define regL2_L2A_MEMPWR_GATE_4_BASE_IDX 5 |
| #define regL2_L2A_MEMPWR_GATE_5 0x1580039 |
| #define regL2_L2A_MEMPWR_GATE_5_BASE_IDX 5 |
| #define regL2_L2A_MEMPWR_GATE_6 0x158003a |
| #define regL2_L2A_MEMPWR_GATE_6_BASE_IDX 5 |
| #define regL2_L2A_MEMPWR_GATE_7 0x158003b |
| #define regL2_L2A_MEMPWR_GATE_7_BASE_IDX 5 |
| #define regL2_L2A_MEMPWR_GATE_8 0x158003c |
| #define regL2_L2A_MEMPWR_GATE_8_BASE_IDX 5 |
| #define regL2_L2A_MEMPWR_GATE_9 0x158003d |
| #define regL2_L2A_MEMPWR_GATE_9_BASE_IDX 5 |
| #define regL2_PWRGATE_CNTRL_REG_0 0x158003e |
| #define regL2_PWRGATE_CNTRL_REG_0_BASE_IDX 5 |
| #define regL2_L2A_MEMPWR_GATE_10 0x158003f |
| #define regL2_L2A_MEMPWR_GATE_10_BASE_IDX 5 |
| #define regL2_PWRGATE_CNTRL_REG_3 0x1580041 |
| #define regL2_PWRGATE_CNTRL_REG_3_BASE_IDX 5 |
| #define regL2_ECO_CNTRL_0 0x1580042 |
| #define regL2_ECO_CNTRL_0_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_iohub_iommu_l2ashdw_l2ashdw |
| // base address: 0x15704000 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
| // base address: 0xd0000000 |
| #define regBIF_BX_PF2_MM_INDEX 0x2ffc0000 |
| #define regBIF_BX_PF2_MM_INDEX_BASE_IDX 5 |
| #define regBIF_BX_PF2_MM_DATA 0x2ffc0001 |
| #define regBIF_BX_PF2_MM_DATA_BASE_IDX 5 |
| #define regBIF_BX_PF2_MM_INDEX_HI 0x2ffc0006 |
| #define regBIF_BX_PF2_MM_INDEX_HI_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_SYSDEC |
| // base address: 0xd0000000 |
| #define regBIF_BX2_PCIE_INDEX 0x2ffc000c |
| #define regBIF_BX2_PCIE_INDEX_BASE_IDX 5 |
| #define regBIF_BX2_PCIE_DATA 0x2ffc000d |
| #define regBIF_BX2_PCIE_DATA_BASE_IDX 5 |
| #define regBIF_BX2_PCIE_INDEX2 0x2ffc000e |
| #define regBIF_BX2_PCIE_INDEX2_BASE_IDX 5 |
| #define regBIF_BX2_PCIE_DATA2 0x2ffc000f |
| #define regBIF_BX2_PCIE_DATA2_BASE_IDX 5 |
| #define regBIF_BX2_SBIOS_SCRATCH_0 0x2ffc0048 |
| #define regBIF_BX2_SBIOS_SCRATCH_0_BASE_IDX 5 |
| #define regBIF_BX2_SBIOS_SCRATCH_1 0x2ffc0049 |
| #define regBIF_BX2_SBIOS_SCRATCH_1_BASE_IDX 5 |
| #define regBIF_BX2_SBIOS_SCRATCH_2 0x2ffc004a |
| #define regBIF_BX2_SBIOS_SCRATCH_2_BASE_IDX 5 |
| #define regBIF_BX2_SBIOS_SCRATCH_3 0x2ffc004b |
| #define regBIF_BX2_SBIOS_SCRATCH_3_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_0 0x2ffc004c |
| #define regBIF_BX2_BIOS_SCRATCH_0_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_1 0x2ffc004d |
| #define regBIF_BX2_BIOS_SCRATCH_1_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_2 0x2ffc004e |
| #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_3 0x2ffc004f |
| #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_4 0x2ffc0050 |
| #define regBIF_BX2_BIOS_SCRATCH_4_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_5 0x2ffc0051 |
| #define regBIF_BX2_BIOS_SCRATCH_5_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_6 0x2ffc0052 |
| #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_7 0x2ffc0053 |
| #define regBIF_BX2_BIOS_SCRATCH_7_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_8 0x2ffc0054 |
| #define regBIF_BX2_BIOS_SCRATCH_8_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_9 0x2ffc0055 |
| #define regBIF_BX2_BIOS_SCRATCH_9_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_10 0x2ffc0056 |
| #define regBIF_BX2_BIOS_SCRATCH_10_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_11 0x2ffc0057 |
| #define regBIF_BX2_BIOS_SCRATCH_11_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_12 0x2ffc0058 |
| #define regBIF_BX2_BIOS_SCRATCH_12_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_13 0x2ffc0059 |
| #define regBIF_BX2_BIOS_SCRATCH_13_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_14 0x2ffc005a |
| #define regBIF_BX2_BIOS_SCRATCH_14_BASE_IDX 5 |
| #define regBIF_BX2_BIOS_SCRATCH_15 0x2ffc005b |
| #define regBIF_BX2_BIOS_SCRATCH_15_BASE_IDX 5 |
| #define regBIF_BX2_BIF_RLC_INTR_CNTL 0x2ffc0060 |
| #define regBIF_BX2_BIF_RLC_INTR_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_VCE_INTR_CNTL 0x2ffc0061 |
| #define regBIF_BX2_BIF_VCE_INTR_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_UVD_INTR_CNTL 0x2ffc0062 |
| #define regBIF_BX2_BIF_UVD_INTR_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR0 0x2ffc0080 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0 0x2ffc0081 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR1 0x2ffc0082 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1 0x2ffc0083 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR2 0x2ffc0084 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2 0x2ffc0085 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR3 0x2ffc0086 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3 0x2ffc0087 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR4 0x2ffc0088 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4 0x2ffc0089 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR5 0x2ffc008a |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5 0x2ffc008b |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR6 0x2ffc008c |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6 0x2ffc008d |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR7 0x2ffc008e |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7 0x2ffc008f |
| #define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_CNTL 0x2ffc0090 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL 0x2ffc0091 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ONE_CPL 0x2ffc0092 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 5 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x2ffc0093 |
| #define regBIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
| // base address: 0xd0000000 |
| #define regRCC_STRAP3_RCC_BIF_STRAP0 0x2ffc0d20 |
| #define regRCC_STRAP3_RCC_BIF_STRAP0_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_BIF_STRAP1 0x2ffc0d21 |
| #define regRCC_STRAP3_RCC_BIF_STRAP1_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_BIF_STRAP2 0x2ffc0d22 |
| #define regRCC_STRAP3_RCC_BIF_STRAP2_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_BIF_STRAP3 0x2ffc0d23 |
| #define regRCC_STRAP3_RCC_BIF_STRAP3_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_BIF_STRAP4 0x2ffc0d24 |
| #define regRCC_STRAP3_RCC_BIF_STRAP4_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_BIF_STRAP5 0x2ffc0d25 |
| #define regRCC_STRAP3_RCC_BIF_STRAP5_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_BIF_STRAP6 0x2ffc0d26 |
| #define regRCC_STRAP3_RCC_BIF_STRAP6_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP0 0x2ffc0d27 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP0_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP1 0x2ffc0d28 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP1_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP10 0x2ffc0d29 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP10_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP11 0x2ffc0d2a |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP11_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP12 0x2ffc0d2b |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP12_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP13 0x2ffc0d2c |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP13_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP2 0x2ffc0d2d |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP2_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP3 0x2ffc0d2e |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP3_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP4 0x2ffc0d2f |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP4_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP5 0x2ffc0d30 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP5_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP6 0x2ffc0d31 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP6_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP7 0x2ffc0d32 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP7_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP8 0x2ffc0d33 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP8_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP9 0x2ffc0d34 |
| #define regRCC_STRAP3_RCC_DEV0_PORT_STRAP9_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP0 0x2ffc0d35 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP1 0x2ffc0d36 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP1_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP13 0x2ffc0d37 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP13_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP14 0x2ffc0d38 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP14_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP15 0x2ffc0d39 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP15_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP16 0x2ffc0d3a |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP16_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP17 0x2ffc0d3b |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP17_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP18 0x2ffc0d3c |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP18_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP2 0x2ffc0d3d |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP2_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP3 0x2ffc0d3e |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP3_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP4 0x2ffc0d3f |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP4_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP5 0x2ffc0d40 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP5_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP8 0x2ffc0d42 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP8_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP9 0x2ffc0d43 |
| #define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP9_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP0 0x2ffc0d44 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP0_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP2 0x2ffc0d4f |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP2_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP3 0x2ffc0d50 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP3_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP4 0x2ffc0d51 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP4_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP5 0x2ffc0d52 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP5_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP6 0x2ffc0d53 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP6_BASE_IDX 5 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP7 0x2ffc0d54 |
| #define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP7_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
| // base address: 0xd0000000 |
| #define regRCC_EP_DEV0_3_EP_PCIE_SCRATCH 0x2ffc0d56 |
| #define regRCC_EP_DEV0_3_EP_PCIE_SCRATCH_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_CNTL 0x2ffc0d58 |
| #define regRCC_EP_DEV0_3_EP_PCIE_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_INT_CNTL 0x2ffc0d59 |
| #define regRCC_EP_DEV0_3_EP_PCIE_INT_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_INT_STATUS 0x2ffc0d5a |
| #define regRCC_EP_DEV0_3_EP_PCIE_INT_STATUS_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_RX_CNTL2 0x2ffc0d5b |
| #define regRCC_EP_DEV0_3_EP_PCIE_RX_CNTL2_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_BUS_CNTL 0x2ffc0d5c |
| #define regRCC_EP_DEV0_3_EP_PCIE_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_CFG_CNTL 0x2ffc0d5d |
| #define regRCC_EP_DEV0_3_EP_PCIE_CFG_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL 0x2ffc0d5f |
| #define regRCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x2ffc0d60 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x2ffc0d60 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x2ffc0d60 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x2ffc0d60 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x2ffc0d61 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x2ffc0d61 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x2ffc0d61 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x2ffc0d61 |
| #define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_STRAP_MISC 0x2ffc0d62 |
| #define regRCC_EP_DEV0_3_EP_PCIE_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_STRAP_MISC2 0x2ffc0d63 |
| #define regRCC_EP_DEV0_3_EP_PCIE_STRAP_MISC2_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP 0x2ffc0d65 |
| #define regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x2ffc0d66 |
| #define regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL 0x2ffc0d66 |
| #define regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x2ffc0d66 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x2ffc0d67 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x2ffc0d67 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x2ffc0d67 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x2ffc0d67 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x2ffc0d68 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x2ffc0d68 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x2ffc0d68 |
| #define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_PME_CONTROL 0x2ffc0d68 |
| #define regRCC_EP_DEV0_3_EP_PCIE_PME_CONTROL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIEP_RESERVED 0x2ffc0d69 |
| #define regRCC_EP_DEV0_3_EP_PCIEP_RESERVED_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_TX_CNTL 0x2ffc0d6b |
| #define regRCC_EP_DEV0_3_EP_PCIE_TX_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID 0x2ffc0d6c |
| #define regRCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_ERR_CNTL 0x2ffc0d6d |
| #define regRCC_EP_DEV0_3_EP_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_RX_CNTL 0x2ffc0d6e |
| #define regRCC_EP_DEV0_3_EP_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regRCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL 0x2ffc0d6f |
| #define regRCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
| // base address: 0xd0000000 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_RESERVED 0x2ffc0d70 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_RESERVED_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_SCRATCH 0x2ffc0d71 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_SCRATCH_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_CNTL 0x2ffc0d73 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL 0x2ffc0d74 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2 0x2ffc0d75 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL 0x2ffc0d76 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL 0x2ffc0d77 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_STRAP_F0 0x2ffc0d78 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_STRAP_F0_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC 0x2ffc0d79 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC2 0x2ffc0d7a |
| #define regRCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC2_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
| // base address: 0xd0000000 |
| #define regRCC_DWNP_DEV0_3_PCIE_ERR_CNTL 0x2ffc0d7c |
| #define regRCC_DWNP_DEV0_3_PCIE_ERR_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_3_PCIE_RX_CNTL 0x2ffc0d7d |
| #define regRCC_DWNP_DEV0_3_PCIE_RX_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL 0x2ffc0d7e |
| #define regRCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_3_PCIE_LC_CNTL2 0x2ffc0d7f |
| #define regRCC_DWNP_DEV0_3_PCIE_LC_CNTL2_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_3_PCIEP_STRAP_MISC 0x2ffc0d80 |
| #define regRCC_DWNP_DEV0_3_PCIEP_STRAP_MISC_BASE_IDX 5 |
| #define regRCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP 0x2ffc0d81 |
| #define regRCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] |
| // base address: 0xd0003480 |
| #define regRCC_DEV0_EPF0_1_RCC_ERR_LOG 0x2ffc0da5 |
| #define regRCC_DEV0_EPF0_1_RCC_ERR_LOG_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN 0x2ffc0de0 |
| #define regRCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE 0x2ffc0de3 |
| #define regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED 0x2ffc0de4 |
| #define regRCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER 0x2ffc0de5 |
| #define regRCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 |
| // base address: 0xd0000000 |
| #define regRCC_DEV0_2_RCC_ERR_INT_CNTL 0x2ffc0da6 |
| #define regRCC_DEV0_2_RCC_ERR_INT_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_BACO_CNTL_MISC 0x2ffc0da7 |
| #define regRCC_DEV0_2_RCC_BACO_CNTL_MISC_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_RESET_EN 0x2ffc0da8 |
| #define regRCC_DEV0_2_RCC_RESET_EN_BASE_IDX 5 |
| #define regRCC_DEV0_3_RCC_VDM_SUPPORT 0x2ffc0da9 |
| #define regRCC_DEV0_3_RCC_VDM_SUPPORT_BASE_IDX 5 |
| #define regRCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0 0x2ffc0daa |
| #define regRCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 5 |
| #define regRCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1 0x2ffc0dab |
| #define regRCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_GPUIOV_REGION 0x2ffc0dac |
| #define regRCC_DEV0_2_RCC_GPUIOV_REGION_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_GPU_HOSTVM_EN 0x2ffc0dad |
| #define regRCC_DEV0_2_RCC_GPU_HOSTVM_EN_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL 0x2ffc0dae |
| #define regRCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x2ffc0daf |
| #define regRCC_DEV0_2_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_CONSOLE_IOV_VF_STRIDE 0x2ffc0daf |
| #define regRCC_DEV0_2_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_PEER_REG_RANGE0 0x2ffc0dde |
| #define regRCC_DEV0_2_RCC_PEER_REG_RANGE0_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_PEER_REG_RANGE1 0x2ffc0ddf |
| #define regRCC_DEV0_2_RCC_PEER_REG_RANGE1_BASE_IDX 5 |
| #define regRCC_DEV0_3_RCC_BUS_CNTL 0x2ffc0de1 |
| #define regRCC_DEV0_3_RCC_BUS_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_CONFIG_CNTL 0x2ffc0de2 |
| #define regRCC_DEV0_2_RCC_CONFIG_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_CONFIG_F0_BASE 0x2ffc0de6 |
| #define regRCC_DEV0_2_RCC_CONFIG_F0_BASE_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_CONFIG_APER_SIZE 0x2ffc0de7 |
| #define regRCC_DEV0_2_RCC_CONFIG_APER_SIZE_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_CONFIG_REG_APER_SIZE 0x2ffc0de8 |
| #define regRCC_DEV0_2_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_XDMA_LO 0x2ffc0de9 |
| #define regRCC_DEV0_2_RCC_XDMA_LO_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_XDMA_HI 0x2ffc0dea |
| #define regRCC_DEV0_2_RCC_XDMA_HI_BASE_IDX 5 |
| #define regRCC_DEV0_3_RCC_FEATURES_CONTROL_MISC 0x2ffc0deb |
| #define regRCC_DEV0_3_RCC_FEATURES_CONTROL_MISC_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_BUSNUM_CNTL1 0x2ffc0dec |
| #define regRCC_DEV0_2_RCC_BUSNUM_CNTL1_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_BUSNUM_LIST0 0x2ffc0ded |
| #define regRCC_DEV0_2_RCC_BUSNUM_LIST0_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_BUSNUM_LIST1 0x2ffc0dee |
| #define regRCC_DEV0_2_RCC_BUSNUM_LIST1_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_BUSNUM_CNTL2 0x2ffc0def |
| #define regRCC_DEV0_2_RCC_BUSNUM_CNTL2_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_CAPTURE_HOST_BUSNUM 0x2ffc0df0 |
| #define regRCC_DEV0_2_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_HOST_BUSNUM 0x2ffc0df1 |
| #define regRCC_DEV0_2_RCC_HOST_BUSNUM_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_PEER0_FB_OFFSET_HI 0x2ffc0df2 |
| #define regRCC_DEV0_2_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO 0x2ffc0df3 |
| #define regRCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_PEER1_FB_OFFSET_HI 0x2ffc0df4 |
| #define regRCC_DEV0_2_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO 0x2ffc0df5 |
| #define regRCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_PEER2_FB_OFFSET_HI 0x2ffc0df6 |
| #define regRCC_DEV0_2_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO 0x2ffc0df7 |
| #define regRCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_PEER3_FB_OFFSET_HI 0x2ffc0df8 |
| #define regRCC_DEV0_2_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO 0x2ffc0df9 |
| #define regRCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_DEVFUNCNUM_LIST0 0x2ffc0dfa |
| #define regRCC_DEV0_2_RCC_DEVFUNCNUM_LIST0_BASE_IDX 5 |
| #define regRCC_DEV0_2_RCC_DEVFUNCNUM_LIST1 0x2ffc0dfb |
| #define regRCC_DEV0_2_RCC_DEVFUNCNUM_LIST1_BASE_IDX 5 |
| #define regRCC_DEV0_3_RCC_DEV0_LINK_CNTL 0x2ffc0dfd |
| #define regRCC_DEV0_3_RCC_DEV0_LINK_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_3_RCC_CMN_LINK_CNTL 0x2ffc0dfe |
| #define regRCC_DEV0_3_RCC_CMN_LINK_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE 0x2ffc0dff |
| #define regRCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 5 |
| #define regRCC_DEV0_3_RCC_LTR_LSWITCH_CNTL 0x2ffc0e00 |
| #define regRCC_DEV0_3_RCC_LTR_LSWITCH_CNTL_BASE_IDX 5 |
| #define regRCC_DEV0_3_RCC_MH_ARB_CNTL 0x2ffc0e01 |
| #define regRCC_DEV0_3_RCC_MH_ARB_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 |
| // base address: 0xd0000000 |
| #define regBIF_BX2_CC_BIF_BX_STRAP0 0x2ffc0e02 |
| #define regBIF_BX2_CC_BIF_BX_STRAP0_BASE_IDX 5 |
| #define regBIF_BX2_CC_BIF_BX_PINSTRAP0 0x2ffc0e04 |
| #define regBIF_BX2_CC_BIF_BX_PINSTRAP0_BASE_IDX 5 |
| #define regBIF_BX2_BIF_MM_INDACCESS_CNTL 0x2ffc0e06 |
| #define regBIF_BX2_BIF_MM_INDACCESS_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BUS_CNTL 0x2ffc0e07 |
| #define regBIF_BX2_BUS_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_SCRATCH0 0x2ffc0e08 |
| #define regBIF_BX2_BIF_SCRATCH0_BASE_IDX 5 |
| #define regBIF_BX2_BIF_SCRATCH1 0x2ffc0e09 |
| #define regBIF_BX2_BIF_SCRATCH1_BASE_IDX 5 |
| #define regBIF_BX2_BX_RESET_EN 0x2ffc0e0d |
| #define regBIF_BX2_BX_RESET_EN_BASE_IDX 5 |
| #define regBIF_BX2_MM_CFGREGS_CNTL 0x2ffc0e0e |
| #define regBIF_BX2_MM_CFGREGS_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BX_RESET_CNTL 0x2ffc0e10 |
| #define regBIF_BX2_BX_RESET_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_INTERRUPT_CNTL 0x2ffc0e11 |
| #define regBIF_BX2_INTERRUPT_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_INTERRUPT_CNTL2 0x2ffc0e12 |
| #define regBIF_BX2_INTERRUPT_CNTL2_BASE_IDX 5 |
| #define regBIF_BX2_CLKREQB_PAD_CNTL 0x2ffc0e18 |
| #define regBIF_BX2_CLKREQB_PAD_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_FEATURES_CONTROL_MISC 0x2ffc0e1b |
| #define regBIF_BX2_BIF_FEATURES_CONTROL_MISC_BASE_IDX 5 |
| #define regBIF_BX2_BIF_DOORBELL_CNTL 0x2ffc0e1d |
| #define regBIF_BX2_BIF_DOORBELL_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_DOORBELL_INT_CNTL 0x2ffc0e1e |
| #define regBIF_BX2_BIF_DOORBELL_INT_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_FB_EN 0x2ffc0e20 |
| #define regBIF_BX2_BIF_FB_EN_BASE_IDX 5 |
| #define regBIF_BX2_BIF_INTR_CNTL 0x2ffc0e21 |
| #define regBIF_BX2_BIF_INTR_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_MST_TRANS_PENDING_VF 0x2ffc0e29 |
| #define regBIF_BX2_BIF_MST_TRANS_PENDING_VF_BASE_IDX 5 |
| #define regBIF_BX2_BIF_SLV_TRANS_PENDING_VF 0x2ffc0e2a |
| #define regBIF_BX2_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 5 |
| #define regBIF_BX2_BACO_CNTL 0x2ffc0e2b |
| #define regBIF_BX2_BACO_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_BACO_EXIT_TIME0 0x2ffc0e2c |
| #define regBIF_BX2_BIF_BACO_EXIT_TIME0_BASE_IDX 5 |
| #define regBIF_BX2_BIF_BACO_EXIT_TIMER1 0x2ffc0e2d |
| #define regBIF_BX2_BIF_BACO_EXIT_TIMER1_BASE_IDX 5 |
| #define regBIF_BX2_BIF_BACO_EXIT_TIMER2 0x2ffc0e2e |
| #define regBIF_BX2_BIF_BACO_EXIT_TIMER2_BASE_IDX 5 |
| #define regBIF_BX2_BIF_BACO_EXIT_TIMER3 0x2ffc0e2f |
| #define regBIF_BX2_BIF_BACO_EXIT_TIMER3_BASE_IDX 5 |
| #define regBIF_BX2_BIF_BACO_EXIT_TIMER4 0x2ffc0e30 |
| #define regBIF_BX2_BIF_BACO_EXIT_TIMER4_BASE_IDX 5 |
| #define regBIF_BX2_MEM_TYPE_CNTL 0x2ffc0e31 |
| #define regBIF_BX2_MEM_TYPE_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_CNTL 0x2ffc0e33 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_0 0x2ffc0e34 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_0_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_1 0x2ffc0e35 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_1_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_2 0x2ffc0e36 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_2_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_3 0x2ffc0e37 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_3_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_4 0x2ffc0e38 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_4_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_5 0x2ffc0e39 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_5_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_6 0x2ffc0e3a |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_6_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_7 0x2ffc0e3b |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_7_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_8 0x2ffc0e3c |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_8_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_9 0x2ffc0e3d |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_9_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_10 0x2ffc0e3e |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_10_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_11 0x2ffc0e3f |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_11_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_12 0x2ffc0e40 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_12_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_13 0x2ffc0e41 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_13_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_14 0x2ffc0e42 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_14_BASE_IDX 5 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_15 0x2ffc0e43 |
| #define regBIF_BX2_NBIF_GFX_ADDR_LUT_15_BASE_IDX 5 |
| #define regBIF_BX2_VF_REGWR_EN 0x2ffc0e44 |
| #define regBIF_BX2_VF_REGWR_EN_BASE_IDX 5 |
| #define regBIF_BX2_VF_DOORBELL_EN 0x2ffc0e45 |
| #define regBIF_BX2_VF_DOORBELL_EN_BASE_IDX 5 |
| #define regBIF_BX2_VF_FB_EN 0x2ffc0e46 |
| #define regBIF_BX2_VF_FB_EN_BASE_IDX 5 |
| #define regBIF_BX2_VF_REGWR_STATUS 0x2ffc0e47 |
| #define regBIF_BX2_VF_REGWR_STATUS_BASE_IDX 5 |
| #define regBIF_BX2_VF_DOORBELL_STATUS 0x2ffc0e48 |
| #define regBIF_BX2_VF_DOORBELL_STATUS_BASE_IDX 5 |
| #define regBIF_BX2_VF_FB_STATUS 0x2ffc0e49 |
| #define regBIF_BX2_VF_FB_STATUS_BASE_IDX 5 |
| #define regBIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL 0x2ffc0e4d |
| #define regBIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_REMAP_HDP_REG_FLUSH_CNTL 0x2ffc0e4e |
| #define regBIF_BX2_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_RB_CNTL 0x2ffc0e4f |
| #define regBIF_BX2_BIF_RB_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_RB_BASE 0x2ffc0e50 |
| #define regBIF_BX2_BIF_RB_BASE_BASE_IDX 5 |
| #define regBIF_BX2_BIF_RB_RPTR 0x2ffc0e51 |
| #define regBIF_BX2_BIF_RB_RPTR_BASE_IDX 5 |
| #define regBIF_BX2_BIF_RB_WPTR 0x2ffc0e52 |
| #define regBIF_BX2_BIF_RB_WPTR_BASE_IDX 5 |
| #define regBIF_BX2_BIF_RB_WPTR_ADDR_HI 0x2ffc0e53 |
| #define regBIF_BX2_BIF_RB_WPTR_ADDR_HI_BASE_IDX 5 |
| #define regBIF_BX2_BIF_RB_WPTR_ADDR_LO 0x2ffc0e54 |
| #define regBIF_BX2_BIF_RB_WPTR_ADDR_LO_BASE_IDX 5 |
| #define regBIF_BX2_MAILBOX_INDEX 0x2ffc0e55 |
| #define regBIF_BX2_MAILBOX_INDEX_BASE_IDX 5 |
| #define regBIF_BX2_BIF_VCN0_GPUIOV_CFG_SIZE 0x2ffc0e63 |
| #define regBIF_BX2_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX 5 |
| #define regBIF_BX2_BIF_VCN1_GPUIOV_CFG_SIZE 0x2ffc0e64 |
| #define regBIF_BX2_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX 5 |
| #define regBIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x2ffc0e65 |
| #define regBIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 5 |
| #define regBIF_BX2_BIF_PERSTB_PAD_CNTL 0x2ffc0e68 |
| #define regBIF_BX2_BIF_PERSTB_PAD_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_PX_EN_PAD_CNTL 0x2ffc0e69 |
| #define regBIF_BX2_BIF_PX_EN_PAD_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_REFPADKIN_PAD_CNTL 0x2ffc0e6a |
| #define regBIF_BX2_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_CLKREQB_PAD_CNTL 0x2ffc0e6b |
| #define regBIF_BX2_BIF_CLKREQB_PAD_CNTL_BASE_IDX 5 |
| #define regBIF_BX2_BIF_PWRBRK_PAD_CNTL 0x2ffc0e6c |
| #define regBIF_BX2_BIF_PWRBRK_PAD_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
| // base address: 0xd0000000 |
| #define regBIF_BX_PF2_BIF_BME_STATUS 0x2ffc0e0b |
| #define regBIF_BX_PF2_BIF_BME_STATUS_BASE_IDX 5 |
| #define regBIF_BX_PF2_BIF_ATOMIC_ERR_LOG 0x2ffc0e0c |
| #define regBIF_BX_PF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 5 |
| #define regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x2ffc0e13 |
| #define regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 5 |
| #define regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x2ffc0e14 |
| #define regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 5 |
| #define regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x2ffc0e15 |
| #define regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 5 |
| #define regBIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x2ffc0e16 |
| #define regBIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 5 |
| #define regBIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x2ffc0e17 |
| #define regBIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 5 |
| #define regBIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x2ffc0e19 |
| #define regBIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 5 |
| #define regBIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x2ffc0e1a |
| #define regBIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 5 |
| #define regBIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ 0x2ffc0e24 |
| #define regBIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ_BASE_IDX 5 |
| #define regBIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ 0x2ffc0e25 |
| #define regBIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ_BASE_IDX 5 |
| #define regBIF_BX_PF2_GPU_HDP_FLUSH_REQ 0x2ffc0e26 |
| #define regBIF_BX_PF2_GPU_HDP_FLUSH_REQ_BASE_IDX 5 |
| #define regBIF_BX_PF2_GPU_HDP_FLUSH_DONE 0x2ffc0e27 |
| #define regBIF_BX_PF2_GPU_HDP_FLUSH_DONE_BASE_IDX 5 |
| #define regBIF_BX_PF2_BIF_TRANS_PENDING 0x2ffc0e28 |
| #define regBIF_BX_PF2_BIF_TRANS_PENDING_BASE_IDX 5 |
| #define regBIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS 0x2ffc0e32 |
| #define regBIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 5 |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0 0x2ffc0e56 |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 5 |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1 0x2ffc0e57 |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 5 |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2 0x2ffc0e58 |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 5 |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3 0x2ffc0e59 |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 5 |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0 0x2ffc0e5a |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 5 |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1 0x2ffc0e5b |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 5 |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2 0x2ffc0e5c |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 5 |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3 0x2ffc0e5d |
| #define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 5 |
| #define regBIF_BX_PF2_MAILBOX_CONTROL 0x2ffc0e5e |
| #define regBIF_BX_PF2_MAILBOX_CONTROL_BASE_IDX 5 |
| #define regBIF_BX_PF2_MAILBOX_INT_CNTL 0x2ffc0e5f |
| #define regBIF_BX_PF2_MAILBOX_INT_CNTL_BASE_IDX 5 |
| #define regBIF_BX_PF2_BIF_VMHV_MAILBOX 0x2ffc0e60 |
| #define regBIF_BX_PF2_BIF_VMHV_MAILBOX_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_gdc_GDCDEC |
| // base address: 0xd0000000 |
| #define regGDC1_NGDC_SDP_PORT_CTRL 0x2ffc0ee2 |
| #define regGDC1_NGDC_SDP_PORT_CTRL_BASE_IDX 5 |
| #define regGDC1_NGDC_MGCG_CTRL 0x2ffc0eea |
| #define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 5 |
| #define regGDC1_NGDC_RESERVED_0 0x2ffc0eeb |
| #define regGDC1_NGDC_RESERVED_0_BASE_IDX 5 |
| #define regGDC1_NGDC_RESERVED_1 0x2ffc0eec |
| #define regGDC1_NGDC_RESERVED_1_BASE_IDX 5 |
| #define regGDC1_NGDC_SDP_PORT_CTRL_SOCCLK 0x2ffc0eed |
| #define regGDC1_NGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 5 |
| #define regGDC1_NGDC_SDP_PORT_CTRL1_SOCCLK 0x2ffc0eee |
| #define regGDC1_NGDC_SDP_PORT_CTRL1_SOCCLK_BASE_IDX 5 |
| #define regGDC1_NBIF_GFX_DOORBELL_STATUS 0x2ffc0eef |
| #define regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 5 |
| #define regGDC1_BIF_SDMA0_DOORBELL_RANGE 0x2ffc0ef0 |
| #define regGDC1_BIF_SDMA0_DOORBELL_RANGE_BASE_IDX 5 |
| #define regGDC1_BIF_SDMA1_DOORBELL_RANGE 0x2ffc0ef1 |
| #define regGDC1_BIF_SDMA1_DOORBELL_RANGE_BASE_IDX 5 |
| #define regGDC1_BIF_IH_DOORBELL_RANGE 0x2ffc0ef2 |
| #define regGDC1_BIF_IH_DOORBELL_RANGE_BASE_IDX 5 |
| #define regGDC1_BIF_VCN0_DOORBELL_RANGE 0x2ffc0ef3 |
| #define regGDC1_BIF_VCN0_DOORBELL_RANGE_BASE_IDX 5 |
| #define regGDC1_BIF_RLC_DOORBELL_RANGE 0x2ffc0ef5 |
| #define regGDC1_BIF_RLC_DOORBELL_RANGE_BASE_IDX 5 |
| #define regGDC1_BIF_SDMA2_DOORBELL_RANGE 0x2ffc0ef6 |
| #define regGDC1_BIF_SDMA2_DOORBELL_RANGE_BASE_IDX 5 |
| #define regGDC1_BIF_SDMA3_DOORBELL_RANGE 0x2ffc0ef7 |
| #define regGDC1_BIF_SDMA3_DOORBELL_RANGE_BASE_IDX 5 |
| #define regGDC1_BIF_VCN1_DOORBELL_RANGE 0x2ffc0ef8 |
| #define regGDC1_BIF_VCN1_DOORBELL_RANGE_BASE_IDX 5 |
| #define regGDC1_BIF_SDMA4_DOORBELL_RANGE 0x2ffc0ef9 |
| #define regGDC1_BIF_SDMA4_DOORBELL_RANGE_BASE_IDX 5 |
| #define regGDC1_BIF_SDMA5_DOORBELL_RANGE 0x2ffc0efa |
| #define regGDC1_BIF_SDMA5_DOORBELL_RANGE_BASE_IDX 5 |
| #define regGDC1_BIF_CSDMA_DOORBELL_RANGE 0x2ffc0efb |
| #define regGDC1_BIF_CSDMA_DOORBELL_RANGE_BASE_IDX 5 |
| #define regGDC1_ATDMA_MISC_CNTL 0x2ffc0efd |
| #define regGDC1_ATDMA_MISC_CNTL_BASE_IDX 5 |
| #define regGDC1_BIF_DOORBELL_FENCE_CNTL 0x2ffc0efe |
| #define regGDC1_BIF_DOORBELL_FENCE_CNTL_BASE_IDX 5 |
| #define regGDC1_S2A_MISC_CNTL 0x2ffc0eff |
| #define regGDC1_S2A_MISC_CNTL_BASE_IDX 5 |
| #define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x2ffc0f01 |
| #define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 5 |
| #define regGDC1_NGDC_PG_MISC_CTRL 0x2ffc0f18 |
| #define regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX 5 |
| #define regGDC1_NGDC_PGMST_CTRL 0x2ffc0f19 |
| #define regGDC1_NGDC_PGMST_CTRL_BASE_IDX 5 |
| #define regGDC1_NGDC_PGSLV_CTRL 0x2ffc0f1a |
| #define regGDC1_NGDC_PGSLV_CTRL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 |
| // base address: 0xd0000000 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO 0x2ffd0800 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI 0x2ffd0801 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA 0x2ffd0802 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL 0x2ffd0803 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO 0x2ffd0804 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI 0x2ffd0805 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA 0x2ffd0806 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL 0x2ffd0807 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO 0x2ffd0808 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI 0x2ffd0809 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA 0x2ffd080a |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL 0x2ffd080b |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO 0x2ffd080c |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI 0x2ffd080d |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA 0x2ffd080e |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL 0x2ffd080f |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_BASE_IDX 5 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_PBA 0x2ffd0c00 |
| #define regRCC_DEV0_EPF0_1_GFXMSIX_PBA_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec |
| // base address: 0xfffe00000000 |
| #define regNB_NBCFG1_NB_VENDOR_ID 0x3fff7bfc0000 |
| #define regNB_NBCFG1_NB_VENDOR_ID_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_DEVICE_ID 0x3fff7bfc0000 |
| #define regNB_NBCFG1_NB_DEVICE_ID_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_COMMAND 0x3fff7bfc0001 |
| #define regNB_NBCFG1_NB_COMMAND_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_STATUS 0x3fff7bfc0001 |
| #define regNB_NBCFG1_NB_STATUS_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_REVISION_ID 0x3fff7bfc0002 |
| #define regNB_NBCFG1_NB_REVISION_ID_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_REGPROG_INF 0x3fff7bfc0002 |
| #define regNB_NBCFG1_NB_REGPROG_INF_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SUB_CLASS 0x3fff7bfc0002 |
| #define regNB_NBCFG1_NB_SUB_CLASS_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_BASE_CODE 0x3fff7bfc0002 |
| #define regNB_NBCFG1_NB_BASE_CODE_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_CACHE_LINE 0x3fff7bfc0003 |
| #define regNB_NBCFG1_NB_CACHE_LINE_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_LATENCY 0x3fff7bfc0003 |
| #define regNB_NBCFG1_NB_LATENCY_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_HEADER 0x3fff7bfc0003 |
| #define regNB_NBCFG1_NB_HEADER_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_ADAPTER_ID 0x3fff7bfc000b |
| #define regNB_NBCFG1_NB_ADAPTER_ID_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_CAPABILITIES_PTR 0x3fff7bfc000d |
| #define regNB_NBCFG1_NB_CAPABILITIES_PTR_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_HEADER_W 0x3fff7bfc0012 |
| #define regNB_NBCFG1_NB_HEADER_W_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_PCI_CTRL 0x3fff7bfc0013 |
| #define regNB_NBCFG1_NB_PCI_CTRL_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_ADAPTER_ID_W 0x3fff7bfc0014 |
| #define regNB_NBCFG1_NB_ADAPTER_ID_W_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_EXTENSION_0 0x3fff7bfc0017 |
| #define regNB_NBCFG1_NB_SMN_INDEX_EXTENSION_0_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_0 0x3fff7bfc0018 |
| #define regNB_NBCFG1_NB_SMN_INDEX_0_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_DATA_0 0x3fff7bfc0019 |
| #define regNB_NBCFG1_NB_SMN_DATA_0_BASE_IDX 5 |
| #define regNB_NBCFG1_NBCFG_SCRATCH_0 0x3fff7bfc001a |
| #define regNB_NBCFG1_NBCFG_SCRATCH_0_BASE_IDX 5 |
| #define regNB_NBCFG1_NBCFG_SCRATCH_1 0x3fff7bfc001b |
| #define regNB_NBCFG1_NBCFG_SCRATCH_1_BASE_IDX 5 |
| #define regNB_NBCFG1_NBCFG_SCRATCH_2 0x3fff7bfc001c |
| #define regNB_NBCFG1_NBCFG_SCRATCH_2_BASE_IDX 5 |
| #define regNB_NBCFG1_NBCFG_SCRATCH_3 0x3fff7bfc001d |
| #define regNB_NBCFG1_NBCFG_SCRATCH_3_BASE_IDX 5 |
| #define regNB_NBCFG1_NBCFG_SCRATCH_4 0x3fff7bfc001e |
| #define regNB_NBCFG1_NBCFG_SCRATCH_4_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_PCI_ARB 0x3fff7bfc0021 |
| #define regNB_NBCFG1_NB_PCI_ARB_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_DRAM_SLOT1_BASE 0x3fff7bfc0022 |
| #define regNB_NBCFG1_NB_DRAM_SLOT1_BASE_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_TOP_OF_DRAM_SLOT1 0x3fff7bfc0024 |
| #define regNB_NBCFG1_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_EXTENSION_1 0x3fff7bfc0027 |
| #define regNB_NBCFG1_NB_SMN_INDEX_EXTENSION_1_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_1 0x3fff7bfc0028 |
| #define regNB_NBCFG1_NB_SMN_INDEX_1_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_DATA_1 0x3fff7bfc0029 |
| #define regNB_NBCFG1_NB_SMN_DATA_1_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_INDEX_DATA_MUTEX0 0x3fff7bfc002a |
| #define regNB_NBCFG1_NB_INDEX_DATA_MUTEX0_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_INDEX_DATA_MUTEX1 0x3fff7bfc002b |
| #define regNB_NBCFG1_NB_INDEX_DATA_MUTEX1_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_EXTENSION_2 0x3fff7bfc002d |
| #define regNB_NBCFG1_NB_SMN_INDEX_EXTENSION_2_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_2 0x3fff7bfc002e |
| #define regNB_NBCFG1_NB_SMN_INDEX_2_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_DATA_2 0x3fff7bfc002f |
| #define regNB_NBCFG1_NB_SMN_DATA_2_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_EXTENSION_3 0x3fff7bfc0030 |
| #define regNB_NBCFG1_NB_SMN_INDEX_EXTENSION_3_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_3 0x3fff7bfc0031 |
| #define regNB_NBCFG1_NB_SMN_INDEX_3_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_DATA_3 0x3fff7bfc0032 |
| #define regNB_NBCFG1_NB_SMN_DATA_3_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_EXTENSION_4 0x3fff7bfc0033 |
| #define regNB_NBCFG1_NB_SMN_INDEX_EXTENSION_4_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_4 0x3fff7bfc0034 |
| #define regNB_NBCFG1_NB_SMN_INDEX_4_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_DATA_4 0x3fff7bfc0035 |
| #define regNB_NBCFG1_NB_SMN_DATA_4_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_EXTENSION_5 0x3fff7bfc0037 |
| #define regNB_NBCFG1_NB_SMN_INDEX_EXTENSION_5_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_5 0x3fff7bfc0038 |
| #define regNB_NBCFG1_NB_SMN_INDEX_5_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_DATA_5 0x3fff7bfc0039 |
| #define regNB_NBCFG1_NB_SMN_DATA_5_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_PERF_CNT_CTRL 0x3fff7bfc003d |
| #define regNB_NBCFG1_NB_PERF_CNT_CTRL_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_INDEX_6 0x3fff7bfc003e |
| #define regNB_NBCFG1_NB_SMN_INDEX_6_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_SMN_DATA_6 0x3fff7bfc003f |
| #define regNB_NBCFG1_NB_SMN_DATA_6_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_VENDOR_ID_W 0x3fff7bfc0040 |
| #define regNB_NBCFG1_NB_VENDOR_ID_W_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_DEVICE_ID_W 0x3fff7bfc0040 |
| #define regNB_NBCFG1_NB_DEVICE_ID_W_BASE_IDX 5 |
| #define regNB_NBCFG1_NB_REVISION_ID_W 0x3fff7bfc0042 |
| #define regNB_NBCFG1_NB_REVISION_ID_W_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifplr0_cfgdecp |
| // base address: 0xfffe00009000 |
| #define regBIFPLR0_2_VENDOR_ID 0x3fff7bfc2400 |
| #define regBIFPLR0_2_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR0_2_DEVICE_ID 0x3fff7bfc2400 |
| #define regBIFPLR0_2_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR0_2_COMMAND 0x3fff7bfc2401 |
| #define regBIFPLR0_2_COMMAND_BASE_IDX 5 |
| #define regBIFPLR0_2_STATUS 0x3fff7bfc2401 |
| #define regBIFPLR0_2_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_REVISION_ID 0x3fff7bfc2402 |
| #define regBIFPLR0_2_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR0_2_PROG_INTERFACE 0x3fff7bfc2402 |
| #define regBIFPLR0_2_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR0_2_SUB_CLASS 0x3fff7bfc2402 |
| #define regBIFPLR0_2_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR0_2_BASE_CLASS 0x3fff7bfc2402 |
| #define regBIFPLR0_2_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR0_2_CACHE_LINE 0x3fff7bfc2403 |
| #define regBIFPLR0_2_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR0_2_LATENCY 0x3fff7bfc2403 |
| #define regBIFPLR0_2_LATENCY_BASE_IDX 5 |
| #define regBIFPLR0_2_HEADER 0x3fff7bfc2403 |
| #define regBIFPLR0_2_HEADER_BASE_IDX 5 |
| #define regBIFPLR0_2_BIST 0x3fff7bfc2403 |
| #define regBIFPLR0_2_BIST_BASE_IDX 5 |
| #define regBIFPLR0_2_SUB_BUS_NUMBER_LATENCY 0x3fff7bfc2406 |
| #define regBIFPLR0_2_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR0_2_IO_BASE_LIMIT 0x3fff7bfc2407 |
| #define regBIFPLR0_2_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR0_2_SECONDARY_STATUS 0x3fff7bfc2407 |
| #define regBIFPLR0_2_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_MEM_BASE_LIMIT 0x3fff7bfc2408 |
| #define regBIFPLR0_2_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR0_2_PREF_BASE_LIMIT 0x3fff7bfc2409 |
| #define regBIFPLR0_2_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR0_2_PREF_BASE_UPPER 0x3fff7bfc240a |
| #define regBIFPLR0_2_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR0_2_PREF_LIMIT_UPPER 0x3fff7bfc240b |
| #define regBIFPLR0_2_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR0_2_IO_BASE_LIMIT_HI 0x3fff7bfc240c |
| #define regBIFPLR0_2_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR0_2_CAP_PTR 0x3fff7bfc240d |
| #define regBIFPLR0_2_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR0_2_INTERRUPT_LINE 0x3fff7bfc240f |
| #define regBIFPLR0_2_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR0_2_INTERRUPT_PIN 0x3fff7bfc240f |
| #define regBIFPLR0_2_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR0_2_EXT_BRIDGE_CNTL 0x3fff7bfc2410 |
| #define regBIFPLR0_2_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PMI_CAP_LIST 0x3fff7bfc2414 |
| #define regBIFPLR0_2_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PMI_CAP 0x3fff7bfc2414 |
| #define regBIFPLR0_2_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_PMI_STATUS_CNTL 0x3fff7bfc2415 |
| #define regBIFPLR0_2_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_CAP_LIST 0x3fff7bfc2416 |
| #define regBIFPLR0_2_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_CAP 0x3fff7bfc2416 |
| #define regBIFPLR0_2_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_DEVICE_CAP 0x3fff7bfc2417 |
| #define regBIFPLR0_2_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_DEVICE_CNTL 0x3fff7bfc2418 |
| #define regBIFPLR0_2_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_DEVICE_STATUS 0x3fff7bfc2418 |
| #define regBIFPLR0_2_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_LINK_CAP 0x3fff7bfc2419 |
| #define regBIFPLR0_2_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_LINK_CNTL 0x3fff7bfc241a |
| #define regBIFPLR0_2_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_LINK_STATUS 0x3fff7bfc241a |
| #define regBIFPLR0_2_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_SLOT_CAP 0x3fff7bfc241b |
| #define regBIFPLR0_2_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_SLOT_CNTL 0x3fff7bfc241c |
| #define regBIFPLR0_2_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_SLOT_STATUS 0x3fff7bfc241c |
| #define regBIFPLR0_2_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_ROOT_CNTL 0x3fff7bfc241d |
| #define regBIFPLR0_2_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_ROOT_CAP 0x3fff7bfc241d |
| #define regBIFPLR0_2_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_ROOT_STATUS 0x3fff7bfc241e |
| #define regBIFPLR0_2_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_DEVICE_CAP2 0x3fff7bfc241f |
| #define regBIFPLR0_2_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR0_2_DEVICE_CNTL2 0x3fff7bfc2420 |
| #define regBIFPLR0_2_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_2_DEVICE_STATUS2 0x3fff7bfc2420 |
| #define regBIFPLR0_2_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR0_2_LINK_CAP2 0x3fff7bfc2421 |
| #define regBIFPLR0_2_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR0_2_LINK_CNTL2 0x3fff7bfc2422 |
| #define regBIFPLR0_2_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_2_LINK_STATUS2 0x3fff7bfc2422 |
| #define regBIFPLR0_2_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR0_2_SLOT_CAP2 0x3fff7bfc2423 |
| #define regBIFPLR0_2_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR0_2_SLOT_CNTL2 0x3fff7bfc2424 |
| #define regBIFPLR0_2_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_2_SLOT_STATUS2 0x3fff7bfc2424 |
| #define regBIFPLR0_2_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR0_2_MSI_CAP_LIST 0x3fff7bfc2428 |
| #define regBIFPLR0_2_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_MSI_MSG_CNTL 0x3fff7bfc2428 |
| #define regBIFPLR0_2_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_MSI_MSG_ADDR_LO 0x3fff7bfc2429 |
| #define regBIFPLR0_2_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR0_2_MSI_MSG_ADDR_HI 0x3fff7bfc242a |
| #define regBIFPLR0_2_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR0_2_MSI_MSG_DATA 0x3fff7bfc242a |
| #define regBIFPLR0_2_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR0_2_MSI_MSG_DATA_64 0x3fff7bfc242b |
| #define regBIFPLR0_2_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR0_2_SSID_CAP_LIST 0x3fff7bfc2430 |
| #define regBIFPLR0_2_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_SSID_CAP 0x3fff7bfc2431 |
| #define regBIFPLR0_2_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_MSI_MAP_CAP_LIST 0x3fff7bfc2432 |
| #define regBIFPLR0_2_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_MSI_MAP_CAP 0x3fff7bfc2432 |
| #define regBIFPLR0_2_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff7bfc2440 |
| #define regBIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR 0x3fff7bfc2441 |
| #define regBIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_VENDOR_SPECIFIC1 0x3fff7bfc2442 |
| #define regBIFPLR0_2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_VENDOR_SPECIFIC2 0x3fff7bfc2443 |
| #define regBIFPLR0_2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_VC_ENH_CAP_LIST 0x3fff7bfc2444 |
| #define regBIFPLR0_2_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_PORT_VC_CAP_REG1 0x3fff7bfc2445 |
| #define regBIFPLR0_2_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_PORT_VC_CAP_REG2 0x3fff7bfc2446 |
| #define regBIFPLR0_2_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_PORT_VC_CNTL 0x3fff7bfc2447 |
| #define regBIFPLR0_2_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_PORT_VC_STATUS 0x3fff7bfc2447 |
| #define regBIFPLR0_2_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_VC0_RESOURCE_CAP 0x3fff7bfc2448 |
| #define regBIFPLR0_2_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_VC0_RESOURCE_CNTL 0x3fff7bfc2449 |
| #define regBIFPLR0_2_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_VC0_RESOURCE_STATUS 0x3fff7bfc244a |
| #define regBIFPLR0_2_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_VC1_RESOURCE_CAP 0x3fff7bfc244b |
| #define regBIFPLR0_2_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_VC1_RESOURCE_CNTL 0x3fff7bfc244c |
| #define regBIFPLR0_2_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_VC1_RESOURCE_STATUS 0x3fff7bfc244d |
| #define regBIFPLR0_2_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3fff7bfc2450 |
| #define regBIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1 0x3fff7bfc2451 |
| #define regBIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2 0x3fff7bfc2452 |
| #define regBIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff7bfc2454 |
| #define regBIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_UNCORR_ERR_STATUS 0x3fff7bfc2455 |
| #define regBIFPLR0_2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_UNCORR_ERR_MASK 0x3fff7bfc2456 |
| #define regBIFPLR0_2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY 0x3fff7bfc2457 |
| #define regBIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_CORR_ERR_STATUS 0x3fff7bfc2458 |
| #define regBIFPLR0_2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_CORR_ERR_MASK 0x3fff7bfc2459 |
| #define regBIFPLR0_2_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL 0x3fff7bfc245a |
| #define regBIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_HDR_LOG0 0x3fff7bfc245b |
| #define regBIFPLR0_2_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_HDR_LOG1 0x3fff7bfc245c |
| #define regBIFPLR0_2_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_HDR_LOG2 0x3fff7bfc245d |
| #define regBIFPLR0_2_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_HDR_LOG3 0x3fff7bfc245e |
| #define regBIFPLR0_2_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ROOT_ERR_CMD 0x3fff7bfc245f |
| #define regBIFPLR0_2_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ROOT_ERR_STATUS 0x3fff7bfc2460 |
| #define regBIFPLR0_2_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ERR_SRC_ID 0x3fff7bfc2461 |
| #define regBIFPLR0_2_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_TLP_PREFIX_LOG0 0x3fff7bfc2462 |
| #define regBIFPLR0_2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_TLP_PREFIX_LOG1 0x3fff7bfc2463 |
| #define regBIFPLR0_2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_TLP_PREFIX_LOG2 0x3fff7bfc2464 |
| #define regBIFPLR0_2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_TLP_PREFIX_LOG3 0x3fff7bfc2465 |
| #define regBIFPLR0_2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff7bfc249c |
| #define regBIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LINK_CNTL3 0x3fff7bfc249d |
| #define regBIFPLR0_2_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_ERROR_STATUS 0x3fff7bfc249e |
| #define regBIFPLR0_2_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff7bfc249f |
| #define regBIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff7bfc249f |
| #define regBIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff7bfc24a0 |
| #define regBIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff7bfc24a0 |
| #define regBIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff7bfc24a1 |
| #define regBIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff7bfc24a1 |
| #define regBIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff7bfc24a2 |
| #define regBIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff7bfc24a2 |
| #define regBIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff7bfc24a3 |
| #define regBIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff7bfc24a3 |
| #define regBIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff7bfc24a4 |
| #define regBIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff7bfc24a4 |
| #define regBIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff7bfc24a5 |
| #define regBIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff7bfc24a5 |
| #define regBIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff7bfc24a6 |
| #define regBIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff7bfc24a6 |
| #define regBIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ACS_ENH_CAP_LIST 0x3fff7bfc24a8 |
| #define regBIFPLR0_2_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ACS_CAP 0x3fff7bfc24a9 |
| #define regBIFPLR0_2_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ACS_CNTL 0x3fff7bfc24a9 |
| #define regBIFPLR0_2_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_ENH_CAP_LIST 0x3fff7bfc24bc |
| #define regBIFPLR0_2_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_CAP 0x3fff7bfc24bd |
| #define regBIFPLR0_2_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_CNTL 0x3fff7bfc24bd |
| #define regBIFPLR0_2_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_ADDR0 0x3fff7bfc24be |
| #define regBIFPLR0_2_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_ADDR1 0x3fff7bfc24bf |
| #define regBIFPLR0_2_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_RCV0 0x3fff7bfc24c0 |
| #define regBIFPLR0_2_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_RCV1 0x3fff7bfc24c1 |
| #define regBIFPLR0_2_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_BLOCK_ALL0 0x3fff7bfc24c2 |
| #define regBIFPLR0_2_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_BLOCK_ALL1 0x3fff7bfc24c3 |
| #define regBIFPLR0_2_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x3fff7bfc24c4 |
| #define regBIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x3fff7bfc24c5 |
| #define regBIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_OVERLAY_BAR0 0x3fff7bfc24c6 |
| #define regBIFPLR0_2_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_MC_OVERLAY_BAR1 0x3fff7bfc24c7 |
| #define regBIFPLR0_2_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST 0x3fff7bfc24dc |
| #define regBIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_L1_PM_SUB_CAP 0x3fff7bfc24dd |
| #define regBIFPLR0_2_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_L1_PM_SUB_CNTL 0x3fff7bfc24de |
| #define regBIFPLR0_2_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_L1_PM_SUB_CNTL2 0x3fff7bfc24df |
| #define regBIFPLR0_2_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_DPC_ENH_CAP_LIST 0x3fff7bfc24e0 |
| #define regBIFPLR0_2_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_DPC_CAP_LIST 0x3fff7bfc24e1 |
| #define regBIFPLR0_2_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_DPC_CNTL 0x3fff7bfc24e1 |
| #define regBIFPLR0_2_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_DPC_STATUS 0x3fff7bfc24e2 |
| #define regBIFPLR0_2_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID 0x3fff7bfc24e2 |
| #define regBIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_STATUS 0x3fff7bfc24e3 |
| #define regBIFPLR0_2_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_MASK 0x3fff7bfc24e4 |
| #define regBIFPLR0_2_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_SEVERITY 0x3fff7bfc24e5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_SYSERROR 0x3fff7bfc24e6 |
| #define regBIFPLR0_2_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_EXCEPTION 0x3fff7bfc24e7 |
| #define regBIFPLR0_2_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_HDR_LOG0 0x3fff7bfc24e8 |
| #define regBIFPLR0_2_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_HDR_LOG1 0x3fff7bfc24e9 |
| #define regBIFPLR0_2_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_HDR_LOG2 0x3fff7bfc24ea |
| #define regBIFPLR0_2_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_HDR_LOG3 0x3fff7bfc24eb |
| #define regBIFPLR0_2_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0 0x3fff7bfc24ed |
| #define regBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1 0x3fff7bfc24ee |
| #define regBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2 0x3fff7bfc24ef |
| #define regBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3 0x3fff7bfc24f0 |
| #define regBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_LIST 0x3fff7bfc24f1 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ESM_HEADER_1 0x3fff7bfc24f2 |
| #define regBIFPLR0_2_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ESM_HEADER_2 0x3fff7bfc24f3 |
| #define regBIFPLR0_2_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ESM_STATUS 0x3fff7bfc24f3 |
| #define regBIFPLR0_2_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ESM_CTRL 0x3fff7bfc24f4 |
| #define regBIFPLR0_2_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_1 0x3fff7bfc24f5 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_2 0x3fff7bfc24f6 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_3 0x3fff7bfc24f7 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_4 0x3fff7bfc24f8 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_5 0x3fff7bfc24f9 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_6 0x3fff7bfc24fa |
| #define regBIFPLR0_2_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR0_2_PCIE_ESM_CAP_7 0x3fff7bfc24fb |
| #define regBIFPLR0_2_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR0_2_LINK_CAP_16GT 0x3fff7bfc2505 |
| #define regBIFPLR0_2_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR0_2_LINK_CNTL_16GT 0x3fff7bfc2506 |
| #define regBIFPLR0_2_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR0_2_LINK_STATUS_16GT 0x3fff7bfc2507 |
| #define regBIFPLR0_2_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR0_2_LINK_CAP_32GT 0x3fff7bfc2541 |
| #define regBIFPLR0_2_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR0_2_LINK_CNTL_32GT 0x3fff7bfc2542 |
| #define regBIFPLR0_2_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR0_2_LINK_STATUS_32GT 0x3fff7bfc2543 |
| #define regBIFPLR0_2_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifplr1_cfgdecp |
| // base address: 0xfffe0000a000 |
| #define regBIFPLR1_2_VENDOR_ID 0x3fff7bfc2800 |
| #define regBIFPLR1_2_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR1_2_DEVICE_ID 0x3fff7bfc2800 |
| #define regBIFPLR1_2_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR1_2_COMMAND 0x3fff7bfc2801 |
| #define regBIFPLR1_2_COMMAND_BASE_IDX 5 |
| #define regBIFPLR1_2_STATUS 0x3fff7bfc2801 |
| #define regBIFPLR1_2_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_REVISION_ID 0x3fff7bfc2802 |
| #define regBIFPLR1_2_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR1_2_PROG_INTERFACE 0x3fff7bfc2802 |
| #define regBIFPLR1_2_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR1_2_SUB_CLASS 0x3fff7bfc2802 |
| #define regBIFPLR1_2_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR1_2_BASE_CLASS 0x3fff7bfc2802 |
| #define regBIFPLR1_2_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR1_2_CACHE_LINE 0x3fff7bfc2803 |
| #define regBIFPLR1_2_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR1_2_LATENCY 0x3fff7bfc2803 |
| #define regBIFPLR1_2_LATENCY_BASE_IDX 5 |
| #define regBIFPLR1_2_HEADER 0x3fff7bfc2803 |
| #define regBIFPLR1_2_HEADER_BASE_IDX 5 |
| #define regBIFPLR1_2_BIST 0x3fff7bfc2803 |
| #define regBIFPLR1_2_BIST_BASE_IDX 5 |
| #define regBIFPLR1_2_SUB_BUS_NUMBER_LATENCY 0x3fff7bfc2806 |
| #define regBIFPLR1_2_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR1_2_IO_BASE_LIMIT 0x3fff7bfc2807 |
| #define regBIFPLR1_2_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR1_2_SECONDARY_STATUS 0x3fff7bfc2807 |
| #define regBIFPLR1_2_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_MEM_BASE_LIMIT 0x3fff7bfc2808 |
| #define regBIFPLR1_2_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR1_2_PREF_BASE_LIMIT 0x3fff7bfc2809 |
| #define regBIFPLR1_2_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR1_2_PREF_BASE_UPPER 0x3fff7bfc280a |
| #define regBIFPLR1_2_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR1_2_PREF_LIMIT_UPPER 0x3fff7bfc280b |
| #define regBIFPLR1_2_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR1_2_IO_BASE_LIMIT_HI 0x3fff7bfc280c |
| #define regBIFPLR1_2_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR1_2_CAP_PTR 0x3fff7bfc280d |
| #define regBIFPLR1_2_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR1_2_INTERRUPT_LINE 0x3fff7bfc280f |
| #define regBIFPLR1_2_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR1_2_INTERRUPT_PIN 0x3fff7bfc280f |
| #define regBIFPLR1_2_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR1_2_EXT_BRIDGE_CNTL 0x3fff7bfc2810 |
| #define regBIFPLR1_2_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PMI_CAP_LIST 0x3fff7bfc2814 |
| #define regBIFPLR1_2_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PMI_CAP 0x3fff7bfc2814 |
| #define regBIFPLR1_2_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_PMI_STATUS_CNTL 0x3fff7bfc2815 |
| #define regBIFPLR1_2_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_CAP_LIST 0x3fff7bfc2816 |
| #define regBIFPLR1_2_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_CAP 0x3fff7bfc2816 |
| #define regBIFPLR1_2_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_DEVICE_CAP 0x3fff7bfc2817 |
| #define regBIFPLR1_2_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_DEVICE_CNTL 0x3fff7bfc2818 |
| #define regBIFPLR1_2_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_DEVICE_STATUS 0x3fff7bfc2818 |
| #define regBIFPLR1_2_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_LINK_CAP 0x3fff7bfc2819 |
| #define regBIFPLR1_2_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_LINK_CNTL 0x3fff7bfc281a |
| #define regBIFPLR1_2_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_LINK_STATUS 0x3fff7bfc281a |
| #define regBIFPLR1_2_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_SLOT_CAP 0x3fff7bfc281b |
| #define regBIFPLR1_2_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_SLOT_CNTL 0x3fff7bfc281c |
| #define regBIFPLR1_2_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_SLOT_STATUS 0x3fff7bfc281c |
| #define regBIFPLR1_2_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_ROOT_CNTL 0x3fff7bfc281d |
| #define regBIFPLR1_2_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_ROOT_CAP 0x3fff7bfc281d |
| #define regBIFPLR1_2_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_ROOT_STATUS 0x3fff7bfc281e |
| #define regBIFPLR1_2_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_DEVICE_CAP2 0x3fff7bfc281f |
| #define regBIFPLR1_2_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR1_2_DEVICE_CNTL2 0x3fff7bfc2820 |
| #define regBIFPLR1_2_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_2_DEVICE_STATUS2 0x3fff7bfc2820 |
| #define regBIFPLR1_2_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR1_2_LINK_CAP2 0x3fff7bfc2821 |
| #define regBIFPLR1_2_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR1_2_LINK_CNTL2 0x3fff7bfc2822 |
| #define regBIFPLR1_2_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_2_LINK_STATUS2 0x3fff7bfc2822 |
| #define regBIFPLR1_2_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR1_2_SLOT_CAP2 0x3fff7bfc2823 |
| #define regBIFPLR1_2_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR1_2_SLOT_CNTL2 0x3fff7bfc2824 |
| #define regBIFPLR1_2_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_2_SLOT_STATUS2 0x3fff7bfc2824 |
| #define regBIFPLR1_2_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR1_2_MSI_CAP_LIST 0x3fff7bfc2828 |
| #define regBIFPLR1_2_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_MSI_MSG_CNTL 0x3fff7bfc2828 |
| #define regBIFPLR1_2_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_MSI_MSG_ADDR_LO 0x3fff7bfc2829 |
| #define regBIFPLR1_2_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR1_2_MSI_MSG_ADDR_HI 0x3fff7bfc282a |
| #define regBIFPLR1_2_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR1_2_MSI_MSG_DATA 0x3fff7bfc282a |
| #define regBIFPLR1_2_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR1_2_MSI_MSG_DATA_64 0x3fff7bfc282b |
| #define regBIFPLR1_2_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR1_2_SSID_CAP_LIST 0x3fff7bfc2830 |
| #define regBIFPLR1_2_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_SSID_CAP 0x3fff7bfc2831 |
| #define regBIFPLR1_2_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_MSI_MAP_CAP_LIST 0x3fff7bfc2832 |
| #define regBIFPLR1_2_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_MSI_MAP_CAP 0x3fff7bfc2832 |
| #define regBIFPLR1_2_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff7bfc2840 |
| #define regBIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR 0x3fff7bfc2841 |
| #define regBIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_VENDOR_SPECIFIC1 0x3fff7bfc2842 |
| #define regBIFPLR1_2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_VENDOR_SPECIFIC2 0x3fff7bfc2843 |
| #define regBIFPLR1_2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_VC_ENH_CAP_LIST 0x3fff7bfc2844 |
| #define regBIFPLR1_2_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_PORT_VC_CAP_REG1 0x3fff7bfc2845 |
| #define regBIFPLR1_2_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_PORT_VC_CAP_REG2 0x3fff7bfc2846 |
| #define regBIFPLR1_2_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_PORT_VC_CNTL 0x3fff7bfc2847 |
| #define regBIFPLR1_2_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_PORT_VC_STATUS 0x3fff7bfc2847 |
| #define regBIFPLR1_2_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_VC0_RESOURCE_CAP 0x3fff7bfc2848 |
| #define regBIFPLR1_2_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_VC0_RESOURCE_CNTL 0x3fff7bfc2849 |
| #define regBIFPLR1_2_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_VC0_RESOURCE_STATUS 0x3fff7bfc284a |
| #define regBIFPLR1_2_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_VC1_RESOURCE_CAP 0x3fff7bfc284b |
| #define regBIFPLR1_2_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_VC1_RESOURCE_CNTL 0x3fff7bfc284c |
| #define regBIFPLR1_2_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_VC1_RESOURCE_STATUS 0x3fff7bfc284d |
| #define regBIFPLR1_2_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3fff7bfc2850 |
| #define regBIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1 0x3fff7bfc2851 |
| #define regBIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2 0x3fff7bfc2852 |
| #define regBIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff7bfc2854 |
| #define regBIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_UNCORR_ERR_STATUS 0x3fff7bfc2855 |
| #define regBIFPLR1_2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_UNCORR_ERR_MASK 0x3fff7bfc2856 |
| #define regBIFPLR1_2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY 0x3fff7bfc2857 |
| #define regBIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_CORR_ERR_STATUS 0x3fff7bfc2858 |
| #define regBIFPLR1_2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_CORR_ERR_MASK 0x3fff7bfc2859 |
| #define regBIFPLR1_2_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL 0x3fff7bfc285a |
| #define regBIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_HDR_LOG0 0x3fff7bfc285b |
| #define regBIFPLR1_2_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_HDR_LOG1 0x3fff7bfc285c |
| #define regBIFPLR1_2_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_HDR_LOG2 0x3fff7bfc285d |
| #define regBIFPLR1_2_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_HDR_LOG3 0x3fff7bfc285e |
| #define regBIFPLR1_2_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ROOT_ERR_CMD 0x3fff7bfc285f |
| #define regBIFPLR1_2_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ROOT_ERR_STATUS 0x3fff7bfc2860 |
| #define regBIFPLR1_2_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ERR_SRC_ID 0x3fff7bfc2861 |
| #define regBIFPLR1_2_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_TLP_PREFIX_LOG0 0x3fff7bfc2862 |
| #define regBIFPLR1_2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_TLP_PREFIX_LOG1 0x3fff7bfc2863 |
| #define regBIFPLR1_2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_TLP_PREFIX_LOG2 0x3fff7bfc2864 |
| #define regBIFPLR1_2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_TLP_PREFIX_LOG3 0x3fff7bfc2865 |
| #define regBIFPLR1_2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff7bfc289c |
| #define regBIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LINK_CNTL3 0x3fff7bfc289d |
| #define regBIFPLR1_2_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_ERROR_STATUS 0x3fff7bfc289e |
| #define regBIFPLR1_2_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff7bfc289f |
| #define regBIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff7bfc289f |
| #define regBIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff7bfc28a0 |
| #define regBIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff7bfc28a0 |
| #define regBIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff7bfc28a1 |
| #define regBIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff7bfc28a1 |
| #define regBIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff7bfc28a2 |
| #define regBIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff7bfc28a2 |
| #define regBIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff7bfc28a3 |
| #define regBIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff7bfc28a3 |
| #define regBIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff7bfc28a4 |
| #define regBIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff7bfc28a4 |
| #define regBIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff7bfc28a5 |
| #define regBIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff7bfc28a5 |
| #define regBIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff7bfc28a6 |
| #define regBIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff7bfc28a6 |
| #define regBIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ACS_ENH_CAP_LIST 0x3fff7bfc28a8 |
| #define regBIFPLR1_2_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ACS_CAP 0x3fff7bfc28a9 |
| #define regBIFPLR1_2_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ACS_CNTL 0x3fff7bfc28a9 |
| #define regBIFPLR1_2_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_ENH_CAP_LIST 0x3fff7bfc28bc |
| #define regBIFPLR1_2_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_CAP 0x3fff7bfc28bd |
| #define regBIFPLR1_2_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_CNTL 0x3fff7bfc28bd |
| #define regBIFPLR1_2_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_ADDR0 0x3fff7bfc28be |
| #define regBIFPLR1_2_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_ADDR1 0x3fff7bfc28bf |
| #define regBIFPLR1_2_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_RCV0 0x3fff7bfc28c0 |
| #define regBIFPLR1_2_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_RCV1 0x3fff7bfc28c1 |
| #define regBIFPLR1_2_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_BLOCK_ALL0 0x3fff7bfc28c2 |
| #define regBIFPLR1_2_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_BLOCK_ALL1 0x3fff7bfc28c3 |
| #define regBIFPLR1_2_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x3fff7bfc28c4 |
| #define regBIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x3fff7bfc28c5 |
| #define regBIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_OVERLAY_BAR0 0x3fff7bfc28c6 |
| #define regBIFPLR1_2_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_MC_OVERLAY_BAR1 0x3fff7bfc28c7 |
| #define regBIFPLR1_2_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST 0x3fff7bfc28dc |
| #define regBIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_L1_PM_SUB_CAP 0x3fff7bfc28dd |
| #define regBIFPLR1_2_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_L1_PM_SUB_CNTL 0x3fff7bfc28de |
| #define regBIFPLR1_2_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_L1_PM_SUB_CNTL2 0x3fff7bfc28df |
| #define regBIFPLR1_2_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_DPC_ENH_CAP_LIST 0x3fff7bfc28e0 |
| #define regBIFPLR1_2_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_DPC_CAP_LIST 0x3fff7bfc28e1 |
| #define regBIFPLR1_2_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_DPC_CNTL 0x3fff7bfc28e1 |
| #define regBIFPLR1_2_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_DPC_STATUS 0x3fff7bfc28e2 |
| #define regBIFPLR1_2_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID 0x3fff7bfc28e2 |
| #define regBIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_STATUS 0x3fff7bfc28e3 |
| #define regBIFPLR1_2_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_MASK 0x3fff7bfc28e4 |
| #define regBIFPLR1_2_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_SEVERITY 0x3fff7bfc28e5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_SYSERROR 0x3fff7bfc28e6 |
| #define regBIFPLR1_2_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_EXCEPTION 0x3fff7bfc28e7 |
| #define regBIFPLR1_2_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_HDR_LOG0 0x3fff7bfc28e8 |
| #define regBIFPLR1_2_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_HDR_LOG1 0x3fff7bfc28e9 |
| #define regBIFPLR1_2_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_HDR_LOG2 0x3fff7bfc28ea |
| #define regBIFPLR1_2_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_HDR_LOG3 0x3fff7bfc28eb |
| #define regBIFPLR1_2_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0 0x3fff7bfc28ed |
| #define regBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1 0x3fff7bfc28ee |
| #define regBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2 0x3fff7bfc28ef |
| #define regBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3 0x3fff7bfc28f0 |
| #define regBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_LIST 0x3fff7bfc28f1 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ESM_HEADER_1 0x3fff7bfc28f2 |
| #define regBIFPLR1_2_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ESM_HEADER_2 0x3fff7bfc28f3 |
| #define regBIFPLR1_2_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ESM_STATUS 0x3fff7bfc28f3 |
| #define regBIFPLR1_2_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ESM_CTRL 0x3fff7bfc28f4 |
| #define regBIFPLR1_2_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_1 0x3fff7bfc28f5 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_2 0x3fff7bfc28f6 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_3 0x3fff7bfc28f7 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_4 0x3fff7bfc28f8 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_5 0x3fff7bfc28f9 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_6 0x3fff7bfc28fa |
| #define regBIFPLR1_2_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR1_2_PCIE_ESM_CAP_7 0x3fff7bfc28fb |
| #define regBIFPLR1_2_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR1_2_LINK_CAP_16GT 0x3fff7bfc2905 |
| #define regBIFPLR1_2_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR1_2_LINK_CNTL_16GT 0x3fff7bfc2906 |
| #define regBIFPLR1_2_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR1_2_LINK_STATUS_16GT 0x3fff7bfc2907 |
| #define regBIFPLR1_2_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR1_2_LINK_CAP_32GT 0x3fff7bfc2941 |
| #define regBIFPLR1_2_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR1_2_LINK_CNTL_32GT 0x3fff7bfc2942 |
| #define regBIFPLR1_2_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR1_2_LINK_STATUS_32GT 0x3fff7bfc2943 |
| #define regBIFPLR1_2_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifplr2_cfgdecp |
| // base address: 0xfffe0000b000 |
| #define regBIFPLR2_2_VENDOR_ID 0x3fff7bfc2c00 |
| #define regBIFPLR2_2_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR2_2_DEVICE_ID 0x3fff7bfc2c00 |
| #define regBIFPLR2_2_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR2_2_COMMAND 0x3fff7bfc2c01 |
| #define regBIFPLR2_2_COMMAND_BASE_IDX 5 |
| #define regBIFPLR2_2_STATUS 0x3fff7bfc2c01 |
| #define regBIFPLR2_2_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_REVISION_ID 0x3fff7bfc2c02 |
| #define regBIFPLR2_2_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR2_2_PROG_INTERFACE 0x3fff7bfc2c02 |
| #define regBIFPLR2_2_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR2_2_SUB_CLASS 0x3fff7bfc2c02 |
| #define regBIFPLR2_2_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR2_2_BASE_CLASS 0x3fff7bfc2c02 |
| #define regBIFPLR2_2_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR2_2_CACHE_LINE 0x3fff7bfc2c03 |
| #define regBIFPLR2_2_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR2_2_LATENCY 0x3fff7bfc2c03 |
| #define regBIFPLR2_2_LATENCY_BASE_IDX 5 |
| #define regBIFPLR2_2_HEADER 0x3fff7bfc2c03 |
| #define regBIFPLR2_2_HEADER_BASE_IDX 5 |
| #define regBIFPLR2_2_BIST 0x3fff7bfc2c03 |
| #define regBIFPLR2_2_BIST_BASE_IDX 5 |
| #define regBIFPLR2_2_SUB_BUS_NUMBER_LATENCY 0x3fff7bfc2c06 |
| #define regBIFPLR2_2_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR2_2_IO_BASE_LIMIT 0x3fff7bfc2c07 |
| #define regBIFPLR2_2_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR2_2_SECONDARY_STATUS 0x3fff7bfc2c07 |
| #define regBIFPLR2_2_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_MEM_BASE_LIMIT 0x3fff7bfc2c08 |
| #define regBIFPLR2_2_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR2_2_PREF_BASE_LIMIT 0x3fff7bfc2c09 |
| #define regBIFPLR2_2_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR2_2_PREF_BASE_UPPER 0x3fff7bfc2c0a |
| #define regBIFPLR2_2_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR2_2_PREF_LIMIT_UPPER 0x3fff7bfc2c0b |
| #define regBIFPLR2_2_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR2_2_IO_BASE_LIMIT_HI 0x3fff7bfc2c0c |
| #define regBIFPLR2_2_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR2_2_CAP_PTR 0x3fff7bfc2c0d |
| #define regBIFPLR2_2_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR2_2_INTERRUPT_LINE 0x3fff7bfc2c0f |
| #define regBIFPLR2_2_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR2_2_INTERRUPT_PIN 0x3fff7bfc2c0f |
| #define regBIFPLR2_2_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR2_2_EXT_BRIDGE_CNTL 0x3fff7bfc2c10 |
| #define regBIFPLR2_2_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PMI_CAP_LIST 0x3fff7bfc2c14 |
| #define regBIFPLR2_2_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PMI_CAP 0x3fff7bfc2c14 |
| #define regBIFPLR2_2_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_PMI_STATUS_CNTL 0x3fff7bfc2c15 |
| #define regBIFPLR2_2_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_CAP_LIST 0x3fff7bfc2c16 |
| #define regBIFPLR2_2_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_CAP 0x3fff7bfc2c16 |
| #define regBIFPLR2_2_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_DEVICE_CAP 0x3fff7bfc2c17 |
| #define regBIFPLR2_2_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_DEVICE_CNTL 0x3fff7bfc2c18 |
| #define regBIFPLR2_2_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_DEVICE_STATUS 0x3fff7bfc2c18 |
| #define regBIFPLR2_2_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_LINK_CAP 0x3fff7bfc2c19 |
| #define regBIFPLR2_2_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_LINK_CNTL 0x3fff7bfc2c1a |
| #define regBIFPLR2_2_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_LINK_STATUS 0x3fff7bfc2c1a |
| #define regBIFPLR2_2_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_SLOT_CAP 0x3fff7bfc2c1b |
| #define regBIFPLR2_2_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_SLOT_CNTL 0x3fff7bfc2c1c |
| #define regBIFPLR2_2_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_SLOT_STATUS 0x3fff7bfc2c1c |
| #define regBIFPLR2_2_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_ROOT_CNTL 0x3fff7bfc2c1d |
| #define regBIFPLR2_2_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_ROOT_CAP 0x3fff7bfc2c1d |
| #define regBIFPLR2_2_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_ROOT_STATUS 0x3fff7bfc2c1e |
| #define regBIFPLR2_2_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_DEVICE_CAP2 0x3fff7bfc2c1f |
| #define regBIFPLR2_2_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR2_2_DEVICE_CNTL2 0x3fff7bfc2c20 |
| #define regBIFPLR2_2_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_2_DEVICE_STATUS2 0x3fff7bfc2c20 |
| #define regBIFPLR2_2_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR2_2_LINK_CAP2 0x3fff7bfc2c21 |
| #define regBIFPLR2_2_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR2_2_LINK_CNTL2 0x3fff7bfc2c22 |
| #define regBIFPLR2_2_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_2_LINK_STATUS2 0x3fff7bfc2c22 |
| #define regBIFPLR2_2_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR2_2_SLOT_CAP2 0x3fff7bfc2c23 |
| #define regBIFPLR2_2_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR2_2_SLOT_CNTL2 0x3fff7bfc2c24 |
| #define regBIFPLR2_2_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_2_SLOT_STATUS2 0x3fff7bfc2c24 |
| #define regBIFPLR2_2_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR2_2_MSI_CAP_LIST 0x3fff7bfc2c28 |
| #define regBIFPLR2_2_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_MSI_MSG_CNTL 0x3fff7bfc2c28 |
| #define regBIFPLR2_2_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_MSI_MSG_ADDR_LO 0x3fff7bfc2c29 |
| #define regBIFPLR2_2_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR2_2_MSI_MSG_ADDR_HI 0x3fff7bfc2c2a |
| #define regBIFPLR2_2_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR2_2_MSI_MSG_DATA 0x3fff7bfc2c2a |
| #define regBIFPLR2_2_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR2_2_MSI_MSG_DATA_64 0x3fff7bfc2c2b |
| #define regBIFPLR2_2_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR2_2_SSID_CAP_LIST 0x3fff7bfc2c30 |
| #define regBIFPLR2_2_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_SSID_CAP 0x3fff7bfc2c31 |
| #define regBIFPLR2_2_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_MSI_MAP_CAP_LIST 0x3fff7bfc2c32 |
| #define regBIFPLR2_2_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_MSI_MAP_CAP 0x3fff7bfc2c32 |
| #define regBIFPLR2_2_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff7bfc2c40 |
| #define regBIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR 0x3fff7bfc2c41 |
| #define regBIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_VENDOR_SPECIFIC1 0x3fff7bfc2c42 |
| #define regBIFPLR2_2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_VENDOR_SPECIFIC2 0x3fff7bfc2c43 |
| #define regBIFPLR2_2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_VC_ENH_CAP_LIST 0x3fff7bfc2c44 |
| #define regBIFPLR2_2_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_PORT_VC_CAP_REG1 0x3fff7bfc2c45 |
| #define regBIFPLR2_2_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_PORT_VC_CAP_REG2 0x3fff7bfc2c46 |
| #define regBIFPLR2_2_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_PORT_VC_CNTL 0x3fff7bfc2c47 |
| #define regBIFPLR2_2_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_PORT_VC_STATUS 0x3fff7bfc2c47 |
| #define regBIFPLR2_2_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_VC0_RESOURCE_CAP 0x3fff7bfc2c48 |
| #define regBIFPLR2_2_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_VC0_RESOURCE_CNTL 0x3fff7bfc2c49 |
| #define regBIFPLR2_2_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_VC0_RESOURCE_STATUS 0x3fff7bfc2c4a |
| #define regBIFPLR2_2_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_VC1_RESOURCE_CAP 0x3fff7bfc2c4b |
| #define regBIFPLR2_2_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_VC1_RESOURCE_CNTL 0x3fff7bfc2c4c |
| #define regBIFPLR2_2_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_VC1_RESOURCE_STATUS 0x3fff7bfc2c4d |
| #define regBIFPLR2_2_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3fff7bfc2c50 |
| #define regBIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1 0x3fff7bfc2c51 |
| #define regBIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2 0x3fff7bfc2c52 |
| #define regBIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff7bfc2c54 |
| #define regBIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_UNCORR_ERR_STATUS 0x3fff7bfc2c55 |
| #define regBIFPLR2_2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_UNCORR_ERR_MASK 0x3fff7bfc2c56 |
| #define regBIFPLR2_2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY 0x3fff7bfc2c57 |
| #define regBIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_CORR_ERR_STATUS 0x3fff7bfc2c58 |
| #define regBIFPLR2_2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_CORR_ERR_MASK 0x3fff7bfc2c59 |
| #define regBIFPLR2_2_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL 0x3fff7bfc2c5a |
| #define regBIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_HDR_LOG0 0x3fff7bfc2c5b |
| #define regBIFPLR2_2_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_HDR_LOG1 0x3fff7bfc2c5c |
| #define regBIFPLR2_2_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_HDR_LOG2 0x3fff7bfc2c5d |
| #define regBIFPLR2_2_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_HDR_LOG3 0x3fff7bfc2c5e |
| #define regBIFPLR2_2_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ROOT_ERR_CMD 0x3fff7bfc2c5f |
| #define regBIFPLR2_2_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ROOT_ERR_STATUS 0x3fff7bfc2c60 |
| #define regBIFPLR2_2_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ERR_SRC_ID 0x3fff7bfc2c61 |
| #define regBIFPLR2_2_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_TLP_PREFIX_LOG0 0x3fff7bfc2c62 |
| #define regBIFPLR2_2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_TLP_PREFIX_LOG1 0x3fff7bfc2c63 |
| #define regBIFPLR2_2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_TLP_PREFIX_LOG2 0x3fff7bfc2c64 |
| #define regBIFPLR2_2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_TLP_PREFIX_LOG3 0x3fff7bfc2c65 |
| #define regBIFPLR2_2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff7bfc2c9c |
| #define regBIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LINK_CNTL3 0x3fff7bfc2c9d |
| #define regBIFPLR2_2_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_ERROR_STATUS 0x3fff7bfc2c9e |
| #define regBIFPLR2_2_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff7bfc2c9f |
| #define regBIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff7bfc2c9f |
| #define regBIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff7bfc2ca0 |
| #define regBIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff7bfc2ca0 |
| #define regBIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff7bfc2ca1 |
| #define regBIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff7bfc2ca1 |
| #define regBIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff7bfc2ca2 |
| #define regBIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff7bfc2ca2 |
| #define regBIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff7bfc2ca3 |
| #define regBIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff7bfc2ca3 |
| #define regBIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff7bfc2ca4 |
| #define regBIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff7bfc2ca4 |
| #define regBIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff7bfc2ca5 |
| #define regBIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff7bfc2ca5 |
| #define regBIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff7bfc2ca6 |
| #define regBIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff7bfc2ca6 |
| #define regBIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ACS_ENH_CAP_LIST 0x3fff7bfc2ca8 |
| #define regBIFPLR2_2_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ACS_CAP 0x3fff7bfc2ca9 |
| #define regBIFPLR2_2_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ACS_CNTL 0x3fff7bfc2ca9 |
| #define regBIFPLR2_2_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_ENH_CAP_LIST 0x3fff7bfc2cbc |
| #define regBIFPLR2_2_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_CAP 0x3fff7bfc2cbd |
| #define regBIFPLR2_2_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_CNTL 0x3fff7bfc2cbd |
| #define regBIFPLR2_2_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_ADDR0 0x3fff7bfc2cbe |
| #define regBIFPLR2_2_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_ADDR1 0x3fff7bfc2cbf |
| #define regBIFPLR2_2_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_RCV0 0x3fff7bfc2cc0 |
| #define regBIFPLR2_2_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_RCV1 0x3fff7bfc2cc1 |
| #define regBIFPLR2_2_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_BLOCK_ALL0 0x3fff7bfc2cc2 |
| #define regBIFPLR2_2_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_BLOCK_ALL1 0x3fff7bfc2cc3 |
| #define regBIFPLR2_2_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x3fff7bfc2cc4 |
| #define regBIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x3fff7bfc2cc5 |
| #define regBIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_OVERLAY_BAR0 0x3fff7bfc2cc6 |
| #define regBIFPLR2_2_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_MC_OVERLAY_BAR1 0x3fff7bfc2cc7 |
| #define regBIFPLR2_2_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST 0x3fff7bfc2cdc |
| #define regBIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_L1_PM_SUB_CAP 0x3fff7bfc2cdd |
| #define regBIFPLR2_2_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_L1_PM_SUB_CNTL 0x3fff7bfc2cde |
| #define regBIFPLR2_2_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_L1_PM_SUB_CNTL2 0x3fff7bfc2cdf |
| #define regBIFPLR2_2_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_DPC_ENH_CAP_LIST 0x3fff7bfc2ce0 |
| #define regBIFPLR2_2_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_DPC_CAP_LIST 0x3fff7bfc2ce1 |
| #define regBIFPLR2_2_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_DPC_CNTL 0x3fff7bfc2ce1 |
| #define regBIFPLR2_2_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_DPC_STATUS 0x3fff7bfc2ce2 |
| #define regBIFPLR2_2_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID 0x3fff7bfc2ce2 |
| #define regBIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_STATUS 0x3fff7bfc2ce3 |
| #define regBIFPLR2_2_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_MASK 0x3fff7bfc2ce4 |
| #define regBIFPLR2_2_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_SEVERITY 0x3fff7bfc2ce5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_SYSERROR 0x3fff7bfc2ce6 |
| #define regBIFPLR2_2_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_EXCEPTION 0x3fff7bfc2ce7 |
| #define regBIFPLR2_2_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_HDR_LOG0 0x3fff7bfc2ce8 |
| #define regBIFPLR2_2_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_HDR_LOG1 0x3fff7bfc2ce9 |
| #define regBIFPLR2_2_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_HDR_LOG2 0x3fff7bfc2cea |
| #define regBIFPLR2_2_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_HDR_LOG3 0x3fff7bfc2ceb |
| #define regBIFPLR2_2_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0 0x3fff7bfc2ced |
| #define regBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1 0x3fff7bfc2cee |
| #define regBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2 0x3fff7bfc2cef |
| #define regBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3 0x3fff7bfc2cf0 |
| #define regBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_LIST 0x3fff7bfc2cf1 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ESM_HEADER_1 0x3fff7bfc2cf2 |
| #define regBIFPLR2_2_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ESM_HEADER_2 0x3fff7bfc2cf3 |
| #define regBIFPLR2_2_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ESM_STATUS 0x3fff7bfc2cf3 |
| #define regBIFPLR2_2_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ESM_CTRL 0x3fff7bfc2cf4 |
| #define regBIFPLR2_2_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_1 0x3fff7bfc2cf5 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_2 0x3fff7bfc2cf6 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_3 0x3fff7bfc2cf7 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_4 0x3fff7bfc2cf8 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_5 0x3fff7bfc2cf9 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_6 0x3fff7bfc2cfa |
| #define regBIFPLR2_2_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR2_2_PCIE_ESM_CAP_7 0x3fff7bfc2cfb |
| #define regBIFPLR2_2_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR2_2_LINK_CAP_16GT 0x3fff7bfc2d05 |
| #define regBIFPLR2_2_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR2_2_LINK_CNTL_16GT 0x3fff7bfc2d06 |
| #define regBIFPLR2_2_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR2_2_LINK_STATUS_16GT 0x3fff7bfc2d07 |
| #define regBIFPLR2_2_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR2_2_LINK_CAP_32GT 0x3fff7bfc2d41 |
| #define regBIFPLR2_2_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR2_2_LINK_CNTL_32GT 0x3fff7bfc2d42 |
| #define regBIFPLR2_2_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR2_2_LINK_STATUS_32GT 0x3fff7bfc2d43 |
| #define regBIFPLR2_2_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifplr3_cfgdecp |
| // base address: 0xfffe0000c000 |
| #define regBIFPLR3_2_VENDOR_ID 0x3fff7bfc3000 |
| #define regBIFPLR3_2_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR3_2_DEVICE_ID 0x3fff7bfc3000 |
| #define regBIFPLR3_2_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR3_2_COMMAND 0x3fff7bfc3001 |
| #define regBIFPLR3_2_COMMAND_BASE_IDX 5 |
| #define regBIFPLR3_2_STATUS 0x3fff7bfc3001 |
| #define regBIFPLR3_2_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_REVISION_ID 0x3fff7bfc3002 |
| #define regBIFPLR3_2_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR3_2_PROG_INTERFACE 0x3fff7bfc3002 |
| #define regBIFPLR3_2_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR3_2_SUB_CLASS 0x3fff7bfc3002 |
| #define regBIFPLR3_2_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR3_2_BASE_CLASS 0x3fff7bfc3002 |
| #define regBIFPLR3_2_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR3_2_CACHE_LINE 0x3fff7bfc3003 |
| #define regBIFPLR3_2_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR3_2_LATENCY 0x3fff7bfc3003 |
| #define regBIFPLR3_2_LATENCY_BASE_IDX 5 |
| #define regBIFPLR3_2_HEADER 0x3fff7bfc3003 |
| #define regBIFPLR3_2_HEADER_BASE_IDX 5 |
| #define regBIFPLR3_2_BIST 0x3fff7bfc3003 |
| #define regBIFPLR3_2_BIST_BASE_IDX 5 |
| #define regBIFPLR3_2_SUB_BUS_NUMBER_LATENCY 0x3fff7bfc3006 |
| #define regBIFPLR3_2_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR3_2_IO_BASE_LIMIT 0x3fff7bfc3007 |
| #define regBIFPLR3_2_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR3_2_SECONDARY_STATUS 0x3fff7bfc3007 |
| #define regBIFPLR3_2_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_MEM_BASE_LIMIT 0x3fff7bfc3008 |
| #define regBIFPLR3_2_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR3_2_PREF_BASE_LIMIT 0x3fff7bfc3009 |
| #define regBIFPLR3_2_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR3_2_PREF_BASE_UPPER 0x3fff7bfc300a |
| #define regBIFPLR3_2_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR3_2_PREF_LIMIT_UPPER 0x3fff7bfc300b |
| #define regBIFPLR3_2_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR3_2_IO_BASE_LIMIT_HI 0x3fff7bfc300c |
| #define regBIFPLR3_2_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR3_2_CAP_PTR 0x3fff7bfc300d |
| #define regBIFPLR3_2_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR3_2_INTERRUPT_LINE 0x3fff7bfc300f |
| #define regBIFPLR3_2_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR3_2_INTERRUPT_PIN 0x3fff7bfc300f |
| #define regBIFPLR3_2_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR3_2_EXT_BRIDGE_CNTL 0x3fff7bfc3010 |
| #define regBIFPLR3_2_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PMI_CAP_LIST 0x3fff7bfc3014 |
| #define regBIFPLR3_2_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PMI_CAP 0x3fff7bfc3014 |
| #define regBIFPLR3_2_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_PMI_STATUS_CNTL 0x3fff7bfc3015 |
| #define regBIFPLR3_2_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_CAP_LIST 0x3fff7bfc3016 |
| #define regBIFPLR3_2_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_CAP 0x3fff7bfc3016 |
| #define regBIFPLR3_2_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_DEVICE_CAP 0x3fff7bfc3017 |
| #define regBIFPLR3_2_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_DEVICE_CNTL 0x3fff7bfc3018 |
| #define regBIFPLR3_2_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_DEVICE_STATUS 0x3fff7bfc3018 |
| #define regBIFPLR3_2_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_LINK_CAP 0x3fff7bfc3019 |
| #define regBIFPLR3_2_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_LINK_CNTL 0x3fff7bfc301a |
| #define regBIFPLR3_2_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_LINK_STATUS 0x3fff7bfc301a |
| #define regBIFPLR3_2_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_SLOT_CAP 0x3fff7bfc301b |
| #define regBIFPLR3_2_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_SLOT_CNTL 0x3fff7bfc301c |
| #define regBIFPLR3_2_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_SLOT_STATUS 0x3fff7bfc301c |
| #define regBIFPLR3_2_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_ROOT_CNTL 0x3fff7bfc301d |
| #define regBIFPLR3_2_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_ROOT_CAP 0x3fff7bfc301d |
| #define regBIFPLR3_2_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_ROOT_STATUS 0x3fff7bfc301e |
| #define regBIFPLR3_2_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_DEVICE_CAP2 0x3fff7bfc301f |
| #define regBIFPLR3_2_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR3_2_DEVICE_CNTL2 0x3fff7bfc3020 |
| #define regBIFPLR3_2_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_2_DEVICE_STATUS2 0x3fff7bfc3020 |
| #define regBIFPLR3_2_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR3_2_LINK_CAP2 0x3fff7bfc3021 |
| #define regBIFPLR3_2_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR3_2_LINK_CNTL2 0x3fff7bfc3022 |
| #define regBIFPLR3_2_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_2_LINK_STATUS2 0x3fff7bfc3022 |
| #define regBIFPLR3_2_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR3_2_SLOT_CAP2 0x3fff7bfc3023 |
| #define regBIFPLR3_2_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR3_2_SLOT_CNTL2 0x3fff7bfc3024 |
| #define regBIFPLR3_2_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_2_SLOT_STATUS2 0x3fff7bfc3024 |
| #define regBIFPLR3_2_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR3_2_MSI_CAP_LIST 0x3fff7bfc3028 |
| #define regBIFPLR3_2_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_MSI_MSG_CNTL 0x3fff7bfc3028 |
| #define regBIFPLR3_2_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_MSI_MSG_ADDR_LO 0x3fff7bfc3029 |
| #define regBIFPLR3_2_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR3_2_MSI_MSG_ADDR_HI 0x3fff7bfc302a |
| #define regBIFPLR3_2_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR3_2_MSI_MSG_DATA 0x3fff7bfc302a |
| #define regBIFPLR3_2_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR3_2_MSI_MSG_DATA_64 0x3fff7bfc302b |
| #define regBIFPLR3_2_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR3_2_SSID_CAP_LIST 0x3fff7bfc3030 |
| #define regBIFPLR3_2_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_SSID_CAP 0x3fff7bfc3031 |
| #define regBIFPLR3_2_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_MSI_MAP_CAP_LIST 0x3fff7bfc3032 |
| #define regBIFPLR3_2_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_MSI_MAP_CAP 0x3fff7bfc3032 |
| #define regBIFPLR3_2_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff7bfc3040 |
| #define regBIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR 0x3fff7bfc3041 |
| #define regBIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_VENDOR_SPECIFIC1 0x3fff7bfc3042 |
| #define regBIFPLR3_2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_VENDOR_SPECIFIC2 0x3fff7bfc3043 |
| #define regBIFPLR3_2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_VC_ENH_CAP_LIST 0x3fff7bfc3044 |
| #define regBIFPLR3_2_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_PORT_VC_CAP_REG1 0x3fff7bfc3045 |
| #define regBIFPLR3_2_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_PORT_VC_CAP_REG2 0x3fff7bfc3046 |
| #define regBIFPLR3_2_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_PORT_VC_CNTL 0x3fff7bfc3047 |
| #define regBIFPLR3_2_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_PORT_VC_STATUS 0x3fff7bfc3047 |
| #define regBIFPLR3_2_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_VC0_RESOURCE_CAP 0x3fff7bfc3048 |
| #define regBIFPLR3_2_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_VC0_RESOURCE_CNTL 0x3fff7bfc3049 |
| #define regBIFPLR3_2_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_VC0_RESOURCE_STATUS 0x3fff7bfc304a |
| #define regBIFPLR3_2_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_VC1_RESOURCE_CAP 0x3fff7bfc304b |
| #define regBIFPLR3_2_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_VC1_RESOURCE_CNTL 0x3fff7bfc304c |
| #define regBIFPLR3_2_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_VC1_RESOURCE_STATUS 0x3fff7bfc304d |
| #define regBIFPLR3_2_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3fff7bfc3050 |
| #define regBIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1 0x3fff7bfc3051 |
| #define regBIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2 0x3fff7bfc3052 |
| #define regBIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff7bfc3054 |
| #define regBIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_UNCORR_ERR_STATUS 0x3fff7bfc3055 |
| #define regBIFPLR3_2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_UNCORR_ERR_MASK 0x3fff7bfc3056 |
| #define regBIFPLR3_2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY 0x3fff7bfc3057 |
| #define regBIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_CORR_ERR_STATUS 0x3fff7bfc3058 |
| #define regBIFPLR3_2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_CORR_ERR_MASK 0x3fff7bfc3059 |
| #define regBIFPLR3_2_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL 0x3fff7bfc305a |
| #define regBIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_HDR_LOG0 0x3fff7bfc305b |
| #define regBIFPLR3_2_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_HDR_LOG1 0x3fff7bfc305c |
| #define regBIFPLR3_2_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_HDR_LOG2 0x3fff7bfc305d |
| #define regBIFPLR3_2_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_HDR_LOG3 0x3fff7bfc305e |
| #define regBIFPLR3_2_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ROOT_ERR_CMD 0x3fff7bfc305f |
| #define regBIFPLR3_2_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ROOT_ERR_STATUS 0x3fff7bfc3060 |
| #define regBIFPLR3_2_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ERR_SRC_ID 0x3fff7bfc3061 |
| #define regBIFPLR3_2_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_TLP_PREFIX_LOG0 0x3fff7bfc3062 |
| #define regBIFPLR3_2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_TLP_PREFIX_LOG1 0x3fff7bfc3063 |
| #define regBIFPLR3_2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_TLP_PREFIX_LOG2 0x3fff7bfc3064 |
| #define regBIFPLR3_2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_TLP_PREFIX_LOG3 0x3fff7bfc3065 |
| #define regBIFPLR3_2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff7bfc309c |
| #define regBIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LINK_CNTL3 0x3fff7bfc309d |
| #define regBIFPLR3_2_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_ERROR_STATUS 0x3fff7bfc309e |
| #define regBIFPLR3_2_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff7bfc309f |
| #define regBIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff7bfc309f |
| #define regBIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff7bfc30a0 |
| #define regBIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff7bfc30a0 |
| #define regBIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff7bfc30a1 |
| #define regBIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff7bfc30a1 |
| #define regBIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff7bfc30a2 |
| #define regBIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff7bfc30a2 |
| #define regBIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff7bfc30a3 |
| #define regBIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff7bfc30a3 |
| #define regBIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff7bfc30a4 |
| #define regBIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff7bfc30a4 |
| #define regBIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff7bfc30a5 |
| #define regBIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff7bfc30a5 |
| #define regBIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff7bfc30a6 |
| #define regBIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff7bfc30a6 |
| #define regBIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ACS_ENH_CAP_LIST 0x3fff7bfc30a8 |
| #define regBIFPLR3_2_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ACS_CAP 0x3fff7bfc30a9 |
| #define regBIFPLR3_2_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ACS_CNTL 0x3fff7bfc30a9 |
| #define regBIFPLR3_2_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_ENH_CAP_LIST 0x3fff7bfc30bc |
| #define regBIFPLR3_2_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_CAP 0x3fff7bfc30bd |
| #define regBIFPLR3_2_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_CNTL 0x3fff7bfc30bd |
| #define regBIFPLR3_2_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_ADDR0 0x3fff7bfc30be |
| #define regBIFPLR3_2_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_ADDR1 0x3fff7bfc30bf |
| #define regBIFPLR3_2_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_RCV0 0x3fff7bfc30c0 |
| #define regBIFPLR3_2_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_RCV1 0x3fff7bfc30c1 |
| #define regBIFPLR3_2_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_BLOCK_ALL0 0x3fff7bfc30c2 |
| #define regBIFPLR3_2_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_BLOCK_ALL1 0x3fff7bfc30c3 |
| #define regBIFPLR3_2_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x3fff7bfc30c4 |
| #define regBIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x3fff7bfc30c5 |
| #define regBIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_OVERLAY_BAR0 0x3fff7bfc30c6 |
| #define regBIFPLR3_2_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_MC_OVERLAY_BAR1 0x3fff7bfc30c7 |
| #define regBIFPLR3_2_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST 0x3fff7bfc30dc |
| #define regBIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_L1_PM_SUB_CAP 0x3fff7bfc30dd |
| #define regBIFPLR3_2_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_L1_PM_SUB_CNTL 0x3fff7bfc30de |
| #define regBIFPLR3_2_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_L1_PM_SUB_CNTL2 0x3fff7bfc30df |
| #define regBIFPLR3_2_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_DPC_ENH_CAP_LIST 0x3fff7bfc30e0 |
| #define regBIFPLR3_2_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_DPC_CAP_LIST 0x3fff7bfc30e1 |
| #define regBIFPLR3_2_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_DPC_CNTL 0x3fff7bfc30e1 |
| #define regBIFPLR3_2_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_DPC_STATUS 0x3fff7bfc30e2 |
| #define regBIFPLR3_2_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID 0x3fff7bfc30e2 |
| #define regBIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_STATUS 0x3fff7bfc30e3 |
| #define regBIFPLR3_2_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_MASK 0x3fff7bfc30e4 |
| #define regBIFPLR3_2_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_SEVERITY 0x3fff7bfc30e5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_SYSERROR 0x3fff7bfc30e6 |
| #define regBIFPLR3_2_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_EXCEPTION 0x3fff7bfc30e7 |
| #define regBIFPLR3_2_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_HDR_LOG0 0x3fff7bfc30e8 |
| #define regBIFPLR3_2_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_HDR_LOG1 0x3fff7bfc30e9 |
| #define regBIFPLR3_2_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_HDR_LOG2 0x3fff7bfc30ea |
| #define regBIFPLR3_2_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_HDR_LOG3 0x3fff7bfc30eb |
| #define regBIFPLR3_2_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0 0x3fff7bfc30ed |
| #define regBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1 0x3fff7bfc30ee |
| #define regBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2 0x3fff7bfc30ef |
| #define regBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3 0x3fff7bfc30f0 |
| #define regBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_LIST 0x3fff7bfc30f1 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ESM_HEADER_1 0x3fff7bfc30f2 |
| #define regBIFPLR3_2_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ESM_HEADER_2 0x3fff7bfc30f3 |
| #define regBIFPLR3_2_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ESM_STATUS 0x3fff7bfc30f3 |
| #define regBIFPLR3_2_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ESM_CTRL 0x3fff7bfc30f4 |
| #define regBIFPLR3_2_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_1 0x3fff7bfc30f5 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_2 0x3fff7bfc30f6 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_3 0x3fff7bfc30f7 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_4 0x3fff7bfc30f8 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_5 0x3fff7bfc30f9 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_6 0x3fff7bfc30fa |
| #define regBIFPLR3_2_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR3_2_PCIE_ESM_CAP_7 0x3fff7bfc30fb |
| #define regBIFPLR3_2_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR3_2_LINK_CAP_16GT 0x3fff7bfc3105 |
| #define regBIFPLR3_2_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR3_2_LINK_CNTL_16GT 0x3fff7bfc3106 |
| #define regBIFPLR3_2_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR3_2_LINK_STATUS_16GT 0x3fff7bfc3107 |
| #define regBIFPLR3_2_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR3_2_LINK_CAP_32GT 0x3fff7bfc3141 |
| #define regBIFPLR3_2_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR3_2_LINK_CNTL_32GT 0x3fff7bfc3142 |
| #define regBIFPLR3_2_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR3_2_LINK_STATUS_32GT 0x3fff7bfc3143 |
| #define regBIFPLR3_2_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie0_bifplr4_cfgdecp |
| // base address: 0xfffe0000d000 |
| #define regBIFPLR4_2_VENDOR_ID 0x3fff7bfc3400 |
| #define regBIFPLR4_2_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR4_2_DEVICE_ID 0x3fff7bfc3400 |
| #define regBIFPLR4_2_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR4_2_COMMAND 0x3fff7bfc3401 |
| #define regBIFPLR4_2_COMMAND_BASE_IDX 5 |
| #define regBIFPLR4_2_STATUS 0x3fff7bfc3401 |
| #define regBIFPLR4_2_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_REVISION_ID 0x3fff7bfc3402 |
| #define regBIFPLR4_2_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR4_2_PROG_INTERFACE 0x3fff7bfc3402 |
| #define regBIFPLR4_2_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR4_2_SUB_CLASS 0x3fff7bfc3402 |
| #define regBIFPLR4_2_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR4_2_BASE_CLASS 0x3fff7bfc3402 |
| #define regBIFPLR4_2_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR4_2_CACHE_LINE 0x3fff7bfc3403 |
| #define regBIFPLR4_2_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR4_2_LATENCY 0x3fff7bfc3403 |
| #define regBIFPLR4_2_LATENCY_BASE_IDX 5 |
| #define regBIFPLR4_2_HEADER 0x3fff7bfc3403 |
| #define regBIFPLR4_2_HEADER_BASE_IDX 5 |
| #define regBIFPLR4_2_BIST 0x3fff7bfc3403 |
| #define regBIFPLR4_2_BIST_BASE_IDX 5 |
| #define regBIFPLR4_2_SUB_BUS_NUMBER_LATENCY 0x3fff7bfc3406 |
| #define regBIFPLR4_2_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR4_2_IO_BASE_LIMIT 0x3fff7bfc3407 |
| #define regBIFPLR4_2_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR4_2_SECONDARY_STATUS 0x3fff7bfc3407 |
| #define regBIFPLR4_2_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_MEM_BASE_LIMIT 0x3fff7bfc3408 |
| #define regBIFPLR4_2_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR4_2_PREF_BASE_LIMIT 0x3fff7bfc3409 |
| #define regBIFPLR4_2_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR4_2_PREF_BASE_UPPER 0x3fff7bfc340a |
| #define regBIFPLR4_2_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR4_2_PREF_LIMIT_UPPER 0x3fff7bfc340b |
| #define regBIFPLR4_2_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR4_2_IO_BASE_LIMIT_HI 0x3fff7bfc340c |
| #define regBIFPLR4_2_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR4_2_CAP_PTR 0x3fff7bfc340d |
| #define regBIFPLR4_2_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR4_2_INTERRUPT_LINE 0x3fff7bfc340f |
| #define regBIFPLR4_2_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR4_2_INTERRUPT_PIN 0x3fff7bfc340f |
| #define regBIFPLR4_2_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR4_2_EXT_BRIDGE_CNTL 0x3fff7bfc3410 |
| #define regBIFPLR4_2_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PMI_CAP_LIST 0x3fff7bfc3414 |
| #define regBIFPLR4_2_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PMI_CAP 0x3fff7bfc3414 |
| #define regBIFPLR4_2_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_PMI_STATUS_CNTL 0x3fff7bfc3415 |
| #define regBIFPLR4_2_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_CAP_LIST 0x3fff7bfc3416 |
| #define regBIFPLR4_2_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_CAP 0x3fff7bfc3416 |
| #define regBIFPLR4_2_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_DEVICE_CAP 0x3fff7bfc3417 |
| #define regBIFPLR4_2_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_DEVICE_CNTL 0x3fff7bfc3418 |
| #define regBIFPLR4_2_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_DEVICE_STATUS 0x3fff7bfc3418 |
| #define regBIFPLR4_2_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_LINK_CAP 0x3fff7bfc3419 |
| #define regBIFPLR4_2_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_LINK_CNTL 0x3fff7bfc341a |
| #define regBIFPLR4_2_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_LINK_STATUS 0x3fff7bfc341a |
| #define regBIFPLR4_2_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_SLOT_CAP 0x3fff7bfc341b |
| #define regBIFPLR4_2_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_SLOT_CNTL 0x3fff7bfc341c |
| #define regBIFPLR4_2_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_SLOT_STATUS 0x3fff7bfc341c |
| #define regBIFPLR4_2_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_ROOT_CNTL 0x3fff7bfc341d |
| #define regBIFPLR4_2_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_ROOT_CAP 0x3fff7bfc341d |
| #define regBIFPLR4_2_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_ROOT_STATUS 0x3fff7bfc341e |
| #define regBIFPLR4_2_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_DEVICE_CAP2 0x3fff7bfc341f |
| #define regBIFPLR4_2_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR4_2_DEVICE_CNTL2 0x3fff7bfc3420 |
| #define regBIFPLR4_2_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_2_DEVICE_STATUS2 0x3fff7bfc3420 |
| #define regBIFPLR4_2_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR4_2_LINK_CAP2 0x3fff7bfc3421 |
| #define regBIFPLR4_2_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR4_2_LINK_CNTL2 0x3fff7bfc3422 |
| #define regBIFPLR4_2_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_2_LINK_STATUS2 0x3fff7bfc3422 |
| #define regBIFPLR4_2_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR4_2_SLOT_CAP2 0x3fff7bfc3423 |
| #define regBIFPLR4_2_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR4_2_SLOT_CNTL2 0x3fff7bfc3424 |
| #define regBIFPLR4_2_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_2_SLOT_STATUS2 0x3fff7bfc3424 |
| #define regBIFPLR4_2_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR4_2_MSI_CAP_LIST 0x3fff7bfc3428 |
| #define regBIFPLR4_2_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_MSI_MSG_CNTL 0x3fff7bfc3428 |
| #define regBIFPLR4_2_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_MSI_MSG_ADDR_LO 0x3fff7bfc3429 |
| #define regBIFPLR4_2_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR4_2_MSI_MSG_ADDR_HI 0x3fff7bfc342a |
| #define regBIFPLR4_2_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR4_2_MSI_MSG_DATA 0x3fff7bfc342a |
| #define regBIFPLR4_2_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR4_2_MSI_MSG_DATA_64 0x3fff7bfc342b |
| #define regBIFPLR4_2_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR4_2_SSID_CAP_LIST 0x3fff7bfc3430 |
| #define regBIFPLR4_2_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_SSID_CAP 0x3fff7bfc3431 |
| #define regBIFPLR4_2_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_MSI_MAP_CAP_LIST 0x3fff7bfc3432 |
| #define regBIFPLR4_2_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_MSI_MAP_CAP 0x3fff7bfc3432 |
| #define regBIFPLR4_2_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff7bfc3440 |
| #define regBIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR 0x3fff7bfc3441 |
| #define regBIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_VENDOR_SPECIFIC1 0x3fff7bfc3442 |
| #define regBIFPLR4_2_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_VENDOR_SPECIFIC2 0x3fff7bfc3443 |
| #define regBIFPLR4_2_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_VC_ENH_CAP_LIST 0x3fff7bfc3444 |
| #define regBIFPLR4_2_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_PORT_VC_CAP_REG1 0x3fff7bfc3445 |
| #define regBIFPLR4_2_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_PORT_VC_CAP_REG2 0x3fff7bfc3446 |
| #define regBIFPLR4_2_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_PORT_VC_CNTL 0x3fff7bfc3447 |
| #define regBIFPLR4_2_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_PORT_VC_STATUS 0x3fff7bfc3447 |
| #define regBIFPLR4_2_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_VC0_RESOURCE_CAP 0x3fff7bfc3448 |
| #define regBIFPLR4_2_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_VC0_RESOURCE_CNTL 0x3fff7bfc3449 |
| #define regBIFPLR4_2_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_VC0_RESOURCE_STATUS 0x3fff7bfc344a |
| #define regBIFPLR4_2_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_VC1_RESOURCE_CAP 0x3fff7bfc344b |
| #define regBIFPLR4_2_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_VC1_RESOURCE_CNTL 0x3fff7bfc344c |
| #define regBIFPLR4_2_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_VC1_RESOURCE_STATUS 0x3fff7bfc344d |
| #define regBIFPLR4_2_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3fff7bfc3450 |
| #define regBIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1 0x3fff7bfc3451 |
| #define regBIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2 0x3fff7bfc3452 |
| #define regBIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff7bfc3454 |
| #define regBIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_UNCORR_ERR_STATUS 0x3fff7bfc3455 |
| #define regBIFPLR4_2_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_UNCORR_ERR_MASK 0x3fff7bfc3456 |
| #define regBIFPLR4_2_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY 0x3fff7bfc3457 |
| #define regBIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_CORR_ERR_STATUS 0x3fff7bfc3458 |
| #define regBIFPLR4_2_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_CORR_ERR_MASK 0x3fff7bfc3459 |
| #define regBIFPLR4_2_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL 0x3fff7bfc345a |
| #define regBIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_HDR_LOG0 0x3fff7bfc345b |
| #define regBIFPLR4_2_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_HDR_LOG1 0x3fff7bfc345c |
| #define regBIFPLR4_2_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_HDR_LOG2 0x3fff7bfc345d |
| #define regBIFPLR4_2_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_HDR_LOG3 0x3fff7bfc345e |
| #define regBIFPLR4_2_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ROOT_ERR_CMD 0x3fff7bfc345f |
| #define regBIFPLR4_2_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ROOT_ERR_STATUS 0x3fff7bfc3460 |
| #define regBIFPLR4_2_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ERR_SRC_ID 0x3fff7bfc3461 |
| #define regBIFPLR4_2_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_TLP_PREFIX_LOG0 0x3fff7bfc3462 |
| #define regBIFPLR4_2_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_TLP_PREFIX_LOG1 0x3fff7bfc3463 |
| #define regBIFPLR4_2_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_TLP_PREFIX_LOG2 0x3fff7bfc3464 |
| #define regBIFPLR4_2_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_TLP_PREFIX_LOG3 0x3fff7bfc3465 |
| #define regBIFPLR4_2_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff7bfc349c |
| #define regBIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LINK_CNTL3 0x3fff7bfc349d |
| #define regBIFPLR4_2_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_ERROR_STATUS 0x3fff7bfc349e |
| #define regBIFPLR4_2_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff7bfc349f |
| #define regBIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff7bfc349f |
| #define regBIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff7bfc34a0 |
| #define regBIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff7bfc34a0 |
| #define regBIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff7bfc34a1 |
| #define regBIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff7bfc34a1 |
| #define regBIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff7bfc34a2 |
| #define regBIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff7bfc34a2 |
| #define regBIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff7bfc34a3 |
| #define regBIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff7bfc34a3 |
| #define regBIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff7bfc34a4 |
| #define regBIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff7bfc34a4 |
| #define regBIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff7bfc34a5 |
| #define regBIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff7bfc34a5 |
| #define regBIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff7bfc34a6 |
| #define regBIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff7bfc34a6 |
| #define regBIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ACS_ENH_CAP_LIST 0x3fff7bfc34a8 |
| #define regBIFPLR4_2_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ACS_CAP 0x3fff7bfc34a9 |
| #define regBIFPLR4_2_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ACS_CNTL 0x3fff7bfc34a9 |
| #define regBIFPLR4_2_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_ENH_CAP_LIST 0x3fff7bfc34bc |
| #define regBIFPLR4_2_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_CAP 0x3fff7bfc34bd |
| #define regBIFPLR4_2_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_CNTL 0x3fff7bfc34bd |
| #define regBIFPLR4_2_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_ADDR0 0x3fff7bfc34be |
| #define regBIFPLR4_2_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_ADDR1 0x3fff7bfc34bf |
| #define regBIFPLR4_2_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_RCV0 0x3fff7bfc34c0 |
| #define regBIFPLR4_2_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_RCV1 0x3fff7bfc34c1 |
| #define regBIFPLR4_2_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_BLOCK_ALL0 0x3fff7bfc34c2 |
| #define regBIFPLR4_2_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_BLOCK_ALL1 0x3fff7bfc34c3 |
| #define regBIFPLR4_2_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x3fff7bfc34c4 |
| #define regBIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x3fff7bfc34c5 |
| #define regBIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_OVERLAY_BAR0 0x3fff7bfc34c6 |
| #define regBIFPLR4_2_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_MC_OVERLAY_BAR1 0x3fff7bfc34c7 |
| #define regBIFPLR4_2_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST 0x3fff7bfc34dc |
| #define regBIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_L1_PM_SUB_CAP 0x3fff7bfc34dd |
| #define regBIFPLR4_2_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_L1_PM_SUB_CNTL 0x3fff7bfc34de |
| #define regBIFPLR4_2_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_L1_PM_SUB_CNTL2 0x3fff7bfc34df |
| #define regBIFPLR4_2_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_DPC_ENH_CAP_LIST 0x3fff7bfc34e0 |
| #define regBIFPLR4_2_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_DPC_CAP_LIST 0x3fff7bfc34e1 |
| #define regBIFPLR4_2_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_DPC_CNTL 0x3fff7bfc34e1 |
| #define regBIFPLR4_2_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_DPC_STATUS 0x3fff7bfc34e2 |
| #define regBIFPLR4_2_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID 0x3fff7bfc34e2 |
| #define regBIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_STATUS 0x3fff7bfc34e3 |
| #define regBIFPLR4_2_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_MASK 0x3fff7bfc34e4 |
| #define regBIFPLR4_2_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_SEVERITY 0x3fff7bfc34e5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_SYSERROR 0x3fff7bfc34e6 |
| #define regBIFPLR4_2_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_EXCEPTION 0x3fff7bfc34e7 |
| #define regBIFPLR4_2_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_HDR_LOG0 0x3fff7bfc34e8 |
| #define regBIFPLR4_2_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_HDR_LOG1 0x3fff7bfc34e9 |
| #define regBIFPLR4_2_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_HDR_LOG2 0x3fff7bfc34ea |
| #define regBIFPLR4_2_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_HDR_LOG3 0x3fff7bfc34eb |
| #define regBIFPLR4_2_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0 0x3fff7bfc34ed |
| #define regBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1 0x3fff7bfc34ee |
| #define regBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2 0x3fff7bfc34ef |
| #define regBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3 0x3fff7bfc34f0 |
| #define regBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_LIST 0x3fff7bfc34f1 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ESM_HEADER_1 0x3fff7bfc34f2 |
| #define regBIFPLR4_2_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ESM_HEADER_2 0x3fff7bfc34f3 |
| #define regBIFPLR4_2_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ESM_STATUS 0x3fff7bfc34f3 |
| #define regBIFPLR4_2_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ESM_CTRL 0x3fff7bfc34f4 |
| #define regBIFPLR4_2_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_1 0x3fff7bfc34f5 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_2 0x3fff7bfc34f6 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_3 0x3fff7bfc34f7 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_4 0x3fff7bfc34f8 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_5 0x3fff7bfc34f9 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_6 0x3fff7bfc34fa |
| #define regBIFPLR4_2_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR4_2_PCIE_ESM_CAP_7 0x3fff7bfc34fb |
| #define regBIFPLR4_2_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR4_2_LINK_CAP_16GT 0x3fff7bfc3505 |
| #define regBIFPLR4_2_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR4_2_LINK_CNTL_16GT 0x3fff7bfc3506 |
| #define regBIFPLR4_2_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR4_2_LINK_STATUS_16GT 0x3fff7bfc3507 |
| #define regBIFPLR4_2_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR4_2_LINK_CAP_32GT 0x3fff7bfc3541 |
| #define regBIFPLR4_2_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR4_2_LINK_CNTL_32GT 0x3fff7bfc3542 |
| #define regBIFPLR4_2_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR4_2_LINK_STATUS_32GT 0x3fff7bfc3543 |
| #define regBIFPLR4_2_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifplr0_cfgdecp |
| // base address: 0xfffe00011000 |
| #define regBIFPLR0_3_SUB_BUS_NUMBER_LATENCY 0x3fff7bfc4406 |
| #define regBIFPLR0_3_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR0_3_IO_BASE_LIMIT 0x3fff7bfc4407 |
| #define regBIFPLR0_3_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR0_3_SECONDARY_STATUS 0x3fff7bfc4407 |
| #define regBIFPLR0_3_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_3_MEM_BASE_LIMIT 0x3fff7bfc4408 |
| #define regBIFPLR0_3_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR0_3_PREF_BASE_LIMIT 0x3fff7bfc4409 |
| #define regBIFPLR0_3_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR0_3_PREF_BASE_UPPER 0x3fff7bfc440a |
| #define regBIFPLR0_3_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR0_3_PREF_LIMIT_UPPER 0x3fff7bfc440b |
| #define regBIFPLR0_3_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR0_3_IO_BASE_LIMIT_HI 0x3fff7bfc440c |
| #define regBIFPLR0_3_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR0_3_SLOT_CAP 0x3fff7bfc441b |
| #define regBIFPLR0_3_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR0_3_SLOT_CNTL 0x3fff7bfc441c |
| #define regBIFPLR0_3_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR0_3_SLOT_STATUS 0x3fff7bfc441c |
| #define regBIFPLR0_3_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR0_3_SLOT_CAP2 0x3fff7bfc4423 |
| #define regBIFPLR0_3_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR0_3_SLOT_CNTL2 0x3fff7bfc4424 |
| #define regBIFPLR0_3_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR0_3_SLOT_STATUS2 0x3fff7bfc4424 |
| #define regBIFPLR0_3_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR0_3_SSID_CAP_LIST 0x3fff7bfc4430 |
| #define regBIFPLR0_3_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR0_3_SSID_CAP 0x3fff7bfc4431 |
| #define regBIFPLR0_3_SSID_CAP_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifplr1_cfgdecp |
| // base address: 0xfffe00012000 |
| #define regBIFPLR1_3_SUB_BUS_NUMBER_LATENCY 0x3fff7bfc4806 |
| #define regBIFPLR1_3_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR1_3_IO_BASE_LIMIT 0x3fff7bfc4807 |
| #define regBIFPLR1_3_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR1_3_SECONDARY_STATUS 0x3fff7bfc4807 |
| #define regBIFPLR1_3_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_3_MEM_BASE_LIMIT 0x3fff7bfc4808 |
| #define regBIFPLR1_3_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR1_3_PREF_BASE_LIMIT 0x3fff7bfc4809 |
| #define regBIFPLR1_3_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR1_3_PREF_BASE_UPPER 0x3fff7bfc480a |
| #define regBIFPLR1_3_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR1_3_PREF_LIMIT_UPPER 0x3fff7bfc480b |
| #define regBIFPLR1_3_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR1_3_IO_BASE_LIMIT_HI 0x3fff7bfc480c |
| #define regBIFPLR1_3_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR1_3_SLOT_CAP 0x3fff7bfc481b |
| #define regBIFPLR1_3_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR1_3_SLOT_CNTL 0x3fff7bfc481c |
| #define regBIFPLR1_3_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR1_3_SLOT_STATUS 0x3fff7bfc481c |
| #define regBIFPLR1_3_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR1_3_SLOT_CAP2 0x3fff7bfc4823 |
| #define regBIFPLR1_3_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR1_3_SLOT_CNTL2 0x3fff7bfc4824 |
| #define regBIFPLR1_3_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR1_3_SLOT_STATUS2 0x3fff7bfc4824 |
| #define regBIFPLR1_3_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR1_3_SSID_CAP_LIST 0x3fff7bfc4830 |
| #define regBIFPLR1_3_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR1_3_SSID_CAP 0x3fff7bfc4831 |
| #define regBIFPLR1_3_SSID_CAP_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifplr2_cfgdecp |
| // base address: 0xfffe00013000 |
| #define regBIFPLR2_3_SUB_BUS_NUMBER_LATENCY 0x3fff7bfc4c06 |
| #define regBIFPLR2_3_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR2_3_IO_BASE_LIMIT 0x3fff7bfc4c07 |
| #define regBIFPLR2_3_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR2_3_SECONDARY_STATUS 0x3fff7bfc4c07 |
| #define regBIFPLR2_3_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_3_MEM_BASE_LIMIT 0x3fff7bfc4c08 |
| #define regBIFPLR2_3_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR2_3_PREF_BASE_LIMIT 0x3fff7bfc4c09 |
| #define regBIFPLR2_3_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR2_3_PREF_BASE_UPPER 0x3fff7bfc4c0a |
| #define regBIFPLR2_3_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR2_3_PREF_LIMIT_UPPER 0x3fff7bfc4c0b |
| #define regBIFPLR2_3_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR2_3_IO_BASE_LIMIT_HI 0x3fff7bfc4c0c |
| #define regBIFPLR2_3_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR2_3_SLOT_CAP 0x3fff7bfc4c1b |
| #define regBIFPLR2_3_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR2_3_SLOT_CNTL 0x3fff7bfc4c1c |
| #define regBIFPLR2_3_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR2_3_SLOT_STATUS 0x3fff7bfc4c1c |
| #define regBIFPLR2_3_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR2_3_SLOT_CAP2 0x3fff7bfc4c23 |
| #define regBIFPLR2_3_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR2_3_SLOT_CNTL2 0x3fff7bfc4c24 |
| #define regBIFPLR2_3_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR2_3_SLOT_STATUS2 0x3fff7bfc4c24 |
| #define regBIFPLR2_3_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR2_3_SSID_CAP_LIST 0x3fff7bfc4c30 |
| #define regBIFPLR2_3_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR2_3_SSID_CAP 0x3fff7bfc4c31 |
| #define regBIFPLR2_3_SSID_CAP_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifplr3_cfgdecp |
| // base address: 0xfffe00014000 |
| #define regBIFPLR3_3_SUB_BUS_NUMBER_LATENCY 0x3fff7bfc5006 |
| #define regBIFPLR3_3_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR3_3_IO_BASE_LIMIT 0x3fff7bfc5007 |
| #define regBIFPLR3_3_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR3_3_SECONDARY_STATUS 0x3fff7bfc5007 |
| #define regBIFPLR3_3_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_3_MEM_BASE_LIMIT 0x3fff7bfc5008 |
| #define regBIFPLR3_3_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR3_3_PREF_BASE_LIMIT 0x3fff7bfc5009 |
| #define regBIFPLR3_3_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR3_3_PREF_BASE_UPPER 0x3fff7bfc500a |
| #define regBIFPLR3_3_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR3_3_PREF_LIMIT_UPPER 0x3fff7bfc500b |
| #define regBIFPLR3_3_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR3_3_IO_BASE_LIMIT_HI 0x3fff7bfc500c |
| #define regBIFPLR3_3_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR3_3_SLOT_CAP 0x3fff7bfc501b |
| #define regBIFPLR3_3_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR3_3_SLOT_CNTL 0x3fff7bfc501c |
| #define regBIFPLR3_3_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR3_3_SLOT_STATUS 0x3fff7bfc501c |
| #define regBIFPLR3_3_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR3_3_SLOT_CAP2 0x3fff7bfc5023 |
| #define regBIFPLR3_3_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR3_3_SLOT_CNTL2 0x3fff7bfc5024 |
| #define regBIFPLR3_3_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR3_3_SLOT_STATUS2 0x3fff7bfc5024 |
| #define regBIFPLR3_3_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR3_3_SSID_CAP_LIST 0x3fff7bfc5030 |
| #define regBIFPLR3_3_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR3_3_SSID_CAP 0x3fff7bfc5031 |
| #define regBIFPLR3_3_SSID_CAP_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifplr4_cfgdecp |
| // base address: 0xfffe00015000 |
| #define regBIFPLR4_3_SUB_BUS_NUMBER_LATENCY 0x3fff7bfc5406 |
| #define regBIFPLR4_3_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR4_3_IO_BASE_LIMIT 0x3fff7bfc5407 |
| #define regBIFPLR4_3_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR4_3_SECONDARY_STATUS 0x3fff7bfc5407 |
| #define regBIFPLR4_3_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_3_MEM_BASE_LIMIT 0x3fff7bfc5408 |
| #define regBIFPLR4_3_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR4_3_PREF_BASE_LIMIT 0x3fff7bfc5409 |
| #define regBIFPLR4_3_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR4_3_PREF_BASE_UPPER 0x3fff7bfc540a |
| #define regBIFPLR4_3_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR4_3_PREF_LIMIT_UPPER 0x3fff7bfc540b |
| #define regBIFPLR4_3_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR4_3_IO_BASE_LIMIT_HI 0x3fff7bfc540c |
| #define regBIFPLR4_3_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR4_3_SLOT_CAP 0x3fff7bfc541b |
| #define regBIFPLR4_3_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR4_3_SLOT_CNTL 0x3fff7bfc541c |
| #define regBIFPLR4_3_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR4_3_SLOT_STATUS 0x3fff7bfc541c |
| #define regBIFPLR4_3_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR4_3_SLOT_CAP2 0x3fff7bfc5423 |
| #define regBIFPLR4_3_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR4_3_SLOT_CNTL2 0x3fff7bfc5424 |
| #define regBIFPLR4_3_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR4_3_SLOT_STATUS2 0x3fff7bfc5424 |
| #define regBIFPLR4_3_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR4_3_SSID_CAP_LIST 0x3fff7bfc5430 |
| #define regBIFPLR4_3_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR4_3_SSID_CAP 0x3fff7bfc5431 |
| #define regBIFPLR4_3_SSID_CAP_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_pcie1_bifplr5_cfgdecp |
| // base address: 0xfffe00016000 |
| #define regBIFPLR5_1_VENDOR_ID 0x3fff7bfc5800 |
| #define regBIFPLR5_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIFPLR5_1_DEVICE_ID 0x3fff7bfc5800 |
| #define regBIFPLR5_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIFPLR5_1_COMMAND 0x3fff7bfc5801 |
| #define regBIFPLR5_1_COMMAND_BASE_IDX 5 |
| #define regBIFPLR5_1_STATUS 0x3fff7bfc5801 |
| #define regBIFPLR5_1_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_REVISION_ID 0x3fff7bfc5802 |
| #define regBIFPLR5_1_REVISION_ID_BASE_IDX 5 |
| #define regBIFPLR5_1_PROG_INTERFACE 0x3fff7bfc5802 |
| #define regBIFPLR5_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIFPLR5_1_SUB_CLASS 0x3fff7bfc5802 |
| #define regBIFPLR5_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIFPLR5_1_BASE_CLASS 0x3fff7bfc5802 |
| #define regBIFPLR5_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIFPLR5_1_CACHE_LINE 0x3fff7bfc5803 |
| #define regBIFPLR5_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIFPLR5_1_LATENCY 0x3fff7bfc5803 |
| #define regBIFPLR5_1_LATENCY_BASE_IDX 5 |
| #define regBIFPLR5_1_HEADER 0x3fff7bfc5803 |
| #define regBIFPLR5_1_HEADER_BASE_IDX 5 |
| #define regBIFPLR5_1_BIST 0x3fff7bfc5803 |
| #define regBIFPLR5_1_BIST_BASE_IDX 5 |
| #define regBIFPLR5_1_SUB_BUS_NUMBER_LATENCY 0x3fff7bfc5806 |
| #define regBIFPLR5_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIFPLR5_1_IO_BASE_LIMIT 0x3fff7bfc5807 |
| #define regBIFPLR5_1_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR5_1_SECONDARY_STATUS 0x3fff7bfc5807 |
| #define regBIFPLR5_1_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_MEM_BASE_LIMIT 0x3fff7bfc5808 |
| #define regBIFPLR5_1_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR5_1_PREF_BASE_LIMIT 0x3fff7bfc5809 |
| #define regBIFPLR5_1_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIFPLR5_1_PREF_BASE_UPPER 0x3fff7bfc580a |
| #define regBIFPLR5_1_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIFPLR5_1_PREF_LIMIT_UPPER 0x3fff7bfc580b |
| #define regBIFPLR5_1_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIFPLR5_1_IO_BASE_LIMIT_HI 0x3fff7bfc580c |
| #define regBIFPLR5_1_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIFPLR5_1_CAP_PTR 0x3fff7bfc580d |
| #define regBIFPLR5_1_CAP_PTR_BASE_IDX 5 |
| #define regBIFPLR5_1_ROM_BASE_ADDR 0x3fff7bfc580e |
| #define regBIFPLR5_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIFPLR5_1_INTERRUPT_LINE 0x3fff7bfc580f |
| #define regBIFPLR5_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIFPLR5_1_INTERRUPT_PIN 0x3fff7bfc580f |
| #define regBIFPLR5_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIFPLR5_1_EXT_BRIDGE_CNTL 0x3fff7bfc5810 |
| #define regBIFPLR5_1_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_VENDOR_CAP_LIST 0x3fff7bfc5812 |
| #define regBIFPLR5_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_ADAPTER_ID_W 0x3fff7bfc5813 |
| #define regBIFPLR5_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIFPLR5_1_PMI_CAP_LIST 0x3fff7bfc5814 |
| #define regBIFPLR5_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PMI_CAP 0x3fff7bfc5814 |
| #define regBIFPLR5_1_PMI_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_PMI_STATUS_CNTL 0x3fff7bfc5815 |
| #define regBIFPLR5_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CAP_LIST 0x3fff7bfc5816 |
| #define regBIFPLR5_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CAP 0x3fff7bfc5816 |
| #define regBIFPLR5_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_DEVICE_CAP 0x3fff7bfc5817 |
| #define regBIFPLR5_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_DEVICE_CNTL 0x3fff7bfc5818 |
| #define regBIFPLR5_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_DEVICE_STATUS 0x3fff7bfc5818 |
| #define regBIFPLR5_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LINK_CAP 0x3fff7bfc5819 |
| #define regBIFPLR5_1_LINK_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_LINK_CNTL 0x3fff7bfc581a |
| #define regBIFPLR5_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LINK_STATUS 0x3fff7bfc581a |
| #define regBIFPLR5_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_SLOT_CAP 0x3fff7bfc581b |
| #define regBIFPLR5_1_SLOT_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_SLOT_CNTL 0x3fff7bfc581c |
| #define regBIFPLR5_1_SLOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_SLOT_STATUS 0x3fff7bfc581c |
| #define regBIFPLR5_1_SLOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_ROOT_CNTL 0x3fff7bfc581d |
| #define regBIFPLR5_1_ROOT_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_ROOT_CAP 0x3fff7bfc581d |
| #define regBIFPLR5_1_ROOT_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_ROOT_STATUS 0x3fff7bfc581e |
| #define regBIFPLR5_1_ROOT_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_DEVICE_CAP2 0x3fff7bfc581f |
| #define regBIFPLR5_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIFPLR5_1_DEVICE_CNTL2 0x3fff7bfc5820 |
| #define regBIFPLR5_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIFPLR5_1_DEVICE_STATUS2 0x3fff7bfc5820 |
| #define regBIFPLR5_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIFPLR5_1_LINK_CAP2 0x3fff7bfc5821 |
| #define regBIFPLR5_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIFPLR5_1_LINK_CNTL2 0x3fff7bfc5822 |
| #define regBIFPLR5_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIFPLR5_1_LINK_STATUS2 0x3fff7bfc5822 |
| #define regBIFPLR5_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIFPLR5_1_SLOT_CAP2 0x3fff7bfc5823 |
| #define regBIFPLR5_1_SLOT_CAP2_BASE_IDX 5 |
| #define regBIFPLR5_1_SLOT_CNTL2 0x3fff7bfc5824 |
| #define regBIFPLR5_1_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIFPLR5_1_SLOT_STATUS2 0x3fff7bfc5824 |
| #define regBIFPLR5_1_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIFPLR5_1_MSI_CAP_LIST 0x3fff7bfc5828 |
| #define regBIFPLR5_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_MSI_MSG_CNTL 0x3fff7bfc5828 |
| #define regBIFPLR5_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_MSI_MSG_ADDR_LO 0x3fff7bfc5829 |
| #define regBIFPLR5_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIFPLR5_1_MSI_MSG_ADDR_HI 0x3fff7bfc582a |
| #define regBIFPLR5_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIFPLR5_1_MSI_MSG_DATA 0x3fff7bfc582a |
| #define regBIFPLR5_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIFPLR5_1_MSI_MSG_DATA_64 0x3fff7bfc582b |
| #define regBIFPLR5_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIFPLR5_1_SSID_CAP_LIST 0x3fff7bfc5830 |
| #define regBIFPLR5_1_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_SSID_CAP 0x3fff7bfc5831 |
| #define regBIFPLR5_1_SSID_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_MSI_MAP_CAP_LIST 0x3fff7bfc5832 |
| #define regBIFPLR5_1_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_MSI_MAP_CAP 0x3fff7bfc5832 |
| #define regBIFPLR5_1_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff7bfc5840 |
| #define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff7bfc5841 |
| #define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC1 0x3fff7bfc5842 |
| #define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC2 0x3fff7bfc5843 |
| #define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_VC_ENH_CAP_LIST 0x3fff7bfc5844 |
| #define regBIFPLR5_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_PORT_VC_CAP_REG1 0x3fff7bfc5845 |
| #define regBIFPLR5_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_PORT_VC_CAP_REG2 0x3fff7bfc5846 |
| #define regBIFPLR5_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_PORT_VC_CNTL 0x3fff7bfc5847 |
| #define regBIFPLR5_1_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_PORT_VC_STATUS 0x3fff7bfc5847 |
| #define regBIFPLR5_1_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_VC0_RESOURCE_CAP 0x3fff7bfc5848 |
| #define regBIFPLR5_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_VC0_RESOURCE_CNTL 0x3fff7bfc5849 |
| #define regBIFPLR5_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_VC0_RESOURCE_STATUS 0x3fff7bfc584a |
| #define regBIFPLR5_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_VC1_RESOURCE_CAP 0x3fff7bfc584b |
| #define regBIFPLR5_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_VC1_RESOURCE_CNTL 0x3fff7bfc584c |
| #define regBIFPLR5_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_VC1_RESOURCE_STATUS 0x3fff7bfc584d |
| #define regBIFPLR5_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3fff7bfc5850 |
| #define regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1 0x3fff7bfc5851 |
| #define regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2 0x3fff7bfc5852 |
| #define regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff7bfc5854 |
| #define regBIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_UNCORR_ERR_STATUS 0x3fff7bfc5855 |
| #define regBIFPLR5_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_UNCORR_ERR_MASK 0x3fff7bfc5856 |
| #define regBIFPLR5_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff7bfc5857 |
| #define regBIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CORR_ERR_STATUS 0x3fff7bfc5858 |
| #define regBIFPLR5_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CORR_ERR_MASK 0x3fff7bfc5859 |
| #define regBIFPLR5_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff7bfc585a |
| #define regBIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_HDR_LOG0 0x3fff7bfc585b |
| #define regBIFPLR5_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_HDR_LOG1 0x3fff7bfc585c |
| #define regBIFPLR5_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_HDR_LOG2 0x3fff7bfc585d |
| #define regBIFPLR5_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_HDR_LOG3 0x3fff7bfc585e |
| #define regBIFPLR5_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ROOT_ERR_CMD 0x3fff7bfc585f |
| #define regBIFPLR5_1_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ROOT_ERR_STATUS 0x3fff7bfc5860 |
| #define regBIFPLR5_1_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ERR_SRC_ID 0x3fff7bfc5861 |
| #define regBIFPLR5_1_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG0 0x3fff7bfc5862 |
| #define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG1 0x3fff7bfc5863 |
| #define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG2 0x3fff7bfc5864 |
| #define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG3 0x3fff7bfc5865 |
| #define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff7bfc589c |
| #define regBIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LINK_CNTL3 0x3fff7bfc589d |
| #define regBIFPLR5_1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_ERROR_STATUS 0x3fff7bfc589e |
| #define regBIFPLR5_1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff7bfc589f |
| #define regBIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff7bfc589f |
| #define regBIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff7bfc58a0 |
| #define regBIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff7bfc58a0 |
| #define regBIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff7bfc58a1 |
| #define regBIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff7bfc58a1 |
| #define regBIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff7bfc58a2 |
| #define regBIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff7bfc58a2 |
| #define regBIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff7bfc58a3 |
| #define regBIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff7bfc58a3 |
| #define regBIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff7bfc58a4 |
| #define regBIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff7bfc58a4 |
| #define regBIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff7bfc58a5 |
| #define regBIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff7bfc58a5 |
| #define regBIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff7bfc58a6 |
| #define regBIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff7bfc58a6 |
| #define regBIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ACS_ENH_CAP_LIST 0x3fff7bfc58a8 |
| #define regBIFPLR5_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ACS_CAP 0x3fff7bfc58a9 |
| #define regBIFPLR5_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ACS_CNTL 0x3fff7bfc58a9 |
| #define regBIFPLR5_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_ENH_CAP_LIST 0x3fff7bfc58bc |
| #define regBIFPLR5_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_CAP 0x3fff7bfc58bd |
| #define regBIFPLR5_1_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_CNTL 0x3fff7bfc58bd |
| #define regBIFPLR5_1_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_ADDR0 0x3fff7bfc58be |
| #define regBIFPLR5_1_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_ADDR1 0x3fff7bfc58bf |
| #define regBIFPLR5_1_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_RCV0 0x3fff7bfc58c0 |
| #define regBIFPLR5_1_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_RCV1 0x3fff7bfc58c1 |
| #define regBIFPLR5_1_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_BLOCK_ALL0 0x3fff7bfc58c2 |
| #define regBIFPLR5_1_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_BLOCK_ALL1 0x3fff7bfc58c3 |
| #define regBIFPLR5_1_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x3fff7bfc58c4 |
| #define regBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x3fff7bfc58c5 |
| #define regBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_OVERLAY_BAR0 0x3fff7bfc58c6 |
| #define regBIFPLR5_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MC_OVERLAY_BAR1 0x3fff7bfc58c7 |
| #define regBIFPLR5_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST 0x3fff7bfc58dc |
| #define regBIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_L1_PM_SUB_CAP 0x3fff7bfc58dd |
| #define regBIFPLR5_1_PCIE_L1_PM_SUB_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_L1_PM_SUB_CNTL 0x3fff7bfc58de |
| #define regBIFPLR5_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_L1_PM_SUB_CNTL2 0x3fff7bfc58df |
| #define regBIFPLR5_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_DPC_ENH_CAP_LIST 0x3fff7bfc58e0 |
| #define regBIFPLR5_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_DPC_CAP_LIST 0x3fff7bfc58e1 |
| #define regBIFPLR5_1_PCIE_DPC_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_DPC_CNTL 0x3fff7bfc58e1 |
| #define regBIFPLR5_1_PCIE_DPC_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_DPC_STATUS 0x3fff7bfc58e2 |
| #define regBIFPLR5_1_PCIE_DPC_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID 0x3fff7bfc58e2 |
| #define regBIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_STATUS 0x3fff7bfc58e3 |
| #define regBIFPLR5_1_PCIE_RP_PIO_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_MASK 0x3fff7bfc58e4 |
| #define regBIFPLR5_1_PCIE_RP_PIO_MASK_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_SEVERITY 0x3fff7bfc58e5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_SEVERITY_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_SYSERROR 0x3fff7bfc58e6 |
| #define regBIFPLR5_1_PCIE_RP_PIO_SYSERROR_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_EXCEPTION 0x3fff7bfc58e7 |
| #define regBIFPLR5_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG0 0x3fff7bfc58e8 |
| #define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG1 0x3fff7bfc58e9 |
| #define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG2 0x3fff7bfc58ea |
| #define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG3 0x3fff7bfc58eb |
| #define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0 0x3fff7bfc58ed |
| #define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1 0x3fff7bfc58ee |
| #define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2 0x3fff7bfc58ef |
| #define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3 0x3fff7bfc58f0 |
| #define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_LIST 0x3fff7bfc58f1 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ESM_HEADER_1 0x3fff7bfc58f2 |
| #define regBIFPLR5_1_PCIE_ESM_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ESM_HEADER_2 0x3fff7bfc58f3 |
| #define regBIFPLR5_1_PCIE_ESM_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ESM_STATUS 0x3fff7bfc58f3 |
| #define regBIFPLR5_1_PCIE_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ESM_CTRL 0x3fff7bfc58f4 |
| #define regBIFPLR5_1_PCIE_ESM_CTRL_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_1 0x3fff7bfc58f5 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_2 0x3fff7bfc58f6 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_2_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_3 0x3fff7bfc58f7 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_3_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_4 0x3fff7bfc58f8 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_4_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_5 0x3fff7bfc58f9 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_5_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_6 0x3fff7bfc58fa |
| #define regBIFPLR5_1_PCIE_ESM_CAP_6_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_ESM_CAP_7 0x3fff7bfc58fb |
| #define regBIFPLR5_1_PCIE_ESM_CAP_7_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_DLF_ENH_CAP_LIST 0x3fff7bfc5900 |
| #define regBIFPLR5_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_DATA_LINK_FEATURE_CAP 0x3fff7bfc5901 |
| #define regBIFPLR5_1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_DATA_LINK_FEATURE_STATUS 0x3fff7bfc5902 |
| #define regBIFPLR5_1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x3fff7bfc5904 |
| #define regBIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_LINK_CAP_16GT 0x3fff7bfc5905 |
| #define regBIFPLR5_1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LINK_CNTL_16GT 0x3fff7bfc5906 |
| #define regBIFPLR5_1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LINK_STATUS_16GT 0x3fff7bfc5907 |
| #define regBIFPLR5_1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x3fff7bfc5908 |
| #define regBIFPLR5_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x3fff7bfc5909 |
| #define regBIFPLR5_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x3fff7bfc590a |
| #define regBIFPLR5_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT 0x3fff7bfc590c |
| #define regBIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT 0x3fff7bfc590c |
| #define regBIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT 0x3fff7bfc590c |
| #define regBIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT 0x3fff7bfc590c |
| #define regBIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT 0x3fff7bfc590d |
| #define regBIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT 0x3fff7bfc590d |
| #define regBIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT 0x3fff7bfc590d |
| #define regBIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT 0x3fff7bfc590d |
| #define regBIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT 0x3fff7bfc590e |
| #define regBIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT 0x3fff7bfc590e |
| #define regBIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT 0x3fff7bfc590e |
| #define regBIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT 0x3fff7bfc590e |
| #define regBIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT 0x3fff7bfc590f |
| #define regBIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT 0x3fff7bfc590f |
| #define regBIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT 0x3fff7bfc590f |
| #define regBIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT 0x3fff7bfc590f |
| #define regBIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST 0x3fff7bfc5910 |
| #define regBIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_MARGINING_PORT_CAP 0x3fff7bfc5911 |
| #define regBIFPLR5_1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_MARGINING_PORT_STATUS 0x3fff7bfc5911 |
| #define regBIFPLR5_1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_0_MARGINING_LANE_CNTL 0x3fff7bfc5912 |
| #define regBIFPLR5_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_0_MARGINING_LANE_STATUS 0x3fff7bfc5912 |
| #define regBIFPLR5_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_1_MARGINING_LANE_CNTL 0x3fff7bfc5913 |
| #define regBIFPLR5_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_1_MARGINING_LANE_STATUS 0x3fff7bfc5913 |
| #define regBIFPLR5_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_2_MARGINING_LANE_CNTL 0x3fff7bfc5914 |
| #define regBIFPLR5_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_2_MARGINING_LANE_STATUS 0x3fff7bfc5914 |
| #define regBIFPLR5_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_3_MARGINING_LANE_CNTL 0x3fff7bfc5915 |
| #define regBIFPLR5_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_3_MARGINING_LANE_STATUS 0x3fff7bfc5915 |
| #define regBIFPLR5_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_4_MARGINING_LANE_CNTL 0x3fff7bfc5916 |
| #define regBIFPLR5_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_4_MARGINING_LANE_STATUS 0x3fff7bfc5916 |
| #define regBIFPLR5_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_5_MARGINING_LANE_CNTL 0x3fff7bfc5917 |
| #define regBIFPLR5_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_5_MARGINING_LANE_STATUS 0x3fff7bfc5917 |
| #define regBIFPLR5_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_6_MARGINING_LANE_CNTL 0x3fff7bfc5918 |
| #define regBIFPLR5_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_6_MARGINING_LANE_STATUS 0x3fff7bfc5918 |
| #define regBIFPLR5_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_7_MARGINING_LANE_CNTL 0x3fff7bfc5919 |
| #define regBIFPLR5_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_7_MARGINING_LANE_STATUS 0x3fff7bfc5919 |
| #define regBIFPLR5_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_8_MARGINING_LANE_CNTL 0x3fff7bfc591a |
| #define regBIFPLR5_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_8_MARGINING_LANE_STATUS 0x3fff7bfc591a |
| #define regBIFPLR5_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_9_MARGINING_LANE_CNTL 0x3fff7bfc591b |
| #define regBIFPLR5_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_9_MARGINING_LANE_STATUS 0x3fff7bfc591b |
| #define regBIFPLR5_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_10_MARGINING_LANE_CNTL 0x3fff7bfc591c |
| #define regBIFPLR5_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_10_MARGINING_LANE_STATUS 0x3fff7bfc591c |
| #define regBIFPLR5_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_11_MARGINING_LANE_CNTL 0x3fff7bfc591d |
| #define regBIFPLR5_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_11_MARGINING_LANE_STATUS 0x3fff7bfc591d |
| #define regBIFPLR5_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_12_MARGINING_LANE_CNTL 0x3fff7bfc591e |
| #define regBIFPLR5_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_12_MARGINING_LANE_STATUS 0x3fff7bfc591e |
| #define regBIFPLR5_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_13_MARGINING_LANE_CNTL 0x3fff7bfc591f |
| #define regBIFPLR5_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_13_MARGINING_LANE_STATUS 0x3fff7bfc591f |
| #define regBIFPLR5_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_14_MARGINING_LANE_CNTL 0x3fff7bfc5920 |
| #define regBIFPLR5_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_14_MARGINING_LANE_STATUS 0x3fff7bfc5920 |
| #define regBIFPLR5_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_15_MARGINING_LANE_CNTL 0x3fff7bfc5921 |
| #define regBIFPLR5_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LANE_15_MARGINING_LANE_STATUS 0x3fff7bfc5921 |
| #define regBIFPLR5_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CCIX_CAP_LIST 0x3fff7bfc5922 |
| #define regBIFPLR5_1_PCIE_CCIX_CAP_LIST_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CCIX_HEADER_1 0x3fff7bfc5923 |
| #define regBIFPLR5_1_PCIE_CCIX_HEADER_1_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CCIX_HEADER_2 0x3fff7bfc5924 |
| #define regBIFPLR5_1_PCIE_CCIX_HEADER_2_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CCIX_CAP 0x3fff7bfc5924 |
| #define regBIFPLR5_1_PCIE_CCIX_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP 0x3fff7bfc5925 |
| #define regBIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CCIX_ESM_OPTL_CAP 0x3fff7bfc5926 |
| #define regBIFPLR5_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CCIX_ESM_STATUS 0x3fff7bfc5927 |
| #define regBIFPLR5_1_PCIE_CCIX_ESM_STATUS_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CCIX_ESM_CNTL 0x3fff7bfc5928 |
| #define regBIFPLR5_1_PCIE_CCIX_ESM_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x3fff7bfc5929 |
| #define regBIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x3fff7bfc5929 |
| #define regBIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x3fff7bfc5929 |
| #define regBIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x3fff7bfc5929 |
| #define regBIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x3fff7bfc592a |
| #define regBIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x3fff7bfc592a |
| #define regBIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x3fff7bfc592a |
| #define regBIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x3fff7bfc592a |
| #define regBIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x3fff7bfc592b |
| #define regBIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x3fff7bfc592b |
| #define regBIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x3fff7bfc592b |
| #define regBIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x3fff7bfc592b |
| #define regBIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x3fff7bfc592c |
| #define regBIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x3fff7bfc592c |
| #define regBIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x3fff7bfc592c |
| #define regBIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x3fff7bfc592c |
| #define regBIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x3fff7bfc592d |
| #define regBIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x3fff7bfc592d |
| #define regBIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x3fff7bfc592d |
| #define regBIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x3fff7bfc592d |
| #define regBIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x3fff7bfc592e |
| #define regBIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x3fff7bfc592e |
| #define regBIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x3fff7bfc592e |
| #define regBIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x3fff7bfc592e |
| #define regBIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x3fff7bfc592f |
| #define regBIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x3fff7bfc592f |
| #define regBIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x3fff7bfc592f |
| #define regBIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x3fff7bfc592f |
| #define regBIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x3fff7bfc5930 |
| #define regBIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x3fff7bfc5930 |
| #define regBIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x3fff7bfc5930 |
| #define regBIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x3fff7bfc5930 |
| #define regBIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CCIX_TRANS_CAP 0x3fff7bfc5931 |
| #define regBIFPLR5_1_PCIE_CCIX_TRANS_CAP_BASE_IDX 5 |
| #define regBIFPLR5_1_PCIE_CCIX_TRANS_CNTL 0x3fff7bfc5932 |
| #define regBIFPLR5_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX 5 |
| #define regBIFPLR5_1_LINK_CAP_32GT 0x3fff7bfc5941 |
| #define regBIFPLR5_1_LINK_CAP_32GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LINK_CNTL_32GT 0x3fff7bfc5942 |
| #define regBIFPLR5_1_LINK_CNTL_32GT_BASE_IDX 5 |
| #define regBIFPLR5_1_LINK_STATUS_32GT 0x3fff7bfc5943 |
| #define regBIFPLR5_1_LINK_STATUS_32GT_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp |
| // base address: 0xfffe00041000 |
| #define regBIF_CFG_DEV0_RC1_VENDOR_ID 0x3fff7bfd0400 |
| #define regBIF_CFG_DEV0_RC1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_ID 0x3fff7bfd0400 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_COMMAND 0x3fff7bfd0401 |
| #define regBIF_CFG_DEV0_RC1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_STATUS 0x3fff7bfd0401 |
| #define regBIF_CFG_DEV0_RC1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_REVISION_ID 0x3fff7bfd0402 |
| #define regBIF_CFG_DEV0_RC1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PROG_INTERFACE 0x3fff7bfd0402 |
| #define regBIF_CFG_DEV0_RC1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_SUB_CLASS 0x3fff7bfd0402 |
| #define regBIF_CFG_DEV0_RC1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_BASE_CLASS 0x3fff7bfd0402 |
| #define regBIF_CFG_DEV0_RC1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_CACHE_LINE 0x3fff7bfd0403 |
| #define regBIF_CFG_DEV0_RC1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LATENCY 0x3fff7bfd0403 |
| #define regBIF_CFG_DEV0_RC1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_HEADER 0x3fff7bfd0403 |
| #define regBIF_CFG_DEV0_RC1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_BIST 0x3fff7bfd0403 |
| #define regBIF_CFG_DEV0_RC1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_BASE_ADDR_1 0x3fff7bfd0404 |
| #define regBIF_CFG_DEV0_RC1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_BASE_ADDR_2 0x3fff7bfd0405 |
| #define regBIF_CFG_DEV0_RC1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY 0x3fff7bfd0406 |
| #define regBIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_IO_BASE_LIMIT 0x3fff7bfd0407 |
| #define regBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_SECONDARY_STATUS 0x3fff7bfd0407 |
| #define regBIF_CFG_DEV0_RC1_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MEM_BASE_LIMIT 0x3fff7bfd0408 |
| #define regBIF_CFG_DEV0_RC1_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PREF_BASE_LIMIT 0x3fff7bfd0409 |
| #define regBIF_CFG_DEV0_RC1_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PREF_BASE_UPPER 0x3fff7bfd040a |
| #define regBIF_CFG_DEV0_RC1_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER 0x3fff7bfd040b |
| #define regBIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI 0x3fff7bfd040c |
| #define regBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_CAP_PTR 0x3fff7bfd040d |
| #define regBIF_CFG_DEV0_RC1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_ROM_BASE_ADDR 0x3fff7bfd040e |
| #define regBIF_CFG_DEV0_RC1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_INTERRUPT_LINE 0x3fff7bfd040f |
| #define regBIF_CFG_DEV0_RC1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_INTERRUPT_PIN 0x3fff7bfd040f |
| #define regBIF_CFG_DEV0_RC1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL 0x3fff7bfd040f |
| #define regBIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL 0x3fff7bfd0410 |
| #define regBIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PMI_CAP_LIST 0x3fff7bfd0414 |
| #define regBIF_CFG_DEV0_RC1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PMI_CAP 0x3fff7bfd0414 |
| #define regBIF_CFG_DEV0_RC1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PMI_STATUS_CNTL 0x3fff7bfd0415 |
| #define regBIF_CFG_DEV0_RC1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_CAP_LIST 0x3fff7bfd0416 |
| #define regBIF_CFG_DEV0_RC1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_CAP 0x3fff7bfd0416 |
| #define regBIF_CFG_DEV0_RC1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_CAP 0x3fff7bfd0417 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_CNTL 0x3fff7bfd0418 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_STATUS 0x3fff7bfd0418 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LINK_CAP 0x3fff7bfd0419 |
| #define regBIF_CFG_DEV0_RC1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LINK_CNTL 0x3fff7bfd041a |
| #define regBIF_CFG_DEV0_RC1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LINK_STATUS 0x3fff7bfd041a |
| #define regBIF_CFG_DEV0_RC1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_SLOT_CAP 0x3fff7bfd041b |
| #define regBIF_CFG_DEV0_RC1_SLOT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_SLOT_CNTL 0x3fff7bfd041c |
| #define regBIF_CFG_DEV0_RC1_SLOT_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_SLOT_STATUS 0x3fff7bfd041c |
| #define regBIF_CFG_DEV0_RC1_SLOT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_ROOT_CNTL 0x3fff7bfd041d |
| #define regBIF_CFG_DEV0_RC1_ROOT_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_ROOT_CAP 0x3fff7bfd041d |
| #define regBIF_CFG_DEV0_RC1_ROOT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_ROOT_STATUS 0x3fff7bfd041e |
| #define regBIF_CFG_DEV0_RC1_ROOT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_CAP2 0x3fff7bfd041f |
| #define regBIF_CFG_DEV0_RC1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_CNTL2 0x3fff7bfd0420 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_STATUS2 0x3fff7bfd0420 |
| #define regBIF_CFG_DEV0_RC1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LINK_CAP2 0x3fff7bfd0421 |
| #define regBIF_CFG_DEV0_RC1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LINK_CNTL2 0x3fff7bfd0422 |
| #define regBIF_CFG_DEV0_RC1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LINK_STATUS2 0x3fff7bfd0422 |
| #define regBIF_CFG_DEV0_RC1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_SLOT_CAP2 0x3fff7bfd0423 |
| #define regBIF_CFG_DEV0_RC1_SLOT_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_SLOT_CNTL2 0x3fff7bfd0424 |
| #define regBIF_CFG_DEV0_RC1_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_SLOT_STATUS2 0x3fff7bfd0424 |
| #define regBIF_CFG_DEV0_RC1_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MSI_CAP_LIST 0x3fff7bfd0428 |
| #define regBIF_CFG_DEV0_RC1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MSI_MSG_CNTL 0x3fff7bfd0428 |
| #define regBIF_CFG_DEV0_RC1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO 0x3fff7bfd0429 |
| #define regBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI 0x3fff7bfd042a |
| #define regBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MSI_MSG_DATA 0x3fff7bfd042a |
| #define regBIF_CFG_DEV0_RC1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA 0x3fff7bfd042a |
| #define regBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MSI_MSG_DATA_64 0x3fff7bfd042b |
| #define regBIF_CFG_DEV0_RC1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64 0x3fff7bfd042b |
| #define regBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_SSID_CAP_LIST 0x3fff7bfd0430 |
| #define regBIF_CFG_DEV0_RC1_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_SSID_CAP 0x3fff7bfd0431 |
| #define regBIF_CFG_DEV0_RC1_SSID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST 0x3fff7bfd0432 |
| #define regBIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MSI_MAP_CAP 0x3fff7bfd0432 |
| #define regBIF_CFG_DEV0_RC1_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff7bfd0440 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff7bfd0441 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1 0x3fff7bfd0442 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2 0x3fff7bfd0443 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST 0x3fff7bfd0444 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1 0x3fff7bfd0445 |
| #define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2 0x3fff7bfd0446 |
| #define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL 0x3fff7bfd0447 |
| #define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS 0x3fff7bfd0447 |
| #define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP 0x3fff7bfd0448 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL 0x3fff7bfd0449 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS 0x3fff7bfd044a |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP 0x3fff7bfd044b |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL 0x3fff7bfd044c |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS 0x3fff7bfd044d |
| #define regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3fff7bfd0450 |
| #define regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1 0x3fff7bfd0451 |
| #define regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2 0x3fff7bfd0452 |
| #define regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff7bfd0454 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS 0x3fff7bfd0455 |
| #define regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK 0x3fff7bfd0456 |
| #define regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY 0x3fff7bfd0457 |
| #define regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS 0x3fff7bfd0458 |
| #define regBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK 0x3fff7bfd0459 |
| #define regBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL 0x3fff7bfd045a |
| #define regBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG0 0x3fff7bfd045b |
| #define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG1 0x3fff7bfd045c |
| #define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG2 0x3fff7bfd045d |
| #define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG3 0x3fff7bfd045e |
| #define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD 0x3fff7bfd045f |
| #define regBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS 0x3fff7bfd0460 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID 0x3fff7bfd0461 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0 0x3fff7bfd0462 |
| #define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1 0x3fff7bfd0463 |
| #define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2 0x3fff7bfd0464 |
| #define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3 0x3fff7bfd0465 |
| #define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff7bfd049c |
| #define regBIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3 0x3fff7bfd049d |
| #define regBIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS 0x3fff7bfd049e |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff7bfd049f |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff7bfd049f |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff7bfd04a0 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff7bfd04a0 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff7bfd04a1 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff7bfd04a1 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff7bfd04a2 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff7bfd04a2 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff7bfd04a3 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff7bfd04a3 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff7bfd04a4 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff7bfd04a4 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff7bfd04a5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff7bfd04a5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff7bfd04a6 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff7bfd04a6 |
| #define regBIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST 0x3fff7bfd04a8 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ACS_CAP 0x3fff7bfd04a9 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ACS_CNTL 0x3fff7bfd04a9 |
| #define regBIF_CFG_DEV0_RC1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST 0x3fff7bfd0500 |
| #define regBIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP 0x3fff7bfd0501 |
| #define regBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS 0x3fff7bfd0502 |
| #define regBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST 0x3fff7bfd0504 |
| #define regBIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LINK_CAP_16GT 0x3fff7bfd0505 |
| #define regBIF_CFG_DEV0_RC1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LINK_CNTL_16GT 0x3fff7bfd0506 |
| #define regBIF_CFG_DEV0_RC1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LINK_STATUS_16GT 0x3fff7bfd0507 |
| #define regBIF_CFG_DEV0_RC1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x3fff7bfd0508 |
| #define regBIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x3fff7bfd0509 |
| #define regBIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x3fff7bfd050a |
| #define regBIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT 0x3fff7bfd050c |
| #define regBIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT 0x3fff7bfd050c |
| #define regBIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT 0x3fff7bfd050c |
| #define regBIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT 0x3fff7bfd050c |
| #define regBIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT 0x3fff7bfd050d |
| #define regBIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT 0x3fff7bfd050d |
| #define regBIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT 0x3fff7bfd050d |
| #define regBIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT 0x3fff7bfd050d |
| #define regBIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT 0x3fff7bfd050e |
| #define regBIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT 0x3fff7bfd050e |
| #define regBIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT 0x3fff7bfd050e |
| #define regBIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT 0x3fff7bfd050e |
| #define regBIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT 0x3fff7bfd050f |
| #define regBIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT 0x3fff7bfd050f |
| #define regBIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT 0x3fff7bfd050f |
| #define regBIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT 0x3fff7bfd050f |
| #define regBIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST 0x3fff7bfd0514 |
| #define regBIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MARGINING_PORT_CAP 0x3fff7bfd0515 |
| #define regBIF_CFG_DEV0_RC1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS 0x3fff7bfd0515 |
| #define regBIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL 0x3fff7bfd0516 |
| #define regBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS 0x3fff7bfd0516 |
| #define regBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL 0x3fff7bfd0517 |
| #define regBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS 0x3fff7bfd0517 |
| #define regBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL 0x3fff7bfd0518 |
| #define regBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS 0x3fff7bfd0518 |
| #define regBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL 0x3fff7bfd0519 |
| #define regBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS 0x3fff7bfd0519 |
| #define regBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL 0x3fff7bfd051a |
| #define regBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS 0x3fff7bfd051a |
| #define regBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL 0x3fff7bfd051b |
| #define regBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS 0x3fff7bfd051b |
| #define regBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL 0x3fff7bfd051c |
| #define regBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS 0x3fff7bfd051c |
| #define regBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL 0x3fff7bfd051d |
| #define regBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS 0x3fff7bfd051d |
| #define regBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL 0x3fff7bfd051e |
| #define regBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS 0x3fff7bfd051e |
| #define regBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL 0x3fff7bfd051f |
| #define regBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS 0x3fff7bfd051f |
| #define regBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL 0x3fff7bfd0520 |
| #define regBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS 0x3fff7bfd0520 |
| #define regBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL 0x3fff7bfd0521 |
| #define regBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS 0x3fff7bfd0521 |
| #define regBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL 0x3fff7bfd0522 |
| #define regBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS 0x3fff7bfd0522 |
| #define regBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL 0x3fff7bfd0523 |
| #define regBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS 0x3fff7bfd0523 |
| #define regBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL 0x3fff7bfd0524 |
| #define regBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS 0x3fff7bfd0524 |
| #define regBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL 0x3fff7bfd0525 |
| #define regBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS 0x3fff7bfd0525 |
| #define regBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp |
| // base address: 0xfffe00042000 |
| #define regBIF_CFG_DEV1_RC1_VENDOR_ID 0x3fff7bfd0800 |
| #define regBIF_CFG_DEV1_RC1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_ID 0x3fff7bfd0800 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_COMMAND 0x3fff7bfd0801 |
| #define regBIF_CFG_DEV1_RC1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_STATUS 0x3fff7bfd0801 |
| #define regBIF_CFG_DEV1_RC1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_REVISION_ID 0x3fff7bfd0802 |
| #define regBIF_CFG_DEV1_RC1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PROG_INTERFACE 0x3fff7bfd0802 |
| #define regBIF_CFG_DEV1_RC1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_SUB_CLASS 0x3fff7bfd0802 |
| #define regBIF_CFG_DEV1_RC1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_BASE_CLASS 0x3fff7bfd0802 |
| #define regBIF_CFG_DEV1_RC1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_CACHE_LINE 0x3fff7bfd0803 |
| #define regBIF_CFG_DEV1_RC1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LATENCY 0x3fff7bfd0803 |
| #define regBIF_CFG_DEV1_RC1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_HEADER 0x3fff7bfd0803 |
| #define regBIF_CFG_DEV1_RC1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_BIST 0x3fff7bfd0803 |
| #define regBIF_CFG_DEV1_RC1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_BASE_ADDR_1 0x3fff7bfd0804 |
| #define regBIF_CFG_DEV1_RC1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_BASE_ADDR_2 0x3fff7bfd0805 |
| #define regBIF_CFG_DEV1_RC1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY 0x3fff7bfd0806 |
| #define regBIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_IO_BASE_LIMIT 0x3fff7bfd0807 |
| #define regBIF_CFG_DEV1_RC1_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_SECONDARY_STATUS 0x3fff7bfd0807 |
| #define regBIF_CFG_DEV1_RC1_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MEM_BASE_LIMIT 0x3fff7bfd0808 |
| #define regBIF_CFG_DEV1_RC1_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PREF_BASE_LIMIT 0x3fff7bfd0809 |
| #define regBIF_CFG_DEV1_RC1_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PREF_BASE_UPPER 0x3fff7bfd080a |
| #define regBIF_CFG_DEV1_RC1_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER 0x3fff7bfd080b |
| #define regBIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI 0x3fff7bfd080c |
| #define regBIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_CAP_PTR 0x3fff7bfd080d |
| #define regBIF_CFG_DEV1_RC1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_ROM_BASE_ADDR 0x3fff7bfd080e |
| #define regBIF_CFG_DEV1_RC1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_INTERRUPT_LINE 0x3fff7bfd080f |
| #define regBIF_CFG_DEV1_RC1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_INTERRUPT_PIN 0x3fff7bfd080f |
| #define regBIF_CFG_DEV1_RC1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL 0x3fff7bfd080f |
| #define regBIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL 0x3fff7bfd0810 |
| #define regBIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PMI_CAP_LIST 0x3fff7bfd0814 |
| #define regBIF_CFG_DEV1_RC1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PMI_CAP 0x3fff7bfd0814 |
| #define regBIF_CFG_DEV1_RC1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PMI_STATUS_CNTL 0x3fff7bfd0815 |
| #define regBIF_CFG_DEV1_RC1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_CAP_LIST 0x3fff7bfd0816 |
| #define regBIF_CFG_DEV1_RC1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_CAP 0x3fff7bfd0816 |
| #define regBIF_CFG_DEV1_RC1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_CAP 0x3fff7bfd0817 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_CNTL 0x3fff7bfd0818 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_STATUS 0x3fff7bfd0818 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LINK_CAP 0x3fff7bfd0819 |
| #define regBIF_CFG_DEV1_RC1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LINK_CNTL 0x3fff7bfd081a |
| #define regBIF_CFG_DEV1_RC1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LINK_STATUS 0x3fff7bfd081a |
| #define regBIF_CFG_DEV1_RC1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_SLOT_CAP 0x3fff7bfd081b |
| #define regBIF_CFG_DEV1_RC1_SLOT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_SLOT_CNTL 0x3fff7bfd081c |
| #define regBIF_CFG_DEV1_RC1_SLOT_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_SLOT_STATUS 0x3fff7bfd081c |
| #define regBIF_CFG_DEV1_RC1_SLOT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_ROOT_CNTL 0x3fff7bfd081d |
| #define regBIF_CFG_DEV1_RC1_ROOT_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_ROOT_CAP 0x3fff7bfd081d |
| #define regBIF_CFG_DEV1_RC1_ROOT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_ROOT_STATUS 0x3fff7bfd081e |
| #define regBIF_CFG_DEV1_RC1_ROOT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_CAP2 0x3fff7bfd081f |
| #define regBIF_CFG_DEV1_RC1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_CNTL2 0x3fff7bfd0820 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_STATUS2 0x3fff7bfd0820 |
| #define regBIF_CFG_DEV1_RC1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LINK_CAP2 0x3fff7bfd0821 |
| #define regBIF_CFG_DEV1_RC1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LINK_CNTL2 0x3fff7bfd0822 |
| #define regBIF_CFG_DEV1_RC1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LINK_STATUS2 0x3fff7bfd0822 |
| #define regBIF_CFG_DEV1_RC1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_SLOT_CAP2 0x3fff7bfd0823 |
| #define regBIF_CFG_DEV1_RC1_SLOT_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_SLOT_CNTL2 0x3fff7bfd0824 |
| #define regBIF_CFG_DEV1_RC1_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_SLOT_STATUS2 0x3fff7bfd0824 |
| #define regBIF_CFG_DEV1_RC1_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MSI_CAP_LIST 0x3fff7bfd0828 |
| #define regBIF_CFG_DEV1_RC1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MSI_MSG_CNTL 0x3fff7bfd0828 |
| #define regBIF_CFG_DEV1_RC1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO 0x3fff7bfd0829 |
| #define regBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI 0x3fff7bfd082a |
| #define regBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MSI_MSG_DATA 0x3fff7bfd082a |
| #define regBIF_CFG_DEV1_RC1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA 0x3fff7bfd082a |
| #define regBIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MSI_MSG_DATA_64 0x3fff7bfd082b |
| #define regBIF_CFG_DEV1_RC1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_64 0x3fff7bfd082b |
| #define regBIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_SSID_CAP_LIST 0x3fff7bfd0830 |
| #define regBIF_CFG_DEV1_RC1_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_SSID_CAP 0x3fff7bfd0831 |
| #define regBIF_CFG_DEV1_RC1_SSID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST 0x3fff7bfd0832 |
| #define regBIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MSI_MAP_CAP 0x3fff7bfd0832 |
| #define regBIF_CFG_DEV1_RC1_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff7bfd0840 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff7bfd0841 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1 0x3fff7bfd0842 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2 0x3fff7bfd0843 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST 0x3fff7bfd0844 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1 0x3fff7bfd0845 |
| #define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2 0x3fff7bfd0846 |
| #define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL 0x3fff7bfd0847 |
| #define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS 0x3fff7bfd0847 |
| #define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP 0x3fff7bfd0848 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL 0x3fff7bfd0849 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS 0x3fff7bfd084a |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP 0x3fff7bfd084b |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL 0x3fff7bfd084c |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS 0x3fff7bfd084d |
| #define regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3fff7bfd0850 |
| #define regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1 0x3fff7bfd0851 |
| #define regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2 0x3fff7bfd0852 |
| #define regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff7bfd0854 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS 0x3fff7bfd0855 |
| #define regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK 0x3fff7bfd0856 |
| #define regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY 0x3fff7bfd0857 |
| #define regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS 0x3fff7bfd0858 |
| #define regBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK 0x3fff7bfd0859 |
| #define regBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL 0x3fff7bfd085a |
| #define regBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG0 0x3fff7bfd085b |
| #define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG1 0x3fff7bfd085c |
| #define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG2 0x3fff7bfd085d |
| #define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG3 0x3fff7bfd085e |
| #define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD 0x3fff7bfd085f |
| #define regBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS 0x3fff7bfd0860 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID 0x3fff7bfd0861 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0 0x3fff7bfd0862 |
| #define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1 0x3fff7bfd0863 |
| #define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2 0x3fff7bfd0864 |
| #define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3 0x3fff7bfd0865 |
| #define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff7bfd089c |
| #define regBIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3 0x3fff7bfd089d |
| #define regBIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS 0x3fff7bfd089e |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff7bfd089f |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff7bfd089f |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff7bfd08a0 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff7bfd08a0 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff7bfd08a1 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff7bfd08a1 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff7bfd08a2 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff7bfd08a2 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff7bfd08a3 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff7bfd08a3 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff7bfd08a4 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff7bfd08a4 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff7bfd08a5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff7bfd08a5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff7bfd08a6 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff7bfd08a6 |
| #define regBIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST 0x3fff7bfd08a8 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ACS_CAP 0x3fff7bfd08a9 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ACS_CNTL 0x3fff7bfd08a9 |
| #define regBIF_CFG_DEV1_RC1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST 0x3fff7bfd0900 |
| #define regBIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP 0x3fff7bfd0901 |
| #define regBIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS 0x3fff7bfd0902 |
| #define regBIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST 0x3fff7bfd0904 |
| #define regBIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LINK_CAP_16GT 0x3fff7bfd0905 |
| #define regBIF_CFG_DEV1_RC1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LINK_CNTL_16GT 0x3fff7bfd0906 |
| #define regBIF_CFG_DEV1_RC1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LINK_STATUS_16GT 0x3fff7bfd0907 |
| #define regBIF_CFG_DEV1_RC1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x3fff7bfd0908 |
| #define regBIF_CFG_DEV1_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x3fff7bfd0909 |
| #define regBIF_CFG_DEV1_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x3fff7bfd090a |
| #define regBIF_CFG_DEV1_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT 0x3fff7bfd090c |
| #define regBIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT 0x3fff7bfd090c |
| #define regBIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT 0x3fff7bfd090c |
| #define regBIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT 0x3fff7bfd090c |
| #define regBIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT 0x3fff7bfd090d |
| #define regBIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT 0x3fff7bfd090d |
| #define regBIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT 0x3fff7bfd090d |
| #define regBIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT 0x3fff7bfd090d |
| #define regBIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT 0x3fff7bfd090e |
| #define regBIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT 0x3fff7bfd090e |
| #define regBIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT 0x3fff7bfd090e |
| #define regBIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT 0x3fff7bfd090e |
| #define regBIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT 0x3fff7bfd090f |
| #define regBIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT 0x3fff7bfd090f |
| #define regBIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT 0x3fff7bfd090f |
| #define regBIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT 0x3fff7bfd090f |
| #define regBIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST 0x3fff7bfd0914 |
| #define regBIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MARGINING_PORT_CAP 0x3fff7bfd0915 |
| #define regBIF_CFG_DEV1_RC1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS 0x3fff7bfd0915 |
| #define regBIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL 0x3fff7bfd0916 |
| #define regBIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS 0x3fff7bfd0916 |
| #define regBIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL 0x3fff7bfd0917 |
| #define regBIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS 0x3fff7bfd0917 |
| #define regBIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL 0x3fff7bfd0918 |
| #define regBIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS 0x3fff7bfd0918 |
| #define regBIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL 0x3fff7bfd0919 |
| #define regBIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS 0x3fff7bfd0919 |
| #define regBIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL 0x3fff7bfd091a |
| #define regBIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS 0x3fff7bfd091a |
| #define regBIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL 0x3fff7bfd091b |
| #define regBIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS 0x3fff7bfd091b |
| #define regBIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL 0x3fff7bfd091c |
| #define regBIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS 0x3fff7bfd091c |
| #define regBIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL 0x3fff7bfd091d |
| #define regBIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS 0x3fff7bfd091d |
| #define regBIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL 0x3fff7bfd091e |
| #define regBIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS 0x3fff7bfd091e |
| #define regBIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL 0x3fff7bfd091f |
| #define regBIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS 0x3fff7bfd091f |
| #define regBIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL 0x3fff7bfd0920 |
| #define regBIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS 0x3fff7bfd0920 |
| #define regBIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL 0x3fff7bfd0921 |
| #define regBIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS 0x3fff7bfd0921 |
| #define regBIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL 0x3fff7bfd0922 |
| #define regBIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS 0x3fff7bfd0922 |
| #define regBIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL 0x3fff7bfd0923 |
| #define regBIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS 0x3fff7bfd0923 |
| #define regBIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL 0x3fff7bfd0924 |
| #define regBIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS 0x3fff7bfd0924 |
| #define regBIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL 0x3fff7bfd0925 |
| #define regBIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS 0x3fff7bfd0925 |
| #define regBIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp |
| // base address: 0xfffe00043000 |
| #define regBIF_CFG_DEV2_RC1_VENDOR_ID 0x3fff7bfd0c00 |
| #define regBIF_CFG_DEV2_RC1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_ID 0x3fff7bfd0c00 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_COMMAND 0x3fff7bfd0c01 |
| #define regBIF_CFG_DEV2_RC1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_STATUS 0x3fff7bfd0c01 |
| #define regBIF_CFG_DEV2_RC1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_REVISION_ID 0x3fff7bfd0c02 |
| #define regBIF_CFG_DEV2_RC1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PROG_INTERFACE 0x3fff7bfd0c02 |
| #define regBIF_CFG_DEV2_RC1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_SUB_CLASS 0x3fff7bfd0c02 |
| #define regBIF_CFG_DEV2_RC1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_BASE_CLASS 0x3fff7bfd0c02 |
| #define regBIF_CFG_DEV2_RC1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_CACHE_LINE 0x3fff7bfd0c03 |
| #define regBIF_CFG_DEV2_RC1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LATENCY 0x3fff7bfd0c03 |
| #define regBIF_CFG_DEV2_RC1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_HEADER 0x3fff7bfd0c03 |
| #define regBIF_CFG_DEV2_RC1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_BIST 0x3fff7bfd0c03 |
| #define regBIF_CFG_DEV2_RC1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_BASE_ADDR_1 0x3fff7bfd0c04 |
| #define regBIF_CFG_DEV2_RC1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_BASE_ADDR_2 0x3fff7bfd0c05 |
| #define regBIF_CFG_DEV2_RC1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY 0x3fff7bfd0c06 |
| #define regBIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_IO_BASE_LIMIT 0x3fff7bfd0c07 |
| #define regBIF_CFG_DEV2_RC1_IO_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_SECONDARY_STATUS 0x3fff7bfd0c07 |
| #define regBIF_CFG_DEV2_RC1_SECONDARY_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MEM_BASE_LIMIT 0x3fff7bfd0c08 |
| #define regBIF_CFG_DEV2_RC1_MEM_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PREF_BASE_LIMIT 0x3fff7bfd0c09 |
| #define regBIF_CFG_DEV2_RC1_PREF_BASE_LIMIT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PREF_BASE_UPPER 0x3fff7bfd0c0a |
| #define regBIF_CFG_DEV2_RC1_PREF_BASE_UPPER_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PREF_LIMIT_UPPER 0x3fff7bfd0c0b |
| #define regBIF_CFG_DEV2_RC1_PREF_LIMIT_UPPER_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI 0x3fff7bfd0c0c |
| #define regBIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_CAP_PTR 0x3fff7bfd0c0d |
| #define regBIF_CFG_DEV2_RC1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_ROM_BASE_ADDR 0x3fff7bfd0c0e |
| #define regBIF_CFG_DEV2_RC1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_INTERRUPT_LINE 0x3fff7bfd0c0f |
| #define regBIF_CFG_DEV2_RC1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_INTERRUPT_PIN 0x3fff7bfd0c0f |
| #define regBIF_CFG_DEV2_RC1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL 0x3fff7bfd0c0f |
| #define regBIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_EXT_BRIDGE_CNTL 0x3fff7bfd0c10 |
| #define regBIF_CFG_DEV2_RC1_EXT_BRIDGE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PMI_CAP_LIST 0x3fff7bfd0c14 |
| #define regBIF_CFG_DEV2_RC1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PMI_CAP 0x3fff7bfd0c14 |
| #define regBIF_CFG_DEV2_RC1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PMI_STATUS_CNTL 0x3fff7bfd0c15 |
| #define regBIF_CFG_DEV2_RC1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_CAP_LIST 0x3fff7bfd0c16 |
| #define regBIF_CFG_DEV2_RC1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_CAP 0x3fff7bfd0c16 |
| #define regBIF_CFG_DEV2_RC1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_CAP 0x3fff7bfd0c17 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_CNTL 0x3fff7bfd0c18 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_STATUS 0x3fff7bfd0c18 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LINK_CAP 0x3fff7bfd0c19 |
| #define regBIF_CFG_DEV2_RC1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LINK_CNTL 0x3fff7bfd0c1a |
| #define regBIF_CFG_DEV2_RC1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LINK_STATUS 0x3fff7bfd0c1a |
| #define regBIF_CFG_DEV2_RC1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_SLOT_CAP 0x3fff7bfd0c1b |
| #define regBIF_CFG_DEV2_RC1_SLOT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_SLOT_CNTL 0x3fff7bfd0c1c |
| #define regBIF_CFG_DEV2_RC1_SLOT_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_SLOT_STATUS 0x3fff7bfd0c1c |
| #define regBIF_CFG_DEV2_RC1_SLOT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_ROOT_CNTL 0x3fff7bfd0c1d |
| #define regBIF_CFG_DEV2_RC1_ROOT_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_ROOT_CAP 0x3fff7bfd0c1d |
| #define regBIF_CFG_DEV2_RC1_ROOT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_ROOT_STATUS 0x3fff7bfd0c1e |
| #define regBIF_CFG_DEV2_RC1_ROOT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_CAP2 0x3fff7bfd0c1f |
| #define regBIF_CFG_DEV2_RC1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_CNTL2 0x3fff7bfd0c20 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_STATUS2 0x3fff7bfd0c20 |
| #define regBIF_CFG_DEV2_RC1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LINK_CAP2 0x3fff7bfd0c21 |
| #define regBIF_CFG_DEV2_RC1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LINK_CNTL2 0x3fff7bfd0c22 |
| #define regBIF_CFG_DEV2_RC1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LINK_STATUS2 0x3fff7bfd0c22 |
| #define regBIF_CFG_DEV2_RC1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_SLOT_CAP2 0x3fff7bfd0c23 |
| #define regBIF_CFG_DEV2_RC1_SLOT_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_SLOT_CNTL2 0x3fff7bfd0c24 |
| #define regBIF_CFG_DEV2_RC1_SLOT_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_SLOT_STATUS2 0x3fff7bfd0c24 |
| #define regBIF_CFG_DEV2_RC1_SLOT_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MSI_CAP_LIST 0x3fff7bfd0c28 |
| #define regBIF_CFG_DEV2_RC1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MSI_MSG_CNTL 0x3fff7bfd0c28 |
| #define regBIF_CFG_DEV2_RC1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MSI_MSG_ADDR_LO 0x3fff7bfd0c29 |
| #define regBIF_CFG_DEV2_RC1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MSI_MSG_ADDR_HI 0x3fff7bfd0c2a |
| #define regBIF_CFG_DEV2_RC1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MSI_MSG_DATA 0x3fff7bfd0c2a |
| #define regBIF_CFG_DEV2_RC1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA 0x3fff7bfd0c2a |
| #define regBIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MSI_MSG_DATA_64 0x3fff7bfd0c2b |
| #define regBIF_CFG_DEV2_RC1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_64 0x3fff7bfd0c2b |
| #define regBIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_SSID_CAP_LIST 0x3fff7bfd0c30 |
| #define regBIF_CFG_DEV2_RC1_SSID_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_SSID_CAP 0x3fff7bfd0c31 |
| #define regBIF_CFG_DEV2_RC1_SSID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST 0x3fff7bfd0c32 |
| #define regBIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MSI_MAP_CAP 0x3fff7bfd0c32 |
| #define regBIF_CFG_DEV2_RC1_MSI_MAP_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff7bfd0c40 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff7bfd0c41 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC1 0x3fff7bfd0c42 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC2 0x3fff7bfd0c43 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST 0x3fff7bfd0c44 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1 0x3fff7bfd0c45 |
| #define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2 0x3fff7bfd0c46 |
| #define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL 0x3fff7bfd0c47 |
| #define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_STATUS 0x3fff7bfd0c47 |
| #define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP 0x3fff7bfd0c48 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL 0x3fff7bfd0c49 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS 0x3fff7bfd0c4a |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP 0x3fff7bfd0c4b |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL 0x3fff7bfd0c4c |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS 0x3fff7bfd0c4d |
| #define regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3fff7bfd0c50 |
| #define regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW1 0x3fff7bfd0c51 |
| #define regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW2 0x3fff7bfd0c52 |
| #define regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff7bfd0c54 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS 0x3fff7bfd0c55 |
| #define regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK 0x3fff7bfd0c56 |
| #define regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY 0x3fff7bfd0c57 |
| #define regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS 0x3fff7bfd0c58 |
| #define regBIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK 0x3fff7bfd0c59 |
| #define regBIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL 0x3fff7bfd0c5a |
| #define regBIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG0 0x3fff7bfd0c5b |
| #define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG1 0x3fff7bfd0c5c |
| #define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG2 0x3fff7bfd0c5d |
| #define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG3 0x3fff7bfd0c5e |
| #define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD 0x3fff7bfd0c5f |
| #define regBIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS 0x3fff7bfd0c60 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID 0x3fff7bfd0c61 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG0 0x3fff7bfd0c62 |
| #define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG1 0x3fff7bfd0c63 |
| #define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG2 0x3fff7bfd0c64 |
| #define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG3 0x3fff7bfd0c65 |
| #define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff7bfd0c9c |
| #define regBIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3 0x3fff7bfd0c9d |
| #define regBIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_ERROR_STATUS 0x3fff7bfd0c9e |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff7bfd0c9f |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff7bfd0c9f |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff7bfd0ca0 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff7bfd0ca0 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff7bfd0ca1 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff7bfd0ca1 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff7bfd0ca2 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff7bfd0ca2 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff7bfd0ca3 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff7bfd0ca3 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff7bfd0ca4 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff7bfd0ca4 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff7bfd0ca5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff7bfd0ca5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff7bfd0ca6 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff7bfd0ca6 |
| #define regBIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST 0x3fff7bfd0ca8 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ACS_CAP 0x3fff7bfd0ca9 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ACS_CNTL 0x3fff7bfd0ca9 |
| #define regBIF_CFG_DEV2_RC1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST 0x3fff7bfd0d00 |
| #define regBIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP 0x3fff7bfd0d01 |
| #define regBIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS 0x3fff7bfd0d02 |
| #define regBIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST 0x3fff7bfd0d04 |
| #define regBIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LINK_CAP_16GT 0x3fff7bfd0d05 |
| #define regBIF_CFG_DEV2_RC1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LINK_CNTL_16GT 0x3fff7bfd0d06 |
| #define regBIF_CFG_DEV2_RC1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LINK_STATUS_16GT 0x3fff7bfd0d07 |
| #define regBIF_CFG_DEV2_RC1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x3fff7bfd0d08 |
| #define regBIF_CFG_DEV2_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x3fff7bfd0d09 |
| #define regBIF_CFG_DEV2_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x3fff7bfd0d0a |
| #define regBIF_CFG_DEV2_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0c |
| #define regBIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0c |
| #define regBIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0c |
| #define regBIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0c |
| #define regBIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0d |
| #define regBIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0d |
| #define regBIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0d |
| #define regBIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0d |
| #define regBIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0e |
| #define regBIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0e |
| #define regBIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0e |
| #define regBIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0e |
| #define regBIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0f |
| #define regBIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0f |
| #define regBIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0f |
| #define regBIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT 0x3fff7bfd0d0f |
| #define regBIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST 0x3fff7bfd0d14 |
| #define regBIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MARGINING_PORT_CAP 0x3fff7bfd0d15 |
| #define regBIF_CFG_DEV2_RC1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS 0x3fff7bfd0d15 |
| #define regBIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL 0x3fff7bfd0d16 |
| #define regBIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS 0x3fff7bfd0d16 |
| #define regBIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL 0x3fff7bfd0d17 |
| #define regBIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS 0x3fff7bfd0d17 |
| #define regBIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL 0x3fff7bfd0d18 |
| #define regBIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS 0x3fff7bfd0d18 |
| #define regBIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL 0x3fff7bfd0d19 |
| #define regBIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS 0x3fff7bfd0d19 |
| #define regBIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL 0x3fff7bfd0d1a |
| #define regBIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS 0x3fff7bfd0d1a |
| #define regBIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL 0x3fff7bfd0d1b |
| #define regBIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS 0x3fff7bfd0d1b |
| #define regBIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL 0x3fff7bfd0d1c |
| #define regBIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS 0x3fff7bfd0d1c |
| #define regBIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL 0x3fff7bfd0d1d |
| #define regBIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS 0x3fff7bfd0d1d |
| #define regBIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL 0x3fff7bfd0d1e |
| #define regBIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS 0x3fff7bfd0d1e |
| #define regBIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL 0x3fff7bfd0d1f |
| #define regBIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS 0x3fff7bfd0d1f |
| #define regBIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL 0x3fff7bfd0d20 |
| #define regBIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS 0x3fff7bfd0d20 |
| #define regBIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL 0x3fff7bfd0d21 |
| #define regBIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS 0x3fff7bfd0d21 |
| #define regBIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL 0x3fff7bfd0d22 |
| #define regBIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS 0x3fff7bfd0d22 |
| #define regBIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL 0x3fff7bfd0d23 |
| #define regBIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS 0x3fff7bfd0d23 |
| #define regBIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL 0x3fff7bfd0d24 |
| #define regBIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS 0x3fff7bfd0d24 |
| #define regBIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL 0x3fff7bfd0d25 |
| #define regBIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS 0x3fff7bfd0d25 |
| #define regBIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
| // base address: 0xfffe12100000 |
| #define regBIF_CFG_DEV0_EPF0_1_VENDOR_ID 0x3fff80800000 |
| #define regBIF_CFG_DEV0_EPF0_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_ID 0x3fff80800000 |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_COMMAND 0x3fff80800001 |
| #define regBIF_CFG_DEV0_EPF0_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_STATUS 0x3fff80800001 |
| #define regBIF_CFG_DEV0_EPF0_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_REVISION_ID 0x3fff80800002 |
| #define regBIF_CFG_DEV0_EPF0_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE 0x3fff80800002 |
| #define regBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_SUB_CLASS 0x3fff80800002 |
| #define regBIF_CFG_DEV0_EPF0_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_CLASS 0x3fff80800002 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_CACHE_LINE 0x3fff80800003 |
| #define regBIF_CFG_DEV0_EPF0_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LATENCY 0x3fff80800003 |
| #define regBIF_CFG_DEV0_EPF0_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_HEADER 0x3fff80800003 |
| #define regBIF_CFG_DEV0_EPF0_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_BIST 0x3fff80800003 |
| #define regBIF_CFG_DEV0_EPF0_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1 0x3fff80800004 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2 0x3fff80800005 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3 0x3fff80800006 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4 0x3fff80800007 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5 0x3fff80800008 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6 0x3fff80800009 |
| #define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR 0x3fff8080000a |
| #define regBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_ADAPTER_ID 0x3fff8080000b |
| #define regBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR 0x3fff8080000c |
| #define regBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_CAP_PTR 0x3fff8080000d |
| #define regBIF_CFG_DEV0_EPF0_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE 0x3fff8080000f |
| #define regBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN 0x3fff8080000f |
| #define regBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MIN_GRANT 0x3fff8080000f |
| #define regBIF_CFG_DEV0_EPF0_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MAX_LATENCY 0x3fff8080000f |
| #define regBIF_CFG_DEV0_EPF0_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST 0x3fff80800012 |
| #define regBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W 0x3fff80800013 |
| #define regBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST 0x3fff80800014 |
| #define regBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PMI_CAP 0x3fff80800014 |
| #define regBIF_CFG_DEV0_EPF0_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL 0x3fff80800015 |
| #define regBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST 0x3fff80800019 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_CAP 0x3fff80800019 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_CAP 0x3fff8080001a |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL 0x3fff8080001b |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS 0x3fff8080001b |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_CAP 0x3fff8080001c |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_CNTL 0x3fff8080001d |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_STATUS 0x3fff8080001d |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2 0x3fff80800022 |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2 0x3fff80800023 |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2 0x3fff80800023 |
| #define regBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_CAP2 0x3fff80800024 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_CNTL2 0x3fff80800025 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_STATUS2 0x3fff80800025 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST 0x3fff80800028 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL 0x3fff80800028 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO 0x3fff80800029 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI 0x3fff8080002a |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA 0x3fff8080002a |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA 0x3fff8080002a |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MASK 0x3fff8080002b |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64 0x3fff8080002b |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64 0x3fff8080002b |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MASK_64 0x3fff8080002c |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_PENDING 0x3fff8080002c |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64 0x3fff8080002d |
| #define regBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST 0x3fff80800030 |
| #define regBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL 0x3fff80800030 |
| #define regBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSIX_TABLE 0x3fff80800031 |
| #define regBIF_CFG_DEV0_EPF0_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MSIX_PBA 0x3fff80800032 |
| #define regBIF_CFG_DEV0_EPF0_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80800040 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80800041 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1 0x3fff80800042 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2 0x3fff80800043 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST 0x3fff80800044 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1 0x3fff80800045 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2 0x3fff80800046 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL 0x3fff80800047 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS 0x3fff80800047 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP 0x3fff80800048 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL 0x3fff80800049 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS 0x3fff8080004a |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP 0x3fff8080004b |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL 0x3fff8080004c |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS 0x3fff8080004d |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3fff80800050 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1 0x3fff80800051 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2 0x3fff80800052 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80800054 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS 0x3fff80800055 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK 0x3fff80800056 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80800057 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS 0x3fff80800058 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK 0x3fff80800059 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff8080005a |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0 0x3fff8080005b |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1 0x3fff8080005c |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2 0x3fff8080005d |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3 0x3fff8080005e |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0 0x3fff80800062 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1 0x3fff80800063 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2 0x3fff80800064 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3 0x3fff80800065 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80800080 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP 0x3fff80800081 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL 0x3fff80800082 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP 0x3fff80800083 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL 0x3fff80800084 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP 0x3fff80800085 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL 0x3fff80800086 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP 0x3fff80800087 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL 0x3fff80800088 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP 0x3fff80800089 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL 0x3fff8080008a |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP 0x3fff8080008b |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL 0x3fff8080008c |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80800090 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80800091 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA 0x3fff80800092 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP 0x3fff80800093 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80800094 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP 0x3fff80800095 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80800096 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS 0x3fff80800097 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL 0x3fff80800097 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80800098 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80800098 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80800098 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80800098 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80800099 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80800099 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80800099 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80800099 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff8080009c |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3 0x3fff8080009d |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS 0x3fff8080009e |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff8080009f |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff8080009f |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff808000a0 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff808000a0 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff808000a1 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff808000a1 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff808000a2 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff808000a2 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff808000a3 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff808000a3 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff808000a4 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff808000a4 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff808000a5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff808000a5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff808000a6 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff808000a6 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST 0x3fff808000a8 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP 0x3fff808000a9 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL 0x3fff808000a9 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST 0x3fff808000ac |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP 0x3fff808000ad |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL 0x3fff808000ad |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST 0x3fff808000b0 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL 0x3fff808000b1 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS 0x3fff808000b1 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x3fff808000b2 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x3fff808000b3 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST 0x3fff808000b4 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP 0x3fff808000b5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL 0x3fff808000b5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST 0x3fff808000bc |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP 0x3fff808000bd |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL 0x3fff808000bd |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0 0x3fff808000be |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1 0x3fff808000bf |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0 0x3fff808000c0 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1 0x3fff808000c1 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0 0x3fff808000c2 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1 0x3fff808000c3 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x3fff808000c4 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x3fff808000c5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST 0x3fff808000c8 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP 0x3fff808000c9 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST 0x3fff808000ca |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP 0x3fff808000cb |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL 0x3fff808000cb |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST 0x3fff808000cc |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP 0x3fff808000cd |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL 0x3fff808000ce |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS 0x3fff808000ce |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS 0x3fff808000cf |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS 0x3fff808000cf |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS 0x3fff808000d0 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK 0x3fff808000d0 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET 0x3fff808000d1 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE 0x3fff808000d1 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID 0x3fff808000d2 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x3fff808000d3 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x3fff808000d4 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0 0x3fff808000d5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1 0x3fff808000d6 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2 0x3fff808000d7 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3 0x3fff808000d8 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4 0x3fff808000d9 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5 0x3fff808000da |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x3fff808000db |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST 0x3fff80800100 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP 0x3fff80800101 |
| #define regBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS 0x3fff80800102 |
| #define regBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x3fff80800104 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT 0x3fff80800105 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT 0x3fff80800106 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT 0x3fff80800107 |
| #define regBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x3fff80800108 |
| #define regBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x3fff80800109 |
| #define regBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x3fff8080010a |
| #define regBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT 0x3fff8080010c |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT 0x3fff8080010c |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT 0x3fff8080010c |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT 0x3fff8080010c |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT 0x3fff8080010d |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT 0x3fff8080010d |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT 0x3fff8080010d |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT 0x3fff8080010d |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT 0x3fff8080010e |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT 0x3fff8080010e |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT 0x3fff8080010e |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT 0x3fff8080010e |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT 0x3fff8080010f |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT 0x3fff8080010f |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT 0x3fff8080010f |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT 0x3fff8080010f |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST 0x3fff80800114 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP 0x3fff80800115 |
| #define regBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS 0x3fff80800115 |
| #define regBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL 0x3fff80800116 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS 0x3fff80800116 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL 0x3fff80800117 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS 0x3fff80800117 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL 0x3fff80800118 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS 0x3fff80800118 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL 0x3fff80800119 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS 0x3fff80800119 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL 0x3fff8080011a |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS 0x3fff8080011a |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL 0x3fff8080011b |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS 0x3fff8080011b |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL 0x3fff8080011c |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS 0x3fff8080011c |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL 0x3fff8080011d |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS 0x3fff8080011d |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL 0x3fff8080011e |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS 0x3fff8080011e |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL 0x3fff8080011f |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS 0x3fff8080011f |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL 0x3fff80800120 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS 0x3fff80800120 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL 0x3fff80800121 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS 0x3fff80800121 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL 0x3fff80800122 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS 0x3fff80800122 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL 0x3fff80800123 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS 0x3fff80800123 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL 0x3fff80800124 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS 0x3fff80800124 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL 0x3fff80800125 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS 0x3fff80800125 |
| #define regBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x3fff80800130 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP 0x3fff80800131 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL 0x3fff80800132 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP 0x3fff80800133 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL 0x3fff80800134 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP 0x3fff80800135 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL 0x3fff80800136 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP 0x3fff80800137 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL 0x3fff80800138 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP 0x3fff80800139 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL 0x3fff8080013a |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP 0x3fff8080013b |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL 0x3fff8080013c |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x3fff80800160 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x3fff80800161 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x3fff80800162 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x3fff80800163 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x3fff80800164 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x3fff80800165 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x3fff80800166 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x3fff80800167 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x3fff80800168 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x3fff80800169 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x3fff8080016a |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x3fff8080016b |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x3fff8080016c |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x3fff8080016d |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x3fff8080016e |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x3fff8080016f |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x3fff80800170 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x3fff80800171 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x3fff80800172 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x3fff80800173 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x3fff80800174 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x3fff80800175 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x3fff80800176 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x3fff80800177 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x3fff80800178 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x3fff80800179 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x3fff8080017a |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x3fff8080017b |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x3fff8080017c |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x3fff8080017d |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x3fff8080017e |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x3fff8080017f |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x3fff80800180 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x3fff80800181 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x3fff80800182 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x3fff80800183 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x3fff80800184 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x3fff80800185 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x3fff80800186 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x3fff80800187 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x3fff80800188 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x3fff80800189 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x3fff8080018a |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x3fff8080018b |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x3fff8080018c |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x3fff80800190 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x3fff80800191 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x3fff80800192 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x3fff80800193 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x3fff80800194 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x3fff80800195 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x3fff80800196 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x3fff80800197 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x3fff80800198 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x3fff8080019c |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x3fff8080019d |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x3fff8080019e |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x3fff8080019f |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x3fff808001a0 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x3fff808001a1 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x3fff808001a2 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x3fff808001a3 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x3fff808001a4 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x3fff808001a8 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x3fff808001a9 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x3fff808001aa |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x3fff808001ab |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x3fff808001ac |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x3fff808001ad |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x3fff808001ae |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x3fff808001af |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x3fff808001b0 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x3fff808001b4 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x3fff808001b5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x3fff808001b6 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x3fff808001b7 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x3fff808001b8 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x3fff808001b9 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x3fff808001ba |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x3fff808001bb |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x3fff808001bc |
| #define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
| // base address: 0xfffe12101000 |
| #define regBIF_CFG_DEV0_EPF1_1_VENDOR_ID 0x3fff80800400 |
| #define regBIF_CFG_DEV0_EPF1_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_ID 0x3fff80800400 |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_COMMAND 0x3fff80800401 |
| #define regBIF_CFG_DEV0_EPF1_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_STATUS 0x3fff80800401 |
| #define regBIF_CFG_DEV0_EPF1_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_REVISION_ID 0x3fff80800402 |
| #define regBIF_CFG_DEV0_EPF1_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE 0x3fff80800402 |
| #define regBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_SUB_CLASS 0x3fff80800402 |
| #define regBIF_CFG_DEV0_EPF1_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_CLASS 0x3fff80800402 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_CACHE_LINE 0x3fff80800403 |
| #define regBIF_CFG_DEV0_EPF1_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LATENCY 0x3fff80800403 |
| #define regBIF_CFG_DEV0_EPF1_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_HEADER 0x3fff80800403 |
| #define regBIF_CFG_DEV0_EPF1_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_BIST 0x3fff80800403 |
| #define regBIF_CFG_DEV0_EPF1_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 0x3fff80800404 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 0x3fff80800405 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 0x3fff80800406 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 0x3fff80800407 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 0x3fff80800408 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 0x3fff80800409 |
| #define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR 0x3fff8080040a |
| #define regBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_ADAPTER_ID 0x3fff8080040b |
| #define regBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR 0x3fff8080040c |
| #define regBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_CAP_PTR 0x3fff8080040d |
| #define regBIF_CFG_DEV0_EPF1_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE 0x3fff8080040f |
| #define regBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN 0x3fff8080040f |
| #define regBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MIN_GRANT 0x3fff8080040f |
| #define regBIF_CFG_DEV0_EPF1_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MAX_LATENCY 0x3fff8080040f |
| #define regBIF_CFG_DEV0_EPF1_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST 0x3fff80800412 |
| #define regBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W 0x3fff80800413 |
| #define regBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST 0x3fff80800414 |
| #define regBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PMI_CAP 0x3fff80800414 |
| #define regBIF_CFG_DEV0_EPF1_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL 0x3fff80800415 |
| #define regBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST 0x3fff80800419 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_CAP 0x3fff80800419 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_CAP 0x3fff8080041a |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL 0x3fff8080041b |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS 0x3fff8080041b |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_CAP 0x3fff8080041c |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_CNTL 0x3fff8080041d |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_STATUS 0x3fff8080041d |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 0x3fff80800422 |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 0x3fff80800423 |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 0x3fff80800423 |
| #define regBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_CAP2 0x3fff80800424 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_CNTL2 0x3fff80800425 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_STATUS2 0x3fff80800425 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST 0x3fff80800428 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL 0x3fff80800428 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO 0x3fff80800429 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI 0x3fff8080042a |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA 0x3fff8080042a |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA 0x3fff8080042a |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MASK 0x3fff8080042b |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 0x3fff8080042b |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64 0x3fff8080042b |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MASK_64 0x3fff8080042c |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_PENDING 0x3fff8080042c |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 0x3fff8080042d |
| #define regBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST 0x3fff80800430 |
| #define regBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL 0x3fff80800430 |
| #define regBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSIX_TABLE 0x3fff80800431 |
| #define regBIF_CFG_DEV0_EPF1_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MSIX_PBA 0x3fff80800432 |
| #define regBIF_CFG_DEV0_EPF1_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80800440 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80800441 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 0x3fff80800442 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 0x3fff80800443 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3fff80800450 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 0x3fff80800451 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 0x3fff80800452 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80800454 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS 0x3fff80800455 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK 0x3fff80800456 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80800457 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS 0x3fff80800458 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK 0x3fff80800459 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff8080045a |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 0x3fff8080045b |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 0x3fff8080045c |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 0x3fff8080045d |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 0x3fff8080045e |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 0x3fff80800462 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 0x3fff80800463 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 0x3fff80800464 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 0x3fff80800465 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80800480 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP 0x3fff80800481 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL 0x3fff80800482 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP 0x3fff80800483 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL 0x3fff80800484 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP 0x3fff80800485 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL 0x3fff80800486 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP 0x3fff80800487 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL 0x3fff80800488 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP 0x3fff80800489 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL 0x3fff8080048a |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP 0x3fff8080048b |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL 0x3fff8080048c |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80800490 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80800491 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA 0x3fff80800492 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP 0x3fff80800493 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80800494 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP 0x3fff80800495 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80800496 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS 0x3fff80800497 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL 0x3fff80800497 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80800498 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80800498 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80800498 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80800498 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80800499 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80800499 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80800499 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80800499 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff8080049c |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 0x3fff8080049d |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS 0x3fff8080049e |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff8080049f |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff8080049f |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff808004a0 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff808004a0 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff808004a1 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff808004a1 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff808004a2 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff808004a2 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff808004a3 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff808004a3 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff808004a4 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff808004a4 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff808004a5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff808004a5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff808004a6 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff808004a6 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST 0x3fff808004a8 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP 0x3fff808004a9 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL 0x3fff808004a9 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST 0x3fff808004ac |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP 0x3fff808004ad |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL 0x3fff808004ad |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST 0x3fff808004b0 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL 0x3fff808004b1 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS 0x3fff808004b1 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x3fff808004b2 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x3fff808004b3 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST 0x3fff808004b4 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP 0x3fff808004b5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL 0x3fff808004b5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST 0x3fff808004bc |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP 0x3fff808004bd |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL 0x3fff808004bd |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 0x3fff808004be |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 0x3fff808004bf |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 0x3fff808004c0 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 0x3fff808004c1 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 0x3fff808004c2 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 0x3fff808004c3 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x3fff808004c4 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x3fff808004c5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST 0x3fff808004c8 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP 0x3fff808004c9 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST 0x3fff808004ca |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP 0x3fff808004cb |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL 0x3fff808004cb |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST 0x3fff808004cc |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP 0x3fff808004cd |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL 0x3fff808004ce |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS 0x3fff808004ce |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS 0x3fff808004cf |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS 0x3fff808004cf |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS 0x3fff808004d0 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK 0x3fff808004d0 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET 0x3fff808004d1 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE 0x3fff808004d1 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID 0x3fff808004d2 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x3fff808004d3 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x3fff808004d4 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 0x3fff808004d5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 0x3fff808004d6 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 0x3fff808004d7 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 0x3fff808004d8 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 0x3fff808004d9 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 0x3fff808004da |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x3fff808004db |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST 0x3fff80800500 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP 0x3fff80800501 |
| #define regBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS 0x3fff80800502 |
| #define regBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x3fff80800504 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT 0x3fff80800505 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT 0x3fff80800506 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT 0x3fff80800507 |
| #define regBIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x3fff80800508 |
| #define regBIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x3fff80800509 |
| #define regBIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x3fff8080050a |
| #define regBIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT 0x3fff8080050c |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT 0x3fff8080050c |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT 0x3fff8080050c |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT 0x3fff8080050c |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT 0x3fff8080050d |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT 0x3fff8080050d |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT 0x3fff8080050d |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT 0x3fff8080050d |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT 0x3fff8080050e |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT 0x3fff8080050e |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT 0x3fff8080050e |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT 0x3fff8080050e |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT 0x3fff8080050f |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT 0x3fff8080050f |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT 0x3fff8080050f |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT 0x3fff8080050f |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST 0x3fff80800514 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP 0x3fff80800515 |
| #define regBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS 0x3fff80800515 |
| #define regBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL 0x3fff80800516 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS 0x3fff80800516 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL 0x3fff80800517 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS 0x3fff80800517 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL 0x3fff80800518 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS 0x3fff80800518 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL 0x3fff80800519 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS 0x3fff80800519 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL 0x3fff8080051a |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS 0x3fff8080051a |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL 0x3fff8080051b |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS 0x3fff8080051b |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL 0x3fff8080051c |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS 0x3fff8080051c |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL 0x3fff8080051d |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS 0x3fff8080051d |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL 0x3fff8080051e |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS 0x3fff8080051e |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL 0x3fff8080051f |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS 0x3fff8080051f |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL 0x3fff80800520 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS 0x3fff80800520 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL 0x3fff80800521 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS 0x3fff80800521 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL 0x3fff80800522 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS 0x3fff80800522 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL 0x3fff80800523 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS 0x3fff80800523 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL 0x3fff80800524 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS 0x3fff80800524 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL 0x3fff80800525 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS 0x3fff80800525 |
| #define regBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x3fff80800530 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP 0x3fff80800531 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL 0x3fff80800532 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP 0x3fff80800533 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL 0x3fff80800534 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP 0x3fff80800535 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL 0x3fff80800536 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP 0x3fff80800537 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL 0x3fff80800538 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP 0x3fff80800539 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL 0x3fff8080053a |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP 0x3fff8080053b |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL 0x3fff8080053c |
| #define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
| // base address: 0xfffe12102000 |
| #define regBIF_CFG_DEV0_EPF2_1_VENDOR_ID 0x3fff80800800 |
| #define regBIF_CFG_DEV0_EPF2_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_ID 0x3fff80800800 |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_COMMAND 0x3fff80800801 |
| #define regBIF_CFG_DEV0_EPF2_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_STATUS 0x3fff80800801 |
| #define regBIF_CFG_DEV0_EPF2_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_REVISION_ID 0x3fff80800802 |
| #define regBIF_CFG_DEV0_EPF2_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE 0x3fff80800802 |
| #define regBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_SUB_CLASS 0x3fff80800802 |
| #define regBIF_CFG_DEV0_EPF2_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_CLASS 0x3fff80800802 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_CACHE_LINE 0x3fff80800803 |
| #define regBIF_CFG_DEV0_EPF2_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_LATENCY 0x3fff80800803 |
| #define regBIF_CFG_DEV0_EPF2_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_HEADER 0x3fff80800803 |
| #define regBIF_CFG_DEV0_EPF2_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_BIST 0x3fff80800803 |
| #define regBIF_CFG_DEV0_EPF2_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 0x3fff80800804 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 0x3fff80800805 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 0x3fff80800806 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 0x3fff80800807 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 0x3fff80800808 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 0x3fff80800809 |
| #define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR 0x3fff8080080a |
| #define regBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_ADAPTER_ID 0x3fff8080080b |
| #define regBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR 0x3fff8080080c |
| #define regBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_CAP_PTR 0x3fff8080080d |
| #define regBIF_CFG_DEV0_EPF2_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE 0x3fff8080080f |
| #define regBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN 0x3fff8080080f |
| #define regBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MIN_GRANT 0x3fff8080080f |
| #define regBIF_CFG_DEV0_EPF2_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MAX_LATENCY 0x3fff8080080f |
| #define regBIF_CFG_DEV0_EPF2_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST 0x3fff80800812 |
| #define regBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W 0x3fff80800813 |
| #define regBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST 0x3fff80800814 |
| #define regBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PMI_CAP 0x3fff80800814 |
| #define regBIF_CFG_DEV0_EPF2_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL 0x3fff80800815 |
| #define regBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_SBRN 0x3fff80800818 |
| #define regBIF_CFG_DEV0_EPF2_1_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_FLADJ 0x3fff80800818 |
| #define regBIF_CFG_DEV0_EPF2_1_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD 0x3fff80800818 |
| #define regBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST 0x3fff80800819 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_CAP 0x3fff80800819 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_CAP 0x3fff8080081a |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL 0x3fff8080081b |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS 0x3fff8080081b |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_LINK_CAP 0x3fff8080081c |
| #define regBIF_CFG_DEV0_EPF2_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_LINK_CNTL 0x3fff8080081d |
| #define regBIF_CFG_DEV0_EPF2_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_LINK_STATUS 0x3fff8080081d |
| #define regBIF_CFG_DEV0_EPF2_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 0x3fff80800822 |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 0x3fff80800823 |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 0x3fff80800823 |
| #define regBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_LINK_CAP2 0x3fff80800824 |
| #define regBIF_CFG_DEV0_EPF2_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_LINK_CNTL2 0x3fff80800825 |
| #define regBIF_CFG_DEV0_EPF2_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_LINK_STATUS2 0x3fff80800825 |
| #define regBIF_CFG_DEV0_EPF2_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST 0x3fff80800828 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL 0x3fff80800828 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO 0x3fff80800829 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI 0x3fff8080082a |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA 0x3fff8080082a |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA 0x3fff8080082a |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MASK 0x3fff8080082b |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 0x3fff8080082b |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64 0x3fff8080082b |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MASK_64 0x3fff8080082c |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_PENDING 0x3fff8080082c |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 0x3fff8080082d |
| #define regBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST 0x3fff80800830 |
| #define regBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL 0x3fff80800830 |
| #define regBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSIX_TABLE 0x3fff80800831 |
| #define regBIF_CFG_DEV0_EPF2_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_MSIX_PBA 0x3fff80800832 |
| #define regBIF_CFG_DEV0_EPF2_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_SATA_CAP_0 0x3fff80800834 |
| #define regBIF_CFG_DEV0_EPF2_1_SATA_CAP_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_SATA_CAP_1 0x3fff80800835 |
| #define regBIF_CFG_DEV0_EPF2_1_SATA_CAP_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX 0x3fff80800836 |
| #define regBIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA 0x3fff80800837 |
| #define regBIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80800840 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80800841 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 0x3fff80800842 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 0x3fff80800843 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80800854 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS 0x3fff80800855 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK 0x3fff80800856 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80800857 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS 0x3fff80800858 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK 0x3fff80800859 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff8080085a |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 0x3fff8080085b |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 0x3fff8080085c |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 0x3fff8080085d |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 0x3fff8080085e |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 0x3fff80800862 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 0x3fff80800863 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 0x3fff80800864 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 0x3fff80800865 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80800880 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP 0x3fff80800881 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL 0x3fff80800882 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP 0x3fff80800883 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL 0x3fff80800884 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP 0x3fff80800885 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL 0x3fff80800886 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP 0x3fff80800887 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL 0x3fff80800888 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP 0x3fff80800889 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL 0x3fff8080088a |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP 0x3fff8080088b |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL 0x3fff8080088c |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80800890 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80800891 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA 0x3fff80800892 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP 0x3fff80800893 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80800894 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP 0x3fff80800895 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80800896 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS 0x3fff80800897 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL 0x3fff80800897 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80800898 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80800898 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80800898 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80800898 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80800899 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80800899 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80800899 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80800899 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST 0x3fff808008a8 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP 0x3fff808008a9 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL 0x3fff808008a9 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST 0x3fff808008b4 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP 0x3fff808008b5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL 0x3fff808008b5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST 0x3fff808008ca |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP 0x3fff808008cb |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL 0x3fff808008cb |
| #define regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
| // base address: 0xfffe12103000 |
| #define regBIF_CFG_DEV0_EPF3_1_VENDOR_ID 0x3fff80800c00 |
| #define regBIF_CFG_DEV0_EPF3_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_ID 0x3fff80800c00 |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_COMMAND 0x3fff80800c01 |
| #define regBIF_CFG_DEV0_EPF3_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_STATUS 0x3fff80800c01 |
| #define regBIF_CFG_DEV0_EPF3_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_REVISION_ID 0x3fff80800c02 |
| #define regBIF_CFG_DEV0_EPF3_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE 0x3fff80800c02 |
| #define regBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_SUB_CLASS 0x3fff80800c02 |
| #define regBIF_CFG_DEV0_EPF3_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_CLASS 0x3fff80800c02 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_CACHE_LINE 0x3fff80800c03 |
| #define regBIF_CFG_DEV0_EPF3_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_LATENCY 0x3fff80800c03 |
| #define regBIF_CFG_DEV0_EPF3_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_HEADER 0x3fff80800c03 |
| #define regBIF_CFG_DEV0_EPF3_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_BIST 0x3fff80800c03 |
| #define regBIF_CFG_DEV0_EPF3_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 0x3fff80800c04 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 0x3fff80800c05 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 0x3fff80800c06 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 0x3fff80800c07 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 0x3fff80800c08 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 0x3fff80800c09 |
| #define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR 0x3fff80800c0a |
| #define regBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_ADAPTER_ID 0x3fff80800c0b |
| #define regBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR 0x3fff80800c0c |
| #define regBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_CAP_PTR 0x3fff80800c0d |
| #define regBIF_CFG_DEV0_EPF3_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE 0x3fff80800c0f |
| #define regBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN 0x3fff80800c0f |
| #define regBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MIN_GRANT 0x3fff80800c0f |
| #define regBIF_CFG_DEV0_EPF3_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MAX_LATENCY 0x3fff80800c0f |
| #define regBIF_CFG_DEV0_EPF3_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST 0x3fff80800c12 |
| #define regBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W 0x3fff80800c13 |
| #define regBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST 0x3fff80800c14 |
| #define regBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PMI_CAP 0x3fff80800c14 |
| #define regBIF_CFG_DEV0_EPF3_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL 0x3fff80800c15 |
| #define regBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_SBRN 0x3fff80800c18 |
| #define regBIF_CFG_DEV0_EPF3_1_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_FLADJ 0x3fff80800c18 |
| #define regBIF_CFG_DEV0_EPF3_1_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD 0x3fff80800c18 |
| #define regBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST 0x3fff80800c19 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_CAP 0x3fff80800c19 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_CAP 0x3fff80800c1a |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL 0x3fff80800c1b |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS 0x3fff80800c1b |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_LINK_CAP 0x3fff80800c1c |
| #define regBIF_CFG_DEV0_EPF3_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_LINK_CNTL 0x3fff80800c1d |
| #define regBIF_CFG_DEV0_EPF3_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_LINK_STATUS 0x3fff80800c1d |
| #define regBIF_CFG_DEV0_EPF3_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 0x3fff80800c22 |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 0x3fff80800c23 |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 0x3fff80800c23 |
| #define regBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_LINK_CAP2 0x3fff80800c24 |
| #define regBIF_CFG_DEV0_EPF3_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_LINK_CNTL2 0x3fff80800c25 |
| #define regBIF_CFG_DEV0_EPF3_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_LINK_STATUS2 0x3fff80800c25 |
| #define regBIF_CFG_DEV0_EPF3_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST 0x3fff80800c28 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL 0x3fff80800c28 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO 0x3fff80800c29 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI 0x3fff80800c2a |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA 0x3fff80800c2a |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA 0x3fff80800c2a |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MASK 0x3fff80800c2b |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 0x3fff80800c2b |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64 0x3fff80800c2b |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MASK_64 0x3fff80800c2c |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_PENDING 0x3fff80800c2c |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 0x3fff80800c2d |
| #define regBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST 0x3fff80800c30 |
| #define regBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL 0x3fff80800c30 |
| #define regBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSIX_TABLE 0x3fff80800c31 |
| #define regBIF_CFG_DEV0_EPF3_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_MSIX_PBA 0x3fff80800c32 |
| #define regBIF_CFG_DEV0_EPF3_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_SATA_CAP_0 0x3fff80800c34 |
| #define regBIF_CFG_DEV0_EPF3_1_SATA_CAP_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_SATA_CAP_1 0x3fff80800c35 |
| #define regBIF_CFG_DEV0_EPF3_1_SATA_CAP_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX 0x3fff80800c36 |
| #define regBIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA 0x3fff80800c37 |
| #define regBIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80800c40 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80800c41 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 0x3fff80800c42 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 0x3fff80800c43 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80800c54 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS 0x3fff80800c55 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK 0x3fff80800c56 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80800c57 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS 0x3fff80800c58 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK 0x3fff80800c59 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff80800c5a |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 0x3fff80800c5b |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 0x3fff80800c5c |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 0x3fff80800c5d |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 0x3fff80800c5e |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 0x3fff80800c62 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 0x3fff80800c63 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 0x3fff80800c64 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 0x3fff80800c65 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80800c80 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP 0x3fff80800c81 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL 0x3fff80800c82 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP 0x3fff80800c83 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL 0x3fff80800c84 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP 0x3fff80800c85 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL 0x3fff80800c86 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP 0x3fff80800c87 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL 0x3fff80800c88 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP 0x3fff80800c89 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL 0x3fff80800c8a |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP 0x3fff80800c8b |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL 0x3fff80800c8c |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80800c90 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80800c91 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA 0x3fff80800c92 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP 0x3fff80800c93 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80800c94 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP 0x3fff80800c95 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80800c96 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS 0x3fff80800c97 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL 0x3fff80800c97 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80800c98 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80800c98 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80800c98 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80800c98 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80800c99 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80800c99 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80800c99 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80800c99 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST 0x3fff80800ca8 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP 0x3fff80800ca9 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL 0x3fff80800ca9 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST 0x3fff80800cb4 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP 0x3fff80800cb5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL 0x3fff80800cb5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST 0x3fff80800cca |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP 0x3fff80800ccb |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL 0x3fff80800ccb |
| #define regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp |
| // base address: 0xfffe12104000 |
| #define regBIF_CFG_DEV0_EPF4_1_VENDOR_ID 0x3fff80801000 |
| #define regBIF_CFG_DEV0_EPF4_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_ID 0x3fff80801000 |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_COMMAND 0x3fff80801001 |
| #define regBIF_CFG_DEV0_EPF4_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_STATUS 0x3fff80801001 |
| #define regBIF_CFG_DEV0_EPF4_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_REVISION_ID 0x3fff80801002 |
| #define regBIF_CFG_DEV0_EPF4_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PROG_INTERFACE 0x3fff80801002 |
| #define regBIF_CFG_DEV0_EPF4_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_SUB_CLASS 0x3fff80801002 |
| #define regBIF_CFG_DEV0_EPF4_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_CLASS 0x3fff80801002 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_CACHE_LINE 0x3fff80801003 |
| #define regBIF_CFG_DEV0_EPF4_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_LATENCY 0x3fff80801003 |
| #define regBIF_CFG_DEV0_EPF4_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_HEADER 0x3fff80801003 |
| #define regBIF_CFG_DEV0_EPF4_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_BIST 0x3fff80801003 |
| #define regBIF_CFG_DEV0_EPF4_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_1 0x3fff80801004 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_2 0x3fff80801005 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_3 0x3fff80801006 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_4 0x3fff80801007 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_5 0x3fff80801008 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_6 0x3fff80801009 |
| #define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_CARDBUS_CIS_PTR 0x3fff8080100a |
| #define regBIF_CFG_DEV0_EPF4_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_ADAPTER_ID 0x3fff8080100b |
| #define regBIF_CFG_DEV0_EPF4_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR 0x3fff8080100c |
| #define regBIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_CAP_PTR 0x3fff8080100d |
| #define regBIF_CFG_DEV0_EPF4_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE 0x3fff8080100f |
| #define regBIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN 0x3fff8080100f |
| #define regBIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MIN_GRANT 0x3fff8080100f |
| #define regBIF_CFG_DEV0_EPF4_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MAX_LATENCY 0x3fff8080100f |
| #define regBIF_CFG_DEV0_EPF4_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST 0x3fff80801012 |
| #define regBIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W 0x3fff80801013 |
| #define regBIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST 0x3fff80801014 |
| #define regBIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PMI_CAP 0x3fff80801014 |
| #define regBIF_CFG_DEV0_EPF4_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL 0x3fff80801015 |
| #define regBIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_SBRN 0x3fff80801018 |
| #define regBIF_CFG_DEV0_EPF4_1_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_FLADJ 0x3fff80801018 |
| #define regBIF_CFG_DEV0_EPF4_1_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_DBESL_DBESLD 0x3fff80801018 |
| #define regBIF_CFG_DEV0_EPF4_1_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST 0x3fff80801019 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_CAP 0x3fff80801019 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_CAP 0x3fff8080101a |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL 0x3fff8080101b |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS 0x3fff8080101b |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_LINK_CAP 0x3fff8080101c |
| #define regBIF_CFG_DEV0_EPF4_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_LINK_CNTL 0x3fff8080101d |
| #define regBIF_CFG_DEV0_EPF4_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_LINK_STATUS 0x3fff8080101d |
| #define regBIF_CFG_DEV0_EPF4_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_CAP2 0x3fff80801022 |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2 0x3fff80801023 |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2 0x3fff80801023 |
| #define regBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_LINK_CAP2 0x3fff80801024 |
| #define regBIF_CFG_DEV0_EPF4_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_LINK_CNTL2 0x3fff80801025 |
| #define regBIF_CFG_DEV0_EPF4_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_LINK_STATUS2 0x3fff80801025 |
| #define regBIF_CFG_DEV0_EPF4_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST 0x3fff80801028 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL 0x3fff80801028 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO 0x3fff80801029 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI 0x3fff8080102a |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA 0x3fff8080102a |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA 0x3fff8080102a |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MASK 0x3fff8080102b |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64 0x3fff8080102b |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_64 0x3fff8080102b |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MASK_64 0x3fff8080102c |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_PENDING 0x3fff8080102c |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_PENDING_64 0x3fff8080102d |
| #define regBIF_CFG_DEV0_EPF4_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST 0x3fff80801030 |
| #define regBIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL 0x3fff80801030 |
| #define regBIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSIX_TABLE 0x3fff80801031 |
| #define regBIF_CFG_DEV0_EPF4_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_MSIX_PBA 0x3fff80801032 |
| #define regBIF_CFG_DEV0_EPF4_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_SATA_CAP_0 0x3fff80801034 |
| #define regBIF_CFG_DEV0_EPF4_1_SATA_CAP_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_SATA_CAP_1 0x3fff80801035 |
| #define regBIF_CFG_DEV0_EPF4_1_SATA_CAP_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX 0x3fff80801036 |
| #define regBIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA 0x3fff80801037 |
| #define regBIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80801040 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80801041 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1 0x3fff80801042 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2 0x3fff80801043 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80801054 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS 0x3fff80801055 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK 0x3fff80801056 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80801057 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS 0x3fff80801058 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK 0x3fff80801059 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff8080105a |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0 0x3fff8080105b |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1 0x3fff8080105c |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2 0x3fff8080105d |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3 0x3fff8080105e |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0 0x3fff80801062 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1 0x3fff80801063 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2 0x3fff80801064 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3 0x3fff80801065 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80801080 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP 0x3fff80801081 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL 0x3fff80801082 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP 0x3fff80801083 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL 0x3fff80801084 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP 0x3fff80801085 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL 0x3fff80801086 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP 0x3fff80801087 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL 0x3fff80801088 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP 0x3fff80801089 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL 0x3fff8080108a |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP 0x3fff8080108b |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL 0x3fff8080108c |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80801090 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80801091 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA 0x3fff80801092 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP 0x3fff80801093 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80801094 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP 0x3fff80801095 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80801096 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS 0x3fff80801097 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL 0x3fff80801097 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80801098 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80801098 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80801098 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80801098 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80801099 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80801099 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80801099 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80801099 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST 0x3fff808010a8 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP 0x3fff808010a9 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL 0x3fff808010a9 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST 0x3fff808010b4 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP 0x3fff808010b5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL 0x3fff808010b5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST 0x3fff808010ca |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP 0x3fff808010cb |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL 0x3fff808010cb |
| #define regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp |
| // base address: 0xfffe12105000 |
| #define regBIF_CFG_DEV0_EPF5_1_VENDOR_ID 0x3fff80801400 |
| #define regBIF_CFG_DEV0_EPF5_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_ID 0x3fff80801400 |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_COMMAND 0x3fff80801401 |
| #define regBIF_CFG_DEV0_EPF5_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_STATUS 0x3fff80801401 |
| #define regBIF_CFG_DEV0_EPF5_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_REVISION_ID 0x3fff80801402 |
| #define regBIF_CFG_DEV0_EPF5_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PROG_INTERFACE 0x3fff80801402 |
| #define regBIF_CFG_DEV0_EPF5_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_SUB_CLASS 0x3fff80801402 |
| #define regBIF_CFG_DEV0_EPF5_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_CLASS 0x3fff80801402 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_CACHE_LINE 0x3fff80801403 |
| #define regBIF_CFG_DEV0_EPF5_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_LATENCY 0x3fff80801403 |
| #define regBIF_CFG_DEV0_EPF5_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_HEADER 0x3fff80801403 |
| #define regBIF_CFG_DEV0_EPF5_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_BIST 0x3fff80801403 |
| #define regBIF_CFG_DEV0_EPF5_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_1 0x3fff80801404 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_2 0x3fff80801405 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_3 0x3fff80801406 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_4 0x3fff80801407 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_5 0x3fff80801408 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_6 0x3fff80801409 |
| #define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_CARDBUS_CIS_PTR 0x3fff8080140a |
| #define regBIF_CFG_DEV0_EPF5_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_ADAPTER_ID 0x3fff8080140b |
| #define regBIF_CFG_DEV0_EPF5_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR 0x3fff8080140c |
| #define regBIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_CAP_PTR 0x3fff8080140d |
| #define regBIF_CFG_DEV0_EPF5_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE 0x3fff8080140f |
| #define regBIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN 0x3fff8080140f |
| #define regBIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MIN_GRANT 0x3fff8080140f |
| #define regBIF_CFG_DEV0_EPF5_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MAX_LATENCY 0x3fff8080140f |
| #define regBIF_CFG_DEV0_EPF5_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST 0x3fff80801412 |
| #define regBIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W 0x3fff80801413 |
| #define regBIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST 0x3fff80801414 |
| #define regBIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PMI_CAP 0x3fff80801414 |
| #define regBIF_CFG_DEV0_EPF5_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL 0x3fff80801415 |
| #define regBIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_SBRN 0x3fff80801418 |
| #define regBIF_CFG_DEV0_EPF5_1_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_FLADJ 0x3fff80801418 |
| #define regBIF_CFG_DEV0_EPF5_1_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_DBESL_DBESLD 0x3fff80801418 |
| #define regBIF_CFG_DEV0_EPF5_1_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST 0x3fff80801419 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_CAP 0x3fff80801419 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_CAP 0x3fff8080141a |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL 0x3fff8080141b |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS 0x3fff8080141b |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_LINK_CAP 0x3fff8080141c |
| #define regBIF_CFG_DEV0_EPF5_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_LINK_CNTL 0x3fff8080141d |
| #define regBIF_CFG_DEV0_EPF5_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_LINK_STATUS 0x3fff8080141d |
| #define regBIF_CFG_DEV0_EPF5_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_CAP2 0x3fff80801422 |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2 0x3fff80801423 |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2 0x3fff80801423 |
| #define regBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_LINK_CAP2 0x3fff80801424 |
| #define regBIF_CFG_DEV0_EPF5_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_LINK_CNTL2 0x3fff80801425 |
| #define regBIF_CFG_DEV0_EPF5_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_LINK_STATUS2 0x3fff80801425 |
| #define regBIF_CFG_DEV0_EPF5_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST 0x3fff80801428 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL 0x3fff80801428 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO 0x3fff80801429 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI 0x3fff8080142a |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA 0x3fff8080142a |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA 0x3fff8080142a |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MASK 0x3fff8080142b |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64 0x3fff8080142b |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_64 0x3fff8080142b |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MASK_64 0x3fff8080142c |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_PENDING 0x3fff8080142c |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_PENDING_64 0x3fff8080142d |
| #define regBIF_CFG_DEV0_EPF5_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST 0x3fff80801430 |
| #define regBIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL 0x3fff80801430 |
| #define regBIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSIX_TABLE 0x3fff80801431 |
| #define regBIF_CFG_DEV0_EPF5_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_MSIX_PBA 0x3fff80801432 |
| #define regBIF_CFG_DEV0_EPF5_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_SATA_CAP_0 0x3fff80801434 |
| #define regBIF_CFG_DEV0_EPF5_1_SATA_CAP_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_SATA_CAP_1 0x3fff80801435 |
| #define regBIF_CFG_DEV0_EPF5_1_SATA_CAP_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX 0x3fff80801436 |
| #define regBIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA 0x3fff80801437 |
| #define regBIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80801440 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80801441 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1 0x3fff80801442 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2 0x3fff80801443 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80801454 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS 0x3fff80801455 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK 0x3fff80801456 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80801457 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS 0x3fff80801458 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK 0x3fff80801459 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff8080145a |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0 0x3fff8080145b |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1 0x3fff8080145c |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2 0x3fff8080145d |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3 0x3fff8080145e |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0 0x3fff80801462 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1 0x3fff80801463 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2 0x3fff80801464 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3 0x3fff80801465 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80801480 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP 0x3fff80801481 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL 0x3fff80801482 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP 0x3fff80801483 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL 0x3fff80801484 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP 0x3fff80801485 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL 0x3fff80801486 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP 0x3fff80801487 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL 0x3fff80801488 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP 0x3fff80801489 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL 0x3fff8080148a |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP 0x3fff8080148b |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL 0x3fff8080148c |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80801490 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80801491 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA 0x3fff80801492 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP 0x3fff80801493 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80801494 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP 0x3fff80801495 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80801496 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS 0x3fff80801497 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL 0x3fff80801497 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80801498 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80801498 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80801498 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80801498 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80801499 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80801499 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80801499 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80801499 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST 0x3fff808014a8 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP 0x3fff808014a9 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL 0x3fff808014a9 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST 0x3fff808014b4 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP 0x3fff808014b5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL 0x3fff808014b5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST 0x3fff808014ca |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP 0x3fff808014cb |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL 0x3fff808014cb |
| #define regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp |
| // base address: 0xfffe12106000 |
| #define regBIF_CFG_DEV0_EPF6_1_VENDOR_ID 0x3fff80801800 |
| #define regBIF_CFG_DEV0_EPF6_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_ID 0x3fff80801800 |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_COMMAND 0x3fff80801801 |
| #define regBIF_CFG_DEV0_EPF6_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_STATUS 0x3fff80801801 |
| #define regBIF_CFG_DEV0_EPF6_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_REVISION_ID 0x3fff80801802 |
| #define regBIF_CFG_DEV0_EPF6_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PROG_INTERFACE 0x3fff80801802 |
| #define regBIF_CFG_DEV0_EPF6_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_SUB_CLASS 0x3fff80801802 |
| #define regBIF_CFG_DEV0_EPF6_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_CLASS 0x3fff80801802 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_CACHE_LINE 0x3fff80801803 |
| #define regBIF_CFG_DEV0_EPF6_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_LATENCY 0x3fff80801803 |
| #define regBIF_CFG_DEV0_EPF6_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_HEADER 0x3fff80801803 |
| #define regBIF_CFG_DEV0_EPF6_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_BIST 0x3fff80801803 |
| #define regBIF_CFG_DEV0_EPF6_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_1 0x3fff80801804 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_2 0x3fff80801805 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_3 0x3fff80801806 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_4 0x3fff80801807 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_5 0x3fff80801808 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_6 0x3fff80801809 |
| #define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_CARDBUS_CIS_PTR 0x3fff8080180a |
| #define regBIF_CFG_DEV0_EPF6_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_ADAPTER_ID 0x3fff8080180b |
| #define regBIF_CFG_DEV0_EPF6_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR 0x3fff8080180c |
| #define regBIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_CAP_PTR 0x3fff8080180d |
| #define regBIF_CFG_DEV0_EPF6_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE 0x3fff8080180f |
| #define regBIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN 0x3fff8080180f |
| #define regBIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MIN_GRANT 0x3fff8080180f |
| #define regBIF_CFG_DEV0_EPF6_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MAX_LATENCY 0x3fff8080180f |
| #define regBIF_CFG_DEV0_EPF6_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST 0x3fff80801812 |
| #define regBIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W 0x3fff80801813 |
| #define regBIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST 0x3fff80801814 |
| #define regBIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PMI_CAP 0x3fff80801814 |
| #define regBIF_CFG_DEV0_EPF6_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL 0x3fff80801815 |
| #define regBIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_SBRN 0x3fff80801818 |
| #define regBIF_CFG_DEV0_EPF6_1_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_FLADJ 0x3fff80801818 |
| #define regBIF_CFG_DEV0_EPF6_1_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_DBESL_DBESLD 0x3fff80801818 |
| #define regBIF_CFG_DEV0_EPF6_1_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST 0x3fff80801819 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_CAP 0x3fff80801819 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_CAP 0x3fff8080181a |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL 0x3fff8080181b |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS 0x3fff8080181b |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_LINK_CAP 0x3fff8080181c |
| #define regBIF_CFG_DEV0_EPF6_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_LINK_CNTL 0x3fff8080181d |
| #define regBIF_CFG_DEV0_EPF6_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_LINK_STATUS 0x3fff8080181d |
| #define regBIF_CFG_DEV0_EPF6_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_CAP2 0x3fff80801822 |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2 0x3fff80801823 |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2 0x3fff80801823 |
| #define regBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_LINK_CAP2 0x3fff80801824 |
| #define regBIF_CFG_DEV0_EPF6_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_LINK_CNTL2 0x3fff80801825 |
| #define regBIF_CFG_DEV0_EPF6_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_LINK_STATUS2 0x3fff80801825 |
| #define regBIF_CFG_DEV0_EPF6_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST 0x3fff80801828 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL 0x3fff80801828 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO 0x3fff80801829 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI 0x3fff8080182a |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA 0x3fff8080182a |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA 0x3fff8080182a |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MASK 0x3fff8080182b |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64 0x3fff8080182b |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_64 0x3fff8080182b |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MASK_64 0x3fff8080182c |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_PENDING 0x3fff8080182c |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_PENDING_64 0x3fff8080182d |
| #define regBIF_CFG_DEV0_EPF6_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST 0x3fff80801830 |
| #define regBIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL 0x3fff80801830 |
| #define regBIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSIX_TABLE 0x3fff80801831 |
| #define regBIF_CFG_DEV0_EPF6_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_MSIX_PBA 0x3fff80801832 |
| #define regBIF_CFG_DEV0_EPF6_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_SATA_CAP_0 0x3fff80801834 |
| #define regBIF_CFG_DEV0_EPF6_1_SATA_CAP_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_SATA_CAP_1 0x3fff80801835 |
| #define regBIF_CFG_DEV0_EPF6_1_SATA_CAP_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX 0x3fff80801836 |
| #define regBIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA 0x3fff80801837 |
| #define regBIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80801840 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80801841 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1 0x3fff80801842 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2 0x3fff80801843 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80801854 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS 0x3fff80801855 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK 0x3fff80801856 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80801857 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS 0x3fff80801858 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK 0x3fff80801859 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff8080185a |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0 0x3fff8080185b |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1 0x3fff8080185c |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2 0x3fff8080185d |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3 0x3fff8080185e |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0 0x3fff80801862 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1 0x3fff80801863 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2 0x3fff80801864 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3 0x3fff80801865 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80801880 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP 0x3fff80801881 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL 0x3fff80801882 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP 0x3fff80801883 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL 0x3fff80801884 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP 0x3fff80801885 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL 0x3fff80801886 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP 0x3fff80801887 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL 0x3fff80801888 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP 0x3fff80801889 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL 0x3fff8080188a |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP 0x3fff8080188b |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL 0x3fff8080188c |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80801890 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80801891 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA 0x3fff80801892 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP 0x3fff80801893 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80801894 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP 0x3fff80801895 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80801896 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS 0x3fff80801897 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL 0x3fff80801897 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80801898 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80801898 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80801898 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80801898 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80801899 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80801899 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80801899 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80801899 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST 0x3fff808018a8 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP 0x3fff808018a9 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL 0x3fff808018a9 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST 0x3fff808018b4 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP 0x3fff808018b5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL 0x3fff808018b5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST 0x3fff808018ca |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP 0x3fff808018cb |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL 0x3fff808018cb |
| #define regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp |
| // base address: 0xfffe12107000 |
| #define regBIF_CFG_DEV0_EPF7_1_VENDOR_ID 0x3fff80801c00 |
| #define regBIF_CFG_DEV0_EPF7_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_ID 0x3fff80801c00 |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_COMMAND 0x3fff80801c01 |
| #define regBIF_CFG_DEV0_EPF7_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_STATUS 0x3fff80801c01 |
| #define regBIF_CFG_DEV0_EPF7_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_REVISION_ID 0x3fff80801c02 |
| #define regBIF_CFG_DEV0_EPF7_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PROG_INTERFACE 0x3fff80801c02 |
| #define regBIF_CFG_DEV0_EPF7_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_SUB_CLASS 0x3fff80801c02 |
| #define regBIF_CFG_DEV0_EPF7_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_CLASS 0x3fff80801c02 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_CACHE_LINE 0x3fff80801c03 |
| #define regBIF_CFG_DEV0_EPF7_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_LATENCY 0x3fff80801c03 |
| #define regBIF_CFG_DEV0_EPF7_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_HEADER 0x3fff80801c03 |
| #define regBIF_CFG_DEV0_EPF7_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_BIST 0x3fff80801c03 |
| #define regBIF_CFG_DEV0_EPF7_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_1 0x3fff80801c04 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_2 0x3fff80801c05 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_3 0x3fff80801c06 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_4 0x3fff80801c07 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_5 0x3fff80801c08 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_6 0x3fff80801c09 |
| #define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_CARDBUS_CIS_PTR 0x3fff80801c0a |
| #define regBIF_CFG_DEV0_EPF7_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_ADAPTER_ID 0x3fff80801c0b |
| #define regBIF_CFG_DEV0_EPF7_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR 0x3fff80801c0c |
| #define regBIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_CAP_PTR 0x3fff80801c0d |
| #define regBIF_CFG_DEV0_EPF7_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE 0x3fff80801c0f |
| #define regBIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN 0x3fff80801c0f |
| #define regBIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MIN_GRANT 0x3fff80801c0f |
| #define regBIF_CFG_DEV0_EPF7_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MAX_LATENCY 0x3fff80801c0f |
| #define regBIF_CFG_DEV0_EPF7_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST 0x3fff80801c12 |
| #define regBIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W 0x3fff80801c13 |
| #define regBIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST 0x3fff80801c14 |
| #define regBIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PMI_CAP 0x3fff80801c14 |
| #define regBIF_CFG_DEV0_EPF7_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL 0x3fff80801c15 |
| #define regBIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_SBRN 0x3fff80801c18 |
| #define regBIF_CFG_DEV0_EPF7_1_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_FLADJ 0x3fff80801c18 |
| #define regBIF_CFG_DEV0_EPF7_1_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_DBESL_DBESLD 0x3fff80801c18 |
| #define regBIF_CFG_DEV0_EPF7_1_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST 0x3fff80801c19 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_CAP 0x3fff80801c19 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_CAP 0x3fff80801c1a |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL 0x3fff80801c1b |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS 0x3fff80801c1b |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_LINK_CAP 0x3fff80801c1c |
| #define regBIF_CFG_DEV0_EPF7_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_LINK_CNTL 0x3fff80801c1d |
| #define regBIF_CFG_DEV0_EPF7_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_LINK_STATUS 0x3fff80801c1d |
| #define regBIF_CFG_DEV0_EPF7_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_CAP2 0x3fff80801c22 |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2 0x3fff80801c23 |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2 0x3fff80801c23 |
| #define regBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_LINK_CAP2 0x3fff80801c24 |
| #define regBIF_CFG_DEV0_EPF7_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_LINK_CNTL2 0x3fff80801c25 |
| #define regBIF_CFG_DEV0_EPF7_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_LINK_STATUS2 0x3fff80801c25 |
| #define regBIF_CFG_DEV0_EPF7_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST 0x3fff80801c28 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL 0x3fff80801c28 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO 0x3fff80801c29 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI 0x3fff80801c2a |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA 0x3fff80801c2a |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA 0x3fff80801c2a |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MASK 0x3fff80801c2b |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64 0x3fff80801c2b |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_64 0x3fff80801c2b |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MASK_64 0x3fff80801c2c |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_PENDING 0x3fff80801c2c |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_PENDING_64 0x3fff80801c2d |
| #define regBIF_CFG_DEV0_EPF7_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST 0x3fff80801c30 |
| #define regBIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL 0x3fff80801c30 |
| #define regBIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSIX_TABLE 0x3fff80801c31 |
| #define regBIF_CFG_DEV0_EPF7_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_MSIX_PBA 0x3fff80801c32 |
| #define regBIF_CFG_DEV0_EPF7_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_SATA_CAP_0 0x3fff80801c34 |
| #define regBIF_CFG_DEV0_EPF7_1_SATA_CAP_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_SATA_CAP_1 0x3fff80801c35 |
| #define regBIF_CFG_DEV0_EPF7_1_SATA_CAP_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX 0x3fff80801c36 |
| #define regBIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA 0x3fff80801c37 |
| #define regBIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80801c40 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80801c41 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1 0x3fff80801c42 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2 0x3fff80801c43 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80801c54 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS 0x3fff80801c55 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK 0x3fff80801c56 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80801c57 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS 0x3fff80801c58 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK 0x3fff80801c59 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff80801c5a |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0 0x3fff80801c5b |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1 0x3fff80801c5c |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2 0x3fff80801c5d |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3 0x3fff80801c5e |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0 0x3fff80801c62 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1 0x3fff80801c63 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2 0x3fff80801c64 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3 0x3fff80801c65 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80801c80 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP 0x3fff80801c81 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL 0x3fff80801c82 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP 0x3fff80801c83 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL 0x3fff80801c84 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP 0x3fff80801c85 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL 0x3fff80801c86 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP 0x3fff80801c87 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL 0x3fff80801c88 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP 0x3fff80801c89 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL 0x3fff80801c8a |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP 0x3fff80801c8b |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL 0x3fff80801c8c |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80801c90 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80801c91 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA 0x3fff80801c92 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP 0x3fff80801c93 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80801c94 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP 0x3fff80801c95 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80801c96 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS 0x3fff80801c97 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL 0x3fff80801c97 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80801c98 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80801c98 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80801c98 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80801c98 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80801c99 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80801c99 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80801c99 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80801c99 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST 0x3fff80801ca8 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP 0x3fff80801ca9 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL 0x3fff80801ca9 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST 0x3fff80801cb4 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP 0x3fff80801cb5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL 0x3fff80801cb5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST 0x3fff80801cca |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP 0x3fff80801ccb |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL 0x3fff80801ccb |
| #define regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp |
| // base address: 0xfffe12300000 |
| #define regBIF_CFG_DEV1_EPF0_1_VENDOR_ID 0x3fff80880000 |
| #define regBIF_CFG_DEV1_EPF0_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_ID 0x3fff80880000 |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_COMMAND 0x3fff80880001 |
| #define regBIF_CFG_DEV1_EPF0_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_STATUS 0x3fff80880001 |
| #define regBIF_CFG_DEV1_EPF0_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_REVISION_ID 0x3fff80880002 |
| #define regBIF_CFG_DEV1_EPF0_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PROG_INTERFACE 0x3fff80880002 |
| #define regBIF_CFG_DEV1_EPF0_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_SUB_CLASS 0x3fff80880002 |
| #define regBIF_CFG_DEV1_EPF0_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_CLASS 0x3fff80880002 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_CACHE_LINE 0x3fff80880003 |
| #define regBIF_CFG_DEV1_EPF0_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LATENCY 0x3fff80880003 |
| #define regBIF_CFG_DEV1_EPF0_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_HEADER 0x3fff80880003 |
| #define regBIF_CFG_DEV1_EPF0_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_BIST 0x3fff80880003 |
| #define regBIF_CFG_DEV1_EPF0_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_1 0x3fff80880004 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_2 0x3fff80880005 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_3 0x3fff80880006 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_4 0x3fff80880007 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_5 0x3fff80880008 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_6 0x3fff80880009 |
| #define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_CARDBUS_CIS_PTR 0x3fff8088000a |
| #define regBIF_CFG_DEV1_EPF0_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_ADAPTER_ID 0x3fff8088000b |
| #define regBIF_CFG_DEV1_EPF0_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR 0x3fff8088000c |
| #define regBIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_CAP_PTR 0x3fff8088000d |
| #define regBIF_CFG_DEV1_EPF0_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE 0x3fff8088000f |
| #define regBIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN 0x3fff8088000f |
| #define regBIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MIN_GRANT 0x3fff8088000f |
| #define regBIF_CFG_DEV1_EPF0_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MAX_LATENCY 0x3fff8088000f |
| #define regBIF_CFG_DEV1_EPF0_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST 0x3fff80880012 |
| #define regBIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W 0x3fff80880013 |
| #define regBIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST 0x3fff80880014 |
| #define regBIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PMI_CAP 0x3fff80880014 |
| #define regBIF_CFG_DEV1_EPF0_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL 0x3fff80880015 |
| #define regBIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_SBRN 0x3fff80880018 |
| #define regBIF_CFG_DEV1_EPF0_1_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_FLADJ 0x3fff80880018 |
| #define regBIF_CFG_DEV1_EPF0_1_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_DBESL_DBESLD 0x3fff80880018 |
| #define regBIF_CFG_DEV1_EPF0_1_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST 0x3fff80880019 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_CAP 0x3fff80880019 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_CAP 0x3fff8088001a |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL 0x3fff8088001b |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS 0x3fff8088001b |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_CAP 0x3fff8088001c |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_CNTL 0x3fff8088001d |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_STATUS 0x3fff8088001d |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_CAP2 0x3fff80880022 |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2 0x3fff80880023 |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2 0x3fff80880023 |
| #define regBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_CAP2 0x3fff80880024 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_CNTL2 0x3fff80880025 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_STATUS2 0x3fff80880025 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST 0x3fff80880028 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL 0x3fff80880028 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO 0x3fff80880029 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI 0x3fff8088002a |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA 0x3fff8088002a |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA 0x3fff8088002a |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MASK 0x3fff8088002b |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64 0x3fff8088002b |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_64 0x3fff8088002b |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MASK_64 0x3fff8088002c |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_PENDING 0x3fff8088002c |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_PENDING_64 0x3fff8088002d |
| #define regBIF_CFG_DEV1_EPF0_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST 0x3fff80880030 |
| #define regBIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL 0x3fff80880030 |
| #define regBIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSIX_TABLE 0x3fff80880031 |
| #define regBIF_CFG_DEV1_EPF0_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MSIX_PBA 0x3fff80880032 |
| #define regBIF_CFG_DEV1_EPF0_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_SATA_CAP_0 0x3fff80880034 |
| #define regBIF_CFG_DEV1_EPF0_1_SATA_CAP_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_SATA_CAP_1 0x3fff80880035 |
| #define regBIF_CFG_DEV1_EPF0_1_SATA_CAP_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX 0x3fff80880036 |
| #define regBIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA 0x3fff80880037 |
| #define regBIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80880040 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80880041 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1 0x3fff80880042 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2 0x3fff80880043 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST 0x3fff80880044 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1 0x3fff80880045 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2 0x3fff80880046 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL 0x3fff80880047 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS 0x3fff80880047 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP 0x3fff80880048 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL 0x3fff80880049 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS 0x3fff8088004a |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP 0x3fff8088004b |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL 0x3fff8088004c |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS 0x3fff8088004d |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80880054 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS 0x3fff80880055 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK 0x3fff80880056 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80880057 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS 0x3fff80880058 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK 0x3fff80880059 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff8088005a |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0 0x3fff8088005b |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1 0x3fff8088005c |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2 0x3fff8088005d |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3 0x3fff8088005e |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0 0x3fff80880062 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1 0x3fff80880063 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2 0x3fff80880064 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3 0x3fff80880065 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80880080 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP 0x3fff80880081 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL 0x3fff80880082 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP 0x3fff80880083 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL 0x3fff80880084 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP 0x3fff80880085 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL 0x3fff80880086 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP 0x3fff80880087 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL 0x3fff80880088 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP 0x3fff80880089 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL 0x3fff8088008a |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP 0x3fff8088008b |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL 0x3fff8088008c |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80880090 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80880091 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA 0x3fff80880092 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP 0x3fff80880093 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80880094 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP 0x3fff80880095 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80880096 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS 0x3fff80880097 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL 0x3fff80880097 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80880098 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80880098 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80880098 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80880098 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80880099 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80880099 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80880099 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80880099 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff8088009c |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3 0x3fff8088009d |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS 0x3fff8088009e |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff8088009f |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff8088009f |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff808800a0 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff808800a0 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff808800a1 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff808800a1 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff808800a2 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff808800a2 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff808800a3 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff808800a3 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff808800a4 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff808800a4 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff808800a5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff808800a5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff808800a6 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff808800a6 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST 0x3fff808800a8 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP 0x3fff808800a9 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL 0x3fff808800a9 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST 0x3fff808800b4 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP 0x3fff808800b5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL 0x3fff808800b5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST 0x3fff808800c8 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP 0x3fff808800c9 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST 0x3fff808800ca |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP 0x3fff808800cb |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL 0x3fff808800cb |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST 0x3fff80880100 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP 0x3fff80880101 |
| #define regBIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS 0x3fff80880102 |
| #define regBIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x3fff80880104 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_CAP_16GT 0x3fff80880105 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_CNTL_16GT 0x3fff80880106 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT 0x3fff80880107 |
| #define regBIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x3fff80880108 |
| #define regBIF_CFG_DEV1_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x3fff80880109 |
| #define regBIF_CFG_DEV1_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x3fff8088010a |
| #define regBIF_CFG_DEV1_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT 0x3fff8088010c |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT 0x3fff8088010c |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT 0x3fff8088010c |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT 0x3fff8088010c |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT 0x3fff8088010d |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT 0x3fff8088010d |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT 0x3fff8088010d |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT 0x3fff8088010d |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT 0x3fff8088010e |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT 0x3fff8088010e |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT 0x3fff8088010e |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT 0x3fff8088010e |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT 0x3fff8088010f |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT 0x3fff8088010f |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT 0x3fff8088010f |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT 0x3fff8088010f |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST 0x3fff80880114 |
| #define regBIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MARGINING_PORT_CAP 0x3fff80880115 |
| #define regBIF_CFG_DEV1_EPF0_1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS 0x3fff80880115 |
| #define regBIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL 0x3fff80880116 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS 0x3fff80880116 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL 0x3fff80880117 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS 0x3fff80880117 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL 0x3fff80880118 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS 0x3fff80880118 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL 0x3fff80880119 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS 0x3fff80880119 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL 0x3fff8088011a |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS 0x3fff8088011a |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL 0x3fff8088011b |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS 0x3fff8088011b |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL 0x3fff8088011c |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS 0x3fff8088011c |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL 0x3fff8088011d |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS 0x3fff8088011d |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL 0x3fff8088011e |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS 0x3fff8088011e |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL 0x3fff8088011f |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS 0x3fff8088011f |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL 0x3fff80880120 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS 0x3fff80880120 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL 0x3fff80880121 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS 0x3fff80880121 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL 0x3fff80880122 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS 0x3fff80880122 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL 0x3fff80880123 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS 0x3fff80880123 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL 0x3fff80880124 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS 0x3fff80880124 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL 0x3fff80880125 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS 0x3fff80880125 |
| #define regBIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp |
| // base address: 0xfffe12301000 |
| #define regBIF_CFG_DEV1_EPF1_1_VENDOR_ID 0x3fff80880400 |
| #define regBIF_CFG_DEV1_EPF1_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_ID 0x3fff80880400 |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_COMMAND 0x3fff80880401 |
| #define regBIF_CFG_DEV1_EPF1_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_STATUS 0x3fff80880401 |
| #define regBIF_CFG_DEV1_EPF1_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_REVISION_ID 0x3fff80880402 |
| #define regBIF_CFG_DEV1_EPF1_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PROG_INTERFACE 0x3fff80880402 |
| #define regBIF_CFG_DEV1_EPF1_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_SUB_CLASS 0x3fff80880402 |
| #define regBIF_CFG_DEV1_EPF1_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_CLASS 0x3fff80880402 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_CACHE_LINE 0x3fff80880403 |
| #define regBIF_CFG_DEV1_EPF1_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_LATENCY 0x3fff80880403 |
| #define regBIF_CFG_DEV1_EPF1_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_HEADER 0x3fff80880403 |
| #define regBIF_CFG_DEV1_EPF1_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_BIST 0x3fff80880403 |
| #define regBIF_CFG_DEV1_EPF1_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_1 0x3fff80880404 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_2 0x3fff80880405 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_3 0x3fff80880406 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_4 0x3fff80880407 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_5 0x3fff80880408 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_6 0x3fff80880409 |
| #define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_CARDBUS_CIS_PTR 0x3fff8088040a |
| #define regBIF_CFG_DEV1_EPF1_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_ADAPTER_ID 0x3fff8088040b |
| #define regBIF_CFG_DEV1_EPF1_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR 0x3fff8088040c |
| #define regBIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_CAP_PTR 0x3fff8088040d |
| #define regBIF_CFG_DEV1_EPF1_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE 0x3fff8088040f |
| #define regBIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN 0x3fff8088040f |
| #define regBIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MIN_GRANT 0x3fff8088040f |
| #define regBIF_CFG_DEV1_EPF1_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MAX_LATENCY 0x3fff8088040f |
| #define regBIF_CFG_DEV1_EPF1_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST 0x3fff80880412 |
| #define regBIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W 0x3fff80880413 |
| #define regBIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST 0x3fff80880414 |
| #define regBIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PMI_CAP 0x3fff80880414 |
| #define regBIF_CFG_DEV1_EPF1_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL 0x3fff80880415 |
| #define regBIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_SBRN 0x3fff80880418 |
| #define regBIF_CFG_DEV1_EPF1_1_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_FLADJ 0x3fff80880418 |
| #define regBIF_CFG_DEV1_EPF1_1_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_DBESL_DBESLD 0x3fff80880418 |
| #define regBIF_CFG_DEV1_EPF1_1_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST 0x3fff80880419 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_CAP 0x3fff80880419 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_CAP 0x3fff8088041a |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL 0x3fff8088041b |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS 0x3fff8088041b |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_LINK_CAP 0x3fff8088041c |
| #define regBIF_CFG_DEV1_EPF1_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_LINK_CNTL 0x3fff8088041d |
| #define regBIF_CFG_DEV1_EPF1_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_LINK_STATUS 0x3fff8088041d |
| #define regBIF_CFG_DEV1_EPF1_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_CAP2 0x3fff80880422 |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2 0x3fff80880423 |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2 0x3fff80880423 |
| #define regBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_LINK_CAP2 0x3fff80880424 |
| #define regBIF_CFG_DEV1_EPF1_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_LINK_CNTL2 0x3fff80880425 |
| #define regBIF_CFG_DEV1_EPF1_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_LINK_STATUS2 0x3fff80880425 |
| #define regBIF_CFG_DEV1_EPF1_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST 0x3fff80880428 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL 0x3fff80880428 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO 0x3fff80880429 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI 0x3fff8088042a |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA 0x3fff8088042a |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA 0x3fff8088042a |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MASK 0x3fff8088042b |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64 0x3fff8088042b |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_64 0x3fff8088042b |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MASK_64 0x3fff8088042c |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_PENDING 0x3fff8088042c |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_PENDING_64 0x3fff8088042d |
| #define regBIF_CFG_DEV1_EPF1_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST 0x3fff80880430 |
| #define regBIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL 0x3fff80880430 |
| #define regBIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSIX_TABLE 0x3fff80880431 |
| #define regBIF_CFG_DEV1_EPF1_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_MSIX_PBA 0x3fff80880432 |
| #define regBIF_CFG_DEV1_EPF1_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_SATA_CAP_0 0x3fff80880434 |
| #define regBIF_CFG_DEV1_EPF1_1_SATA_CAP_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_SATA_CAP_1 0x3fff80880435 |
| #define regBIF_CFG_DEV1_EPF1_1_SATA_CAP_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX 0x3fff80880436 |
| #define regBIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA 0x3fff80880437 |
| #define regBIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80880440 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80880441 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1 0x3fff80880442 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2 0x3fff80880443 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80880454 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS 0x3fff80880455 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK 0x3fff80880456 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80880457 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS 0x3fff80880458 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK 0x3fff80880459 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff8088045a |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0 0x3fff8088045b |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1 0x3fff8088045c |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2 0x3fff8088045d |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3 0x3fff8088045e |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0 0x3fff80880462 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1 0x3fff80880463 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2 0x3fff80880464 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3 0x3fff80880465 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80880480 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP 0x3fff80880481 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL 0x3fff80880482 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP 0x3fff80880483 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL 0x3fff80880484 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP 0x3fff80880485 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL 0x3fff80880486 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP 0x3fff80880487 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL 0x3fff80880488 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP 0x3fff80880489 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL 0x3fff8088048a |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP 0x3fff8088048b |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL 0x3fff8088048c |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80880490 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80880491 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA 0x3fff80880492 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP 0x3fff80880493 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80880494 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP 0x3fff80880495 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80880496 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS 0x3fff80880497 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL 0x3fff80880497 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80880498 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80880498 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80880498 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80880498 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80880499 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80880499 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80880499 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80880499 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST 0x3fff808804a8 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP 0x3fff808804a9 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL 0x3fff808804a9 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST 0x3fff808804b4 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP 0x3fff808804b5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL 0x3fff808804b5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST 0x3fff808804ca |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP 0x3fff808804cb |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL 0x3fff808804cb |
| #define regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev2_epf0_bifcfgdecp |
| // base address: 0xfffe12500000 |
| #define regBIF_CFG_DEV2_EPF0_1_VENDOR_ID 0x3fff80900000 |
| #define regBIF_CFG_DEV2_EPF0_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_ID 0x3fff80900000 |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_COMMAND 0x3fff80900001 |
| #define regBIF_CFG_DEV2_EPF0_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_STATUS 0x3fff80900001 |
| #define regBIF_CFG_DEV2_EPF0_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_REVISION_ID 0x3fff80900002 |
| #define regBIF_CFG_DEV2_EPF0_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PROG_INTERFACE 0x3fff80900002 |
| #define regBIF_CFG_DEV2_EPF0_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_SUB_CLASS 0x3fff80900002 |
| #define regBIF_CFG_DEV2_EPF0_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_CLASS 0x3fff80900002 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_CACHE_LINE 0x3fff80900003 |
| #define regBIF_CFG_DEV2_EPF0_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LATENCY 0x3fff80900003 |
| #define regBIF_CFG_DEV2_EPF0_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_HEADER 0x3fff80900003 |
| #define regBIF_CFG_DEV2_EPF0_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_BIST 0x3fff80900003 |
| #define regBIF_CFG_DEV2_EPF0_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_1 0x3fff80900004 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_2 0x3fff80900005 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_3 0x3fff80900006 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_4 0x3fff80900007 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_5 0x3fff80900008 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_6 0x3fff80900009 |
| #define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_CARDBUS_CIS_PTR 0x3fff8090000a |
| #define regBIF_CFG_DEV2_EPF0_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_ADAPTER_ID 0x3fff8090000b |
| #define regBIF_CFG_DEV2_EPF0_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_ROM_BASE_ADDR 0x3fff8090000c |
| #define regBIF_CFG_DEV2_EPF0_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_CAP_PTR 0x3fff8090000d |
| #define regBIF_CFG_DEV2_EPF0_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_INTERRUPT_LINE 0x3fff8090000f |
| #define regBIF_CFG_DEV2_EPF0_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_INTERRUPT_PIN 0x3fff8090000f |
| #define regBIF_CFG_DEV2_EPF0_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MIN_GRANT 0x3fff8090000f |
| #define regBIF_CFG_DEV2_EPF0_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MAX_LATENCY 0x3fff8090000f |
| #define regBIF_CFG_DEV2_EPF0_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST 0x3fff80900012 |
| #define regBIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W 0x3fff80900013 |
| #define regBIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST 0x3fff80900014 |
| #define regBIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PMI_CAP 0x3fff80900014 |
| #define regBIF_CFG_DEV2_EPF0_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL 0x3fff80900015 |
| #define regBIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST 0x3fff80900019 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_CAP 0x3fff80900019 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_CAP 0x3fff8090001a |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_CNTL 0x3fff8090001b |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_STATUS 0x3fff8090001b |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_CAP 0x3fff8090001c |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_CNTL 0x3fff8090001d |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_STATUS 0x3fff8090001d |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_CAP2 0x3fff80900022 |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2 0x3fff80900023 |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_STATUS2 0x3fff80900023 |
| #define regBIF_CFG_DEV2_EPF0_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_CAP2 0x3fff80900024 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_CNTL2 0x3fff80900025 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_STATUS2 0x3fff80900025 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST 0x3fff80900028 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL 0x3fff80900028 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_LO 0x3fff80900029 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_HI 0x3fff8090002a |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA 0x3fff8090002a |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA 0x3fff8090002a |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MASK 0x3fff8090002b |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_64 0x3fff8090002b |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_64 0x3fff8090002b |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MASK_64 0x3fff8090002c |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_PENDING 0x3fff8090002c |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_PENDING_64 0x3fff8090002d |
| #define regBIF_CFG_DEV2_EPF0_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST 0x3fff80900030 |
| #define regBIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL 0x3fff80900030 |
| #define regBIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSIX_TABLE 0x3fff80900031 |
| #define regBIF_CFG_DEV2_EPF0_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MSIX_PBA 0x3fff80900032 |
| #define regBIF_CFG_DEV2_EPF0_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80900040 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80900041 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC1 0x3fff80900042 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC2 0x3fff80900043 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST 0x3fff80900044 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1 0x3fff80900045 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2 0x3fff80900046 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL 0x3fff80900047 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_STATUS 0x3fff80900047 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP 0x3fff80900048 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL 0x3fff80900049 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS 0x3fff8090004a |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP 0x3fff8090004b |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL 0x3fff8090004c |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS 0x3fff8090004d |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80900054 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS 0x3fff80900055 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK 0x3fff80900056 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80900057 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS 0x3fff80900058 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK 0x3fff80900059 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff8090005a |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG0 0x3fff8090005b |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG1 0x3fff8090005c |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG2 0x3fff8090005d |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG3 0x3fff8090005e |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG0 0x3fff80900062 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG1 0x3fff80900063 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG2 0x3fff80900064 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG3 0x3fff80900065 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80900080 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CAP 0x3fff80900081 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL 0x3fff80900082 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CAP 0x3fff80900083 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL 0x3fff80900084 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CAP 0x3fff80900085 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL 0x3fff80900086 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CAP 0x3fff80900087 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL 0x3fff80900088 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CAP 0x3fff80900089 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL 0x3fff8090008a |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CAP 0x3fff8090008b |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL 0x3fff8090008c |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80900090 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80900091 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA 0x3fff80900092 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_CAP 0x3fff80900093 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80900094 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP 0x3fff80900095 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80900096 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS 0x3fff80900097 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_CNTL 0x3fff80900097 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80900098 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80900098 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80900098 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80900098 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80900099 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80900099 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80900099 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80900099 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST 0x3fff8090009c |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3 0x3fff8090009d |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_ERROR_STATUS 0x3fff8090009e |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_ERROR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0x3fff8090009f |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0x3fff8090009f |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0x3fff809000a0 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0x3fff809000a0 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0x3fff809000a1 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0x3fff809000a1 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0x3fff809000a2 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0x3fff809000a2 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0x3fff809000a3 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0x3fff809000a3 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0x3fff809000a4 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0x3fff809000a4 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0x3fff809000a5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0x3fff809000a5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0x3fff809000a6 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0x3fff809000a6 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST 0x3fff809000a8 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP 0x3fff809000a9 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL 0x3fff809000a9 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST 0x3fff809000b4 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP 0x3fff809000b5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL 0x3fff809000b5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST 0x3fff809000c8 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP 0x3fff809000c9 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST 0x3fff809000ca |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP 0x3fff809000cb |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL 0x3fff809000cb |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST 0x3fff80900100 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP 0x3fff80900101 |
| #define regBIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS 0x3fff80900102 |
| #define regBIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0x3fff80900104 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_CAP_16GT 0x3fff80900105 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_CAP_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_CNTL_16GT 0x3fff80900106 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT 0x3fff80900107 |
| #define regBIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x3fff80900108 |
| #define regBIF_CFG_DEV2_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0x3fff80900109 |
| #define regBIF_CFG_DEV2_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0x3fff8090010a |
| #define regBIF_CFG_DEV2_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT 0x3fff8090010c |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT 0x3fff8090010c |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT 0x3fff8090010c |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT 0x3fff8090010c |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT 0x3fff8090010d |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT 0x3fff8090010d |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT 0x3fff8090010d |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT 0x3fff8090010d |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT 0x3fff8090010e |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT 0x3fff8090010e |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT 0x3fff8090010e |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT 0x3fff8090010e |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT 0x3fff8090010f |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT 0x3fff8090010f |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT 0x3fff8090010f |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT 0x3fff8090010f |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST 0x3fff80900114 |
| #define regBIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MARGINING_PORT_CAP 0x3fff80900115 |
| #define regBIF_CFG_DEV2_EPF0_1_MARGINING_PORT_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS 0x3fff80900115 |
| #define regBIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL 0x3fff80900116 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS 0x3fff80900116 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL 0x3fff80900117 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS 0x3fff80900117 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL 0x3fff80900118 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS 0x3fff80900118 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL 0x3fff80900119 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS 0x3fff80900119 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL 0x3fff8090011a |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS 0x3fff8090011a |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL 0x3fff8090011b |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS 0x3fff8090011b |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL 0x3fff8090011c |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS 0x3fff8090011c |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL 0x3fff8090011d |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS 0x3fff8090011d |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL 0x3fff8090011e |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS 0x3fff8090011e |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL 0x3fff8090011f |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS 0x3fff8090011f |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL 0x3fff80900120 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS 0x3fff80900120 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL 0x3fff80900121 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS 0x3fff80900121 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL 0x3fff80900122 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS 0x3fff80900122 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL 0x3fff80900123 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS 0x3fff80900123 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL 0x3fff80900124 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS 0x3fff80900124 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL 0x3fff80900125 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS 0x3fff80900125 |
| #define regBIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev2_epf1_bifcfgdecp |
| // base address: 0xfffe12501000 |
| #define regBIF_CFG_DEV2_EPF1_1_VENDOR_ID 0x3fff80900400 |
| #define regBIF_CFG_DEV2_EPF1_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_ID 0x3fff80900400 |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_COMMAND 0x3fff80900401 |
| #define regBIF_CFG_DEV2_EPF1_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_STATUS 0x3fff80900401 |
| #define regBIF_CFG_DEV2_EPF1_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_REVISION_ID 0x3fff80900402 |
| #define regBIF_CFG_DEV2_EPF1_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PROG_INTERFACE 0x3fff80900402 |
| #define regBIF_CFG_DEV2_EPF1_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_SUB_CLASS 0x3fff80900402 |
| #define regBIF_CFG_DEV2_EPF1_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_CLASS 0x3fff80900402 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_CACHE_LINE 0x3fff80900403 |
| #define regBIF_CFG_DEV2_EPF1_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_LATENCY 0x3fff80900403 |
| #define regBIF_CFG_DEV2_EPF1_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_HEADER 0x3fff80900403 |
| #define regBIF_CFG_DEV2_EPF1_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_BIST 0x3fff80900403 |
| #define regBIF_CFG_DEV2_EPF1_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_1 0x3fff80900404 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_2 0x3fff80900405 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_3 0x3fff80900406 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_4 0x3fff80900407 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_5 0x3fff80900408 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_6 0x3fff80900409 |
| #define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_CARDBUS_CIS_PTR 0x3fff8090040a |
| #define regBIF_CFG_DEV2_EPF1_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_ADAPTER_ID 0x3fff8090040b |
| #define regBIF_CFG_DEV2_EPF1_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_ROM_BASE_ADDR 0x3fff8090040c |
| #define regBIF_CFG_DEV2_EPF1_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_CAP_PTR 0x3fff8090040d |
| #define regBIF_CFG_DEV2_EPF1_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_INTERRUPT_LINE 0x3fff8090040f |
| #define regBIF_CFG_DEV2_EPF1_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_INTERRUPT_PIN 0x3fff8090040f |
| #define regBIF_CFG_DEV2_EPF1_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MIN_GRANT 0x3fff8090040f |
| #define regBIF_CFG_DEV2_EPF1_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MAX_LATENCY 0x3fff8090040f |
| #define regBIF_CFG_DEV2_EPF1_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST 0x3fff80900412 |
| #define regBIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W 0x3fff80900413 |
| #define regBIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST 0x3fff80900414 |
| #define regBIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PMI_CAP 0x3fff80900414 |
| #define regBIF_CFG_DEV2_EPF1_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL 0x3fff80900415 |
| #define regBIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_SBRN 0x3fff80900418 |
| #define regBIF_CFG_DEV2_EPF1_1_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_FLADJ 0x3fff80900418 |
| #define regBIF_CFG_DEV2_EPF1_1_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_DBESL_DBESLD 0x3fff80900418 |
| #define regBIF_CFG_DEV2_EPF1_1_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST 0x3fff80900419 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_CAP 0x3fff80900419 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_CAP 0x3fff8090041a |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_CNTL 0x3fff8090041b |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_STATUS 0x3fff8090041b |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_LINK_CAP 0x3fff8090041c |
| #define regBIF_CFG_DEV2_EPF1_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_LINK_CNTL 0x3fff8090041d |
| #define regBIF_CFG_DEV2_EPF1_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_LINK_STATUS 0x3fff8090041d |
| #define regBIF_CFG_DEV2_EPF1_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_CAP2 0x3fff80900422 |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2 0x3fff80900423 |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_STATUS2 0x3fff80900423 |
| #define regBIF_CFG_DEV2_EPF1_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_LINK_CAP2 0x3fff80900424 |
| #define regBIF_CFG_DEV2_EPF1_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_LINK_CNTL2 0x3fff80900425 |
| #define regBIF_CFG_DEV2_EPF1_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_LINK_STATUS2 0x3fff80900425 |
| #define regBIF_CFG_DEV2_EPF1_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST 0x3fff80900428 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL 0x3fff80900428 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_LO 0x3fff80900429 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_HI 0x3fff8090042a |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA 0x3fff8090042a |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA 0x3fff8090042a |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MASK 0x3fff8090042b |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_64 0x3fff8090042b |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_64 0x3fff8090042b |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MASK_64 0x3fff8090042c |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_PENDING 0x3fff8090042c |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_PENDING_64 0x3fff8090042d |
| #define regBIF_CFG_DEV2_EPF1_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST 0x3fff80900430 |
| #define regBIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL 0x3fff80900430 |
| #define regBIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSIX_TABLE 0x3fff80900431 |
| #define regBIF_CFG_DEV2_EPF1_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_MSIX_PBA 0x3fff80900432 |
| #define regBIF_CFG_DEV2_EPF1_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80900440 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80900441 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC1 0x3fff80900442 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC2 0x3fff80900443 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80900454 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS 0x3fff80900455 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK 0x3fff80900456 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80900457 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS 0x3fff80900458 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK 0x3fff80900459 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff8090045a |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG0 0x3fff8090045b |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG1 0x3fff8090045c |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG2 0x3fff8090045d |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG3 0x3fff8090045e |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG0 0x3fff80900462 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG1 0x3fff80900463 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG2 0x3fff80900464 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG3 0x3fff80900465 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80900480 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CAP 0x3fff80900481 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL 0x3fff80900482 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CAP 0x3fff80900483 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL 0x3fff80900484 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CAP 0x3fff80900485 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL 0x3fff80900486 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CAP 0x3fff80900487 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL 0x3fff80900488 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CAP 0x3fff80900489 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL 0x3fff8090048a |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CAP 0x3fff8090048b |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL 0x3fff8090048c |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80900490 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80900491 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA 0x3fff80900492 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_CAP 0x3fff80900493 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80900494 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP 0x3fff80900495 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80900496 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS 0x3fff80900497 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_CNTL 0x3fff80900497 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80900498 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80900498 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80900498 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80900498 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80900499 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80900499 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80900499 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80900499 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST 0x3fff809004a8 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP 0x3fff809004a9 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL 0x3fff809004a9 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST 0x3fff809004b4 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP 0x3fff809004b5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL 0x3fff809004b5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST 0x3fff809004ca |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP 0x3fff809004cb |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL 0x3fff809004cb |
| #define regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev2_epf2_bifcfgdecp |
| // base address: 0xfffe12502000 |
| #define regBIF_CFG_DEV2_EPF2_1_VENDOR_ID 0x3fff80900800 |
| #define regBIF_CFG_DEV2_EPF2_1_VENDOR_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_ID 0x3fff80900800 |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_COMMAND 0x3fff80900801 |
| #define regBIF_CFG_DEV2_EPF2_1_COMMAND_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_STATUS 0x3fff80900801 |
| #define regBIF_CFG_DEV2_EPF2_1_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_REVISION_ID 0x3fff80900802 |
| #define regBIF_CFG_DEV2_EPF2_1_REVISION_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PROG_INTERFACE 0x3fff80900802 |
| #define regBIF_CFG_DEV2_EPF2_1_PROG_INTERFACE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_SUB_CLASS 0x3fff80900802 |
| #define regBIF_CFG_DEV2_EPF2_1_SUB_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_CLASS 0x3fff80900802 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_CLASS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_CACHE_LINE 0x3fff80900803 |
| #define regBIF_CFG_DEV2_EPF2_1_CACHE_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_LATENCY 0x3fff80900803 |
| #define regBIF_CFG_DEV2_EPF2_1_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_HEADER 0x3fff80900803 |
| #define regBIF_CFG_DEV2_EPF2_1_HEADER_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_BIST 0x3fff80900803 |
| #define regBIF_CFG_DEV2_EPF2_1_BIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_1 0x3fff80900804 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_2 0x3fff80900805 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_3 0x3fff80900806 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_4 0x3fff80900807 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_5 0x3fff80900808 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_6 0x3fff80900809 |
| #define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_CARDBUS_CIS_PTR 0x3fff8090080a |
| #define regBIF_CFG_DEV2_EPF2_1_CARDBUS_CIS_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_ADAPTER_ID 0x3fff8090080b |
| #define regBIF_CFG_DEV2_EPF2_1_ADAPTER_ID_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_ROM_BASE_ADDR 0x3fff8090080c |
| #define regBIF_CFG_DEV2_EPF2_1_ROM_BASE_ADDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_CAP_PTR 0x3fff8090080d |
| #define regBIF_CFG_DEV2_EPF2_1_CAP_PTR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_INTERRUPT_LINE 0x3fff8090080f |
| #define regBIF_CFG_DEV2_EPF2_1_INTERRUPT_LINE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_INTERRUPT_PIN 0x3fff8090080f |
| #define regBIF_CFG_DEV2_EPF2_1_INTERRUPT_PIN_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MIN_GRANT 0x3fff8090080f |
| #define regBIF_CFG_DEV2_EPF2_1_MIN_GRANT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MAX_LATENCY 0x3fff8090080f |
| #define regBIF_CFG_DEV2_EPF2_1_MAX_LATENCY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST 0x3fff80900812 |
| #define regBIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W 0x3fff80900813 |
| #define regBIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST 0x3fff80900814 |
| #define regBIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PMI_CAP 0x3fff80900814 |
| #define regBIF_CFG_DEV2_EPF2_1_PMI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL 0x3fff80900815 |
| #define regBIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_SBRN 0x3fff80900818 |
| #define regBIF_CFG_DEV2_EPF2_1_SBRN_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_FLADJ 0x3fff80900818 |
| #define regBIF_CFG_DEV2_EPF2_1_FLADJ_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_DBESL_DBESLD 0x3fff80900818 |
| #define regBIF_CFG_DEV2_EPF2_1_DBESL_DBESLD_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST 0x3fff80900819 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_CAP 0x3fff80900819 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_CAP 0x3fff8090081a |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_CNTL 0x3fff8090081b |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_STATUS 0x3fff8090081b |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_LINK_CAP 0x3fff8090081c |
| #define regBIF_CFG_DEV2_EPF2_1_LINK_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_LINK_CNTL 0x3fff8090081d |
| #define regBIF_CFG_DEV2_EPF2_1_LINK_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_LINK_STATUS 0x3fff8090081d |
| #define regBIF_CFG_DEV2_EPF2_1_LINK_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_CAP2 0x3fff80900822 |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2 0x3fff80900823 |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_STATUS2 0x3fff80900823 |
| #define regBIF_CFG_DEV2_EPF2_1_DEVICE_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_LINK_CAP2 0x3fff80900824 |
| #define regBIF_CFG_DEV2_EPF2_1_LINK_CAP2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_LINK_CNTL2 0x3fff80900825 |
| #define regBIF_CFG_DEV2_EPF2_1_LINK_CNTL2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_LINK_STATUS2 0x3fff80900825 |
| #define regBIF_CFG_DEV2_EPF2_1_LINK_STATUS2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST 0x3fff80900828 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL 0x3fff80900828 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_LO 0x3fff80900829 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_LO_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_HI 0x3fff8090082a |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_HI_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA 0x3fff8090082a |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA 0x3fff8090082a |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MASK 0x3fff8090082b |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_64 0x3fff8090082b |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_64 0x3fff8090082b |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MASK_64 0x3fff8090082c |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_MASK_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_PENDING 0x3fff8090082c |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_PENDING_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_PENDING_64 0x3fff8090082d |
| #define regBIF_CFG_DEV2_EPF2_1_MSI_PENDING_64_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST 0x3fff80900830 |
| #define regBIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL 0x3fff80900830 |
| #define regBIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSIX_TABLE 0x3fff80900831 |
| #define regBIF_CFG_DEV2_EPF2_1_MSIX_TABLE_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_MSIX_PBA 0x3fff80900832 |
| #define regBIF_CFG_DEV2_EPF2_1_MSIX_PBA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3fff80900840 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR 0x3fff80900841 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC1 0x3fff80900842 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC2 0x3fff80900843 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3fff80900854 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS 0x3fff80900855 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK 0x3fff80900856 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY 0x3fff80900857 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS 0x3fff80900858 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK 0x3fff80900859 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL 0x3fff8090085a |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG0 0x3fff8090085b |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG1 0x3fff8090085c |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG2 0x3fff8090085d |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG3 0x3fff8090085e |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG0 0x3fff80900862 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG1 0x3fff80900863 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG2 0x3fff80900864 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG3 0x3fff80900865 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST 0x3fff80900880 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CAP 0x3fff80900881 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL 0x3fff80900882 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CAP 0x3fff80900883 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL 0x3fff80900884 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CAP 0x3fff80900885 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL 0x3fff80900886 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CAP 0x3fff80900887 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL 0x3fff80900888 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CAP 0x3fff80900889 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL 0x3fff8090088a |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CAP 0x3fff8090088b |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL 0x3fff8090088c |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x3fff80900890 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT 0x3fff80900891 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA 0x3fff80900892 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_CAP 0x3fff80900893 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST 0x3fff80900894 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP 0x3fff80900895 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_LATENCY_INDICATOR 0x3fff80900896 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS 0x3fff80900897 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_CNTL 0x3fff80900897 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x3fff80900898 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x3fff80900898 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x3fff80900898 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x3fff80900898 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x3fff80900899 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x3fff80900899 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x3fff80900899 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x3fff80900899 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST 0x3fff809008a8 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP 0x3fff809008a9 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL 0x3fff809008a9 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST 0x3fff809008b4 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP 0x3fff809008b5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL 0x3fff809008b5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST 0x3fff809008ca |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP 0x3fff809008cb |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP_BASE_IDX 5 |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL 0x3fff809008cb |
| #define regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL_BASE_IDX 5 |
| |
| |
| #endif |