| /* |
| * Copyright 2023 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| */ |
| #ifndef _vcn_5_0_0_OFFSET_HEADER |
| #define _vcn_5_0_0_OFFSET_HEADER |
| |
| |
| |
| // addressBlock: uvd_uvddec |
| // base address: 0x1fc00 |
| #define regUVD_TOP_CTRL 0x0100 |
| #define regUVD_TOP_CTRL_BASE_IDX 1 |
| #define regUVD_CGC_GATE 0x0101 |
| #define regUVD_CGC_GATE_BASE_IDX 1 |
| #define regUVD_CGC_CTRL 0x0102 |
| #define regUVD_CGC_CTRL_BASE_IDX 1 |
| #define regAVM_SUVD_CGC_GATE 0x0104 |
| #define regAVM_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regEFC_SUVD_CGC_GATE 0x0104 |
| #define regEFC_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regENT_SUVD_CGC_GATE 0x0104 |
| #define regENT_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regIME_SUVD_CGC_GATE 0x0104 |
| #define regIME_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regPPU_SUVD_CGC_GATE 0x0104 |
| #define regPPU_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regSAOE_SUVD_CGC_GATE 0x0104 |
| #define regSAOE_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regSCM_SUVD_CGC_GATE 0x0104 |
| #define regSCM_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regSDB_SUVD_CGC_GATE 0x0104 |
| #define regSDB_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regSIT0_NXT_SUVD_CGC_GATE 0x0104 |
| #define regSIT0_NXT_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regSIT1_NXT_SUVD_CGC_GATE 0x0104 |
| #define regSIT1_NXT_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regSIT2_NXT_SUVD_CGC_GATE 0x0104 |
| #define regSIT2_NXT_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regSIT_SUVD_CGC_GATE 0x0104 |
| #define regSIT_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regSMPA_SUVD_CGC_GATE 0x0104 |
| #define regSMPA_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regSMP_SUVD_CGC_GATE 0x0104 |
| #define regSMP_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regSRE_SUVD_CGC_GATE 0x0104 |
| #define regSRE_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regUVD_SUVD_CGC_GATE 0x0104 |
| #define regUVD_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regAVM_SUVD_CGC_GATE2 0x0105 |
| #define regAVM_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regDBR_SUVD_CGC_GATE2 0x0105 |
| #define regDBR_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regENT_SUVD_CGC_GATE2 0x0105 |
| #define regENT_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regIME_SUVD_CGC_GATE2 0x0105 |
| #define regIME_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regSAOE_SUVD_CGC_GATE2 0x0105 |
| #define regSAOE_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regSDB_SUVD_CGC_GATE2 0x0105 |
| #define regSDB_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regSIT0_NXT_SUVD_CGC_GATE2 0x0105 |
| #define regSIT0_NXT_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regSIT1_NXT_SUVD_CGC_GATE2 0x0105 |
| #define regSIT1_NXT_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regSIT2_NXT_SUVD_CGC_GATE2 0x0105 |
| #define regSIT2_NXT_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regSIT_SUVD_CGC_GATE2 0x0105 |
| #define regSIT_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regSMPA_SUVD_CGC_GATE2 0x0105 |
| #define regSMPA_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regSMP_SUVD_CGC_GATE2 0x0105 |
| #define regSMP_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regSRE_SUVD_CGC_GATE2 0x0105 |
| #define regSRE_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regUVD_SUVD_CGC_GATE2 0x0105 |
| #define regUVD_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regAVM_SUVD_CGC_CTRL 0x0106 |
| #define regAVM_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regDBR_SUVD_CGC_CTRL 0x0106 |
| #define regDBR_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regEFC_SUVD_CGC_CTRL 0x0106 |
| #define regEFC_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regENT_SUVD_CGC_CTRL 0x0106 |
| #define regENT_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regIME_SUVD_CGC_CTRL 0x0106 |
| #define regIME_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regPPU_SUVD_CGC_CTRL 0x0106 |
| #define regPPU_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regSAOE_SUVD_CGC_CTRL 0x0106 |
| #define regSAOE_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regSCM_SUVD_CGC_CTRL 0x0106 |
| #define regSCM_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regSDB_SUVD_CGC_CTRL 0x0106 |
| #define regSDB_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regSIT0_NXT_SUVD_CGC_CTRL 0x0106 |
| #define regSIT0_NXT_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regSIT1_NXT_SUVD_CGC_CTRL 0x0106 |
| #define regSIT1_NXT_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regSIT2_NXT_SUVD_CGC_CTRL 0x0106 |
| #define regSIT2_NXT_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regSIT_SUVD_CGC_CTRL 0x0106 |
| #define regSIT_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regSMPA_SUVD_CGC_CTRL 0x0106 |
| #define regSMPA_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regSMP_SUVD_CGC_CTRL 0x0106 |
| #define regSMP_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regSRE_SUVD_CGC_CTRL 0x0106 |
| #define regSRE_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regUVD_SUVD_CGC_CTRL 0x0106 |
| #define regUVD_SUVD_CGC_CTRL_BASE_IDX 1 |
| #define regUVD_CGC_CTRL3 0x010a |
| #define regUVD_CGC_CTRL3_BASE_IDX 1 |
| #define regUVD_GPCOM_VCPU_DATA0 0x0110 |
| #define regUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 |
| #define regUVD_GPCOM_VCPU_DATA1 0x0111 |
| #define regUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 |
| #define regUVD_GPCOM_SYS_CMD 0x0112 |
| #define regUVD_GPCOM_SYS_CMD_BASE_IDX 1 |
| #define regUVD_GPCOM_SYS_DATA0 0x0113 |
| #define regUVD_GPCOM_SYS_DATA0_BASE_IDX 1 |
| #define regUVD_GPCOM_SYS_DATA1 0x0114 |
| #define regUVD_GPCOM_SYS_DATA1_BASE_IDX 1 |
| #define regUVD_VCPU_INT_EN 0x0115 |
| #define regUVD_VCPU_INT_EN_BASE_IDX 1 |
| #define regUVD_VCPU_INT_STATUS 0x0116 |
| #define regUVD_VCPU_INT_STATUS_BASE_IDX 1 |
| #define regUVD_VCPU_INT_ACK 0x0117 |
| #define regUVD_VCPU_INT_ACK_BASE_IDX 1 |
| #define regUVD_VCPU_INT_ROUTE 0x0118 |
| #define regUVD_VCPU_INT_ROUTE_BASE_IDX 1 |
| #define regUVD_DRV_FW_MSG 0x0119 |
| #define regUVD_DRV_FW_MSG_BASE_IDX 1 |
| #define regUVD_FW_DRV_MSG_ACK 0x011a |
| #define regUVD_FW_DRV_MSG_ACK_BASE_IDX 1 |
| #define regUVD_SUVD_INT_EN 0x011b |
| #define regUVD_SUVD_INT_EN_BASE_IDX 1 |
| #define regUVD_SUVD_INT_STATUS 0x011c |
| #define regUVD_SUVD_INT_STATUS_BASE_IDX 1 |
| #define regUVD_SUVD_INT_ACK 0x011d |
| #define regUVD_SUVD_INT_ACK_BASE_IDX 1 |
| #define regUVD_ENC_VCPU_INT_EN 0x011e |
| #define regUVD_ENC_VCPU_INT_EN_BASE_IDX 1 |
| #define regUVD_ENC_VCPU_INT_STATUS 0x011f |
| #define regUVD_ENC_VCPU_INT_STATUS_BASE_IDX 1 |
| #define regUVD_ENC_VCPU_INT_ACK 0x0120 |
| #define regUVD_ENC_VCPU_INT_ACK_BASE_IDX 1 |
| #define regUVD_MASTINT_EN 0x0121 |
| #define regUVD_MASTINT_EN_BASE_IDX 1 |
| #define regUVD_SYS_INT_EN 0x0122 |
| #define regUVD_SYS_INT_EN_BASE_IDX 1 |
| #define regUVD_SYS_INT_STATUS 0x0123 |
| #define regUVD_SYS_INT_STATUS_BASE_IDX 1 |
| #define regUVD_SYS_INT_ACK 0x0124 |
| #define regUVD_SYS_INT_ACK_BASE_IDX 1 |
| #define regUVD_JOB_DONE 0x0125 |
| #define regUVD_JOB_DONE_BASE_IDX 1 |
| #define regUVD_CBUF_ID 0x0126 |
| #define regUVD_CBUF_ID_BASE_IDX 1 |
| #define regUVD_CONTEXT_ID 0x0127 |
| #define regUVD_CONTEXT_ID_BASE_IDX 1 |
| #define regUVD_CONTEXT_ID2 0x0128 |
| #define regUVD_CONTEXT_ID2_BASE_IDX 1 |
| #define regUVD_NO_OP 0x0129 |
| #define regUVD_NO_OP_BASE_IDX 1 |
| #define regUVD_RB_BASE_LO 0x012a |
| #define regUVD_RB_BASE_LO_BASE_IDX 1 |
| #define regUVD_RB_BASE_HI 0x012b |
| #define regUVD_RB_BASE_HI_BASE_IDX 1 |
| #define regUVD_RB_SIZE 0x012c |
| #define regUVD_RB_SIZE_BASE_IDX 1 |
| #define regUVD_RB_BASE_LO2 0x012f |
| #define regUVD_RB_BASE_LO2_BASE_IDX 1 |
| #define regUVD_RB_BASE_HI2 0x0130 |
| #define regUVD_RB_BASE_HI2_BASE_IDX 1 |
| #define regUVD_RB_SIZE2 0x0131 |
| #define regUVD_RB_SIZE2_BASE_IDX 1 |
| #define regUVD_RB_BASE_LO3 0x0134 |
| #define regUVD_RB_BASE_LO3_BASE_IDX 1 |
| #define regUVD_RB_BASE_HI3 0x0135 |
| #define regUVD_RB_BASE_HI3_BASE_IDX 1 |
| #define regUVD_RB_SIZE3 0x0136 |
| #define regUVD_RB_SIZE3_BASE_IDX 1 |
| #define regUVD_RB_BASE_LO4 0x0139 |
| #define regUVD_RB_BASE_LO4_BASE_IDX 1 |
| #define regUVD_RB_BASE_HI4 0x013a |
| #define regUVD_RB_BASE_HI4_BASE_IDX 1 |
| #define regUVD_RB_SIZE4 0x013b |
| #define regUVD_RB_SIZE4_BASE_IDX 1 |
| #define regUVD_OUT_RB_BASE_LO 0x013e |
| #define regUVD_OUT_RB_BASE_LO_BASE_IDX 1 |
| #define regUVD_OUT_RB_BASE_HI 0x013f |
| #define regUVD_OUT_RB_BASE_HI_BASE_IDX 1 |
| #define regUVD_OUT_RB_SIZE 0x0140 |
| #define regUVD_OUT_RB_SIZE_BASE_IDX 1 |
| #define regUVD_IOV_ACTIVE_FCN_ID 0x0143 |
| #define regUVD_IOV_ACTIVE_FCN_ID_BASE_IDX 1 |
| #define regUVD_IOV_MAILBOX 0x0144 |
| #define regUVD_IOV_MAILBOX_BASE_IDX 1 |
| #define regUVD_IOV_MAILBOX_RESP 0x0145 |
| #define regUVD_IOV_MAILBOX_RESP_BASE_IDX 1 |
| #define regUVD_RB_ARB_CTRL 0x0146 |
| #define regUVD_RB_ARB_CTRL_BASE_IDX 1 |
| #define regUVD_CTX_INDEX 0x0147 |
| #define regUVD_CTX_INDEX_BASE_IDX 1 |
| #define regUVD_CTX_DATA 0x0148 |
| #define regUVD_CTX_DATA_BASE_IDX 1 |
| #define regUVD_CXW_WR 0x0149 |
| #define regUVD_CXW_WR_BASE_IDX 1 |
| #define regUVD_CXW_WR_INT_ID 0x014a |
| #define regUVD_CXW_WR_INT_ID_BASE_IDX 1 |
| #define regUVD_CXW_WR_INT_CTX_ID 0x014b |
| #define regUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 |
| #define regUVD_CXW_INT_ID 0x014c |
| #define regUVD_CXW_INT_ID_BASE_IDX 1 |
| #define regUVD_MPEG2_ERROR 0x014d |
| #define regUVD_MPEG2_ERROR_BASE_IDX 1 |
| #define regUVD_YBASE 0x0150 |
| #define regUVD_YBASE_BASE_IDX 1 |
| #define regUVD_UVBASE 0x0151 |
| #define regUVD_UVBASE_BASE_IDX 1 |
| #define regUVD_PITCH 0x0152 |
| #define regUVD_PITCH_BASE_IDX 1 |
| #define regUVD_WIDTH 0x0153 |
| #define regUVD_WIDTH_BASE_IDX 1 |
| #define regUVD_HEIGHT 0x0154 |
| #define regUVD_HEIGHT_BASE_IDX 1 |
| #define regUVD_PICCOUNT 0x0155 |
| #define regUVD_PICCOUNT_BASE_IDX 1 |
| #define regUVD_MPRD_INITIAL_XY 0x0156 |
| #define regUVD_MPRD_INITIAL_XY_BASE_IDX 1 |
| #define regUVD_MPEG2_CTRL 0x0157 |
| #define regUVD_MPEG2_CTRL_BASE_IDX 1 |
| #define regUVD_MB_CTL_BUF_BASE 0x0158 |
| #define regUVD_MB_CTL_BUF_BASE_BASE_IDX 1 |
| #define regUVD_PIC_CTL_BUF_BASE 0x0159 |
| #define regUVD_PIC_CTL_BUF_BASE_BASE_IDX 1 |
| #define regUVD_DXVA_BUF_SIZE 0x015a |
| #define regUVD_DXVA_BUF_SIZE_BASE_IDX 1 |
| #define regUVD_SCRATCH_NP 0x015b |
| #define regUVD_SCRATCH_NP_BASE_IDX 1 |
| #define regUVD_CLK_SWT_HANDSHAKE 0x015c |
| #define regUVD_CLK_SWT_HANDSHAKE_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH0 0x015e |
| #define regUVD_GP_SCRATCH0_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH1 0x015f |
| #define regUVD_GP_SCRATCH1_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH2 0x0160 |
| #define regUVD_GP_SCRATCH2_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH3 0x0161 |
| #define regUVD_GP_SCRATCH3_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH4 0x0162 |
| #define regUVD_GP_SCRATCH4_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH5 0x0163 |
| #define regUVD_GP_SCRATCH5_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH6 0x0164 |
| #define regUVD_GP_SCRATCH6_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH7 0x0165 |
| #define regUVD_GP_SCRATCH7_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH8 0x0166 |
| #define regUVD_GP_SCRATCH8_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH9 0x0167 |
| #define regUVD_GP_SCRATCH9_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH10 0x0168 |
| #define regUVD_GP_SCRATCH10_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH11 0x0169 |
| #define regUVD_GP_SCRATCH11_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH12 0x016a |
| #define regUVD_GP_SCRATCH12_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH13 0x016b |
| #define regUVD_GP_SCRATCH13_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH14 0x016c |
| #define regUVD_GP_SCRATCH14_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH15 0x016d |
| #define regUVD_GP_SCRATCH15_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH16 0x016e |
| #define regUVD_GP_SCRATCH16_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH17 0x016f |
| #define regUVD_GP_SCRATCH17_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH18 0x0170 |
| #define regUVD_GP_SCRATCH18_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH19 0x0171 |
| #define regUVD_GP_SCRATCH19_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH20 0x0172 |
| #define regUVD_GP_SCRATCH20_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH21 0x0173 |
| #define regUVD_GP_SCRATCH21_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH22 0x0174 |
| #define regUVD_GP_SCRATCH22_BASE_IDX 1 |
| #define regUVD_GP_SCRATCH23 0x0175 |
| #define regUVD_GP_SCRATCH23_BASE_IDX 1 |
| #define regUVD_AUDIO_RB_BASE_LO 0x0176 |
| #define regUVD_AUDIO_RB_BASE_LO_BASE_IDX 1 |
| #define regUVD_AUDIO_RB_BASE_HI 0x0177 |
| #define regUVD_AUDIO_RB_BASE_HI_BASE_IDX 1 |
| #define regUVD_AUDIO_RB_SIZE 0x0178 |
| #define regUVD_AUDIO_RB_SIZE_BASE_IDX 1 |
| #define regUVD_VCPU_INT_STATUS2 0x017b |
| #define regUVD_VCPU_INT_STATUS2_BASE_IDX 1 |
| #define regUVD_VCPU_INT_ACK2 0x017c |
| #define regUVD_VCPU_INT_ACK2_BASE_IDX 1 |
| #define regUVD_VCPU_INT_EN2 0x017d |
| #define regUVD_VCPU_INT_EN2_BASE_IDX 1 |
| #define regUVD_SUVD_CGC_STATUS2 0x017e |
| #define regUVD_SUVD_CGC_STATUS2_BASE_IDX 1 |
| #define regUVD_SUVD_INT_STATUS2 0x0180 |
| #define regUVD_SUVD_INT_STATUS2_BASE_IDX 1 |
| #define regUVD_SUVD_INT_EN2 0x0181 |
| #define regUVD_SUVD_INT_EN2_BASE_IDX 1 |
| #define regUVD_SUVD_INT_ACK2 0x0182 |
| #define regUVD_SUVD_INT_ACK2_BASE_IDX 1 |
| #define regUVD_STATUS 0x0183 |
| #define regUVD_STATUS_BASE_IDX 1 |
| #define regUVD_ENC_PIPE_BUSY 0x0184 |
| #define regUVD_ENC_PIPE_BUSY_BASE_IDX 1 |
| #define regUVD_FW_POWER_STATUS 0x0185 |
| #define regUVD_FW_POWER_STATUS_BASE_IDX 1 |
| #define regUVD_CNTL 0x0186 |
| #define regUVD_CNTL_BASE_IDX 1 |
| #define regUVD_SOFT_RESET 0x0187 |
| #define regUVD_SOFT_RESET_BASE_IDX 1 |
| #define regUVD_SOFT_RESET2 0x0188 |
| #define regUVD_SOFT_RESET2_BASE_IDX 1 |
| #define regUVD_MMSCH_SOFT_RESET 0x0189 |
| #define regUVD_MMSCH_SOFT_RESET_BASE_IDX 1 |
| #define regUVD_WIG_CTRL 0x018a |
| #define regUVD_WIG_CTRL_BASE_IDX 1 |
| #define regUVD_CGC_STATUS 0x018c |
| #define regUVD_CGC_STATUS_BASE_IDX 1 |
| #define regUVD_CGC_UDEC_STATUS 0x018e |
| #define regUVD_CGC_UDEC_STATUS_BASE_IDX 1 |
| #define regUVD_SUVD_CGC_STATUS 0x0190 |
| #define regUVD_SUVD_CGC_STATUS_BASE_IDX 1 |
| #define regUVD_GPCOM_VCPU_CMD 0x0192 |
| #define regUVD_GPCOM_VCPU_CMD_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_vcn_cdefe_cdefe_broadcast_dec0 |
| // base address: 0x1fc00 |
| #define regCDEFE_SUVD_CGC_GATE 0x0104 |
| #define regCDEFE_SUVD_CGC_GATE_BASE_IDX 1 |
| #define regCDEFE_SUVD_CGC_GATE2 0x0105 |
| #define regCDEFE_SUVD_CGC_GATE2_BASE_IDX 1 |
| #define regCDEFE_SUVD_CGC_CTRL 0x0106 |
| #define regCDEFE_SUVD_CGC_CTRL_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_ecpudec |
| // base address: 0x1ff00 |
| #define regUVD_VCPU_CACHE_OFFSET0 0x01c0 |
| #define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_SIZE0 0x01c1 |
| #define regUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_OFFSET1 0x01c2 |
| #define regUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_SIZE1 0x01c3 |
| #define regUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_OFFSET2 0x01c4 |
| #define regUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_SIZE2 0x01c5 |
| #define regUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_OFFSET3 0x01c6 |
| #define regUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_SIZE3 0x01c7 |
| #define regUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_OFFSET4 0x01c8 |
| #define regUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_SIZE4 0x01c9 |
| #define regUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_OFFSET5 0x01ca |
| #define regUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_SIZE5 0x01cb |
| #define regUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_OFFSET6 0x01cc |
| #define regUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_SIZE6 0x01cd |
| #define regUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_OFFSET7 0x01ce |
| #define regUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_SIZE7 0x01cf |
| #define regUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_OFFSET8 0x01d0 |
| #define regUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 |
| #define regUVD_VCPU_CACHE_SIZE8 0x01d1 |
| #define regUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 |
| #define regUVD_VCPU_NONCACHE_OFFSET0 0x01d2 |
| #define regUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 |
| #define regUVD_VCPU_NONCACHE_SIZE0 0x01d3 |
| #define regUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 |
| #define regUVD_VCPU_NONCACHE_OFFSET1 0x01d4 |
| #define regUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 |
| #define regUVD_VCPU_NONCACHE_SIZE1 0x01d5 |
| #define regUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 |
| #define regUVD_VCPU_CNTL 0x01d6 |
| #define regUVD_VCPU_CNTL_BASE_IDX 1 |
| #define regUVD_VCPU_PRID 0x01d7 |
| #define regUVD_VCPU_PRID_BASE_IDX 1 |
| #define regUVD_VCPU_TRCE 0x01d8 |
| #define regUVD_VCPU_TRCE_BASE_IDX 1 |
| #define regUVD_VCPU_TRCE_RD 0x01d9 |
| #define regUVD_VCPU_TRCE_RD_BASE_IDX 1 |
| #define regUVD_VCPU_IND_INDEX 0x01db |
| #define regUVD_VCPU_IND_INDEX_BASE_IDX 1 |
| #define regUVD_VCPU_IND_DATA 0x01dc |
| #define regUVD_VCPU_IND_DATA_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_lmi_adpdec |
| // base address: 0x20290 |
| #define regUVD_LMI_RE_64BIT_BAR_LOW 0x02af |
| #define regUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_RE_64BIT_BAR_HIGH 0x02b0 |
| #define regUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_IT_64BIT_BAR_LOW 0x02b1 |
| #define regUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_IT_64BIT_BAR_HIGH 0x02b2 |
| #define regUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MP_64BIT_BAR_LOW 0x02b3 |
| #define regUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MP_64BIT_BAR_HIGH 0x02b4 |
| #define regUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_CM_64BIT_BAR_LOW 0x02b5 |
| #define regUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_CM_64BIT_BAR_HIGH 0x02b6 |
| #define regUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_DB_64BIT_BAR_LOW 0x02b7 |
| #define regUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_DB_64BIT_BAR_HIGH 0x02b8 |
| #define regUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_DBW_64BIT_BAR_LOW 0x02b9 |
| #define regUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_DBW_64BIT_BAR_HIGH 0x02ba |
| #define regUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_IDCT_64BIT_BAR_LOW 0x02bb |
| #define regUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_IDCT_64BIT_BAR_HIGH 0x02bc |
| #define regUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW 0x02bd |
| #define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH 0x02be |
| #define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW 0x02bf |
| #define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH 0x02c0 |
| #define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW 0x02c1 |
| #define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 0x02c2 |
| #define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x02c5 |
| #define regUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x02c6 |
| #define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x02c7 |
| #define regUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x02c8 |
| #define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_LBSI_64BIT_BAR_LOW 0x02c9 |
| #define regUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_LBSI_64BIT_BAR_HIGH 0x02ca |
| #define regUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x02cb |
| #define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x02cc |
| #define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x02cd |
| #define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x02ce |
| #define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x02cf |
| #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x02d0 |
| #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_CENC_64BIT_BAR_LOW 0x02d1 |
| #define regUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_CENC_64BIT_BAR_HIGH 0x02d2 |
| #define regUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_SRE_64BIT_BAR_LOW 0x02d3 |
| #define regUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_SRE_64BIT_BAR_HIGH 0x02d4 |
| #define regUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 0x02d5 |
| #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 0x02d6 |
| #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 0x02d7 |
| #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 0x02d8 |
| #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 0x02d9 |
| #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 0x02da |
| #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW 0x02dd |
| #define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH 0x02de |
| #define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 0x02df |
| #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 0x02e0 |
| #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW 0x02e1 |
| #define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 0x02e2 |
| #define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW 0x02e3 |
| #define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 0x02e4 |
| #define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW 0x02e5 |
| #define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 0x02e6 |
| #define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW 0x02e7 |
| #define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 0x02e8 |
| #define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW 0x02e9 |
| #define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 0x02ea |
| #define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW 0x02eb |
| #define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 0x02ec |
| #define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW 0x02ed |
| #define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 0x02ee |
| #define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW 0x02ef |
| #define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 0x02f0 |
| #define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW 0x02f1 |
| #define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 0x02f2 |
| #define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x02fb |
| #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x02fc |
| #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x02fd |
| #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x02fe |
| #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x02ff |
| #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x0300 |
| #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x0301 |
| #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x0302 |
| #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0303 |
| #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0304 |
| #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x0305 |
| #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x0306 |
| #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x0307 |
| #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x0308 |
| #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x0309 |
| #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x030a |
| #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW 0x030b |
| #define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 0x030c |
| #define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 0x030d |
| #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 0x030e |
| #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_SPH_64BIT_BAR_HIGH 0x030f |
| #define regUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 0x0318 |
| #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 0x0319 |
| #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 0x031a |
| #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 0x031b |
| #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 0x031c |
| #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 0x031d |
| #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 0x031e |
| #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 0x031f |
| #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_ADP_ATOMIC_CONFIG 0x0321 |
| #define regUVD_ADP_ATOMIC_CONFIG_BASE_IDX 1 |
| #define regUVD_LMI_ARB_CTRL2 0x0322 |
| #define regUVD_LMI_ARB_CTRL2_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x0327 |
| #define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_NC_VMIDS_MULTI 0x0328 |
| #define regUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 |
| #define regUVD_LMI_LAT_CTRL 0x0329 |
| #define regUVD_LMI_LAT_CTRL_BASE_IDX 1 |
| #define regUVD_LMI_LAT_CNTR 0x032a |
| #define regUVD_LMI_LAT_CNTR_BASE_IDX 1 |
| #define regUVD_LMI_AVG_LAT_CNTR 0x032b |
| #define regUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 |
| #define regUVD_LMI_SPH 0x032c |
| #define regUVD_LMI_SPH_BASE_IDX 1 |
| #define regUVD_LMI_VCPU_CACHE_VMID 0x032d |
| #define regUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 |
| #define regUVD_LMI_CTRL2 0x032e |
| #define regUVD_LMI_CTRL2_BASE_IDX 1 |
| #define regUVD_LMI_URGENT_CTRL 0x032f |
| #define regUVD_LMI_URGENT_CTRL_BASE_IDX 1 |
| #define regUVD_LMI_CTRL 0x0330 |
| #define regUVD_LMI_CTRL_BASE_IDX 1 |
| #define regUVD_LMI_STATUS 0x0331 |
| #define regUVD_LMI_STATUS_BASE_IDX 1 |
| #define regUVD_LMI_PERFMON_CTRL 0x0334 |
| #define regUVD_LMI_PERFMON_CTRL_BASE_IDX 1 |
| #define regUVD_LMI_PERFMON_COUNT_LO 0x0335 |
| #define regUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 |
| #define regUVD_LMI_PERFMON_COUNT_HI 0x0336 |
| #define regUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 |
| #define regUVD_LMI_ADP_SWAP_CNTL 0x0337 |
| #define regUVD_LMI_ADP_SWAP_CNTL_BASE_IDX 1 |
| #define regUVD_LMI_RBC_RB_VMID 0x0338 |
| #define regUVD_LMI_RBC_RB_VMID_BASE_IDX 1 |
| #define regUVD_LMI_RBC_IB_VMID 0x0339 |
| #define regUVD_LMI_RBC_IB_VMID_BASE_IDX 1 |
| #define regUVD_LMI_MC_CREDITS 0x033a |
| #define regUVD_LMI_MC_CREDITS_BASE_IDX 1 |
| #define regUVD_LMI_ADP_IND_INDEX 0x033e |
| #define regUVD_LMI_ADP_IND_INDEX_BASE_IDX 1 |
| #define regUVD_LMI_ADP_IND_DATA 0x033f |
| #define regUVD_LMI_ADP_IND_DATA_BASE_IDX 1 |
| #define regUVD_LMI_ADP_PF_EN 0x0340 |
| #define regUVD_LMI_ADP_PF_EN_BASE_IDX 1 |
| #define regUVD_LMI_PREF_CTRL 0x0342 |
| #define regUVD_LMI_PREF_CTRL_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_uvd_jpeg0_jpegnpdec |
| // base address: 0x20f00 |
| #define regUVD_JPEG_CNTL 0x05c0 |
| #define regUVD_JPEG_CNTL_BASE_IDX 1 |
| #define regUVD_JPEG_RB_BASE 0x05c1 |
| #define regUVD_JPEG_RB_BASE_BASE_IDX 1 |
| #define regUVD_JPEG_RB_WPTR 0x05c2 |
| #define regUVD_JPEG_RB_WPTR_BASE_IDX 1 |
| #define regUVD_JPEG_RB_RPTR 0x05c3 |
| #define regUVD_JPEG_RB_RPTR_BASE_IDX 1 |
| #define regUVD_JPEG_RB_SIZE 0x05c4 |
| #define regUVD_JPEG_RB_SIZE_BASE_IDX 1 |
| #define regUVD_JPEG_DEC_CNT 0x05c5 |
| #define regUVD_JPEG_DEC_CNT_BASE_IDX 1 |
| #define regUVD_JPEG_SPS_INFO 0x05c6 |
| #define regUVD_JPEG_SPS_INFO_BASE_IDX 1 |
| #define regUVD_JPEG_SPS1_INFO 0x05c7 |
| #define regUVD_JPEG_SPS1_INFO_BASE_IDX 1 |
| #define regUVD_JPEG_RE_TIMER 0x05c8 |
| #define regUVD_JPEG_RE_TIMER_BASE_IDX 1 |
| #define regUVD_JPEG_DEC_SCRATCH0 0x05c9 |
| #define regUVD_JPEG_DEC_SCRATCH0_BASE_IDX 1 |
| #define regUVD_JPEG_INT_EN 0x05ca |
| #define regUVD_JPEG_INT_EN_BASE_IDX 1 |
| #define regUVD_JPEG_INT_STAT 0x05cb |
| #define regUVD_JPEG_INT_STAT_BASE_IDX 1 |
| #define regUVD_JPEG_TIER_CNTL0 0x05cc |
| #define regUVD_JPEG_TIER_CNTL0_BASE_IDX 1 |
| #define regUVD_JPEG_TIER_CNTL1 0x05cd |
| #define regUVD_JPEG_TIER_CNTL1_BASE_IDX 1 |
| #define regUVD_JPEG_TIER_CNTL2 0x05ce |
| #define regUVD_JPEG_TIER_CNTL2_BASE_IDX 1 |
| #define regUVD_JPEG_TIER_STATUS 0x05cf |
| #define regUVD_JPEG_TIER_STATUS_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_uvd_jpeg_sclk0_jpegnpsclkdec |
| // base address: 0x21000 |
| #define regUVD_JPEG_OUTBUF_CNTL 0x0600 |
| #define regUVD_JPEG_OUTBUF_CNTL_BASE_IDX 1 |
| #define regUVD_JPEG_OUTBUF_WPTR 0x0601 |
| #define regUVD_JPEG_OUTBUF_WPTR_BASE_IDX 1 |
| #define regUVD_JPEG_OUTBUF_RPTR 0x0602 |
| #define regUVD_JPEG_OUTBUF_RPTR_BASE_IDX 1 |
| #define regUVD_JPEG_PITCH 0x0603 |
| #define regUVD_JPEG_PITCH_BASE_IDX 1 |
| #define regUVD_JPEG_UV_PITCH 0x0604 |
| #define regUVD_JPEG_UV_PITCH_BASE_IDX 1 |
| #define regJPEG_DEC_Y_GFX8_TILING_SURFACE 0x0605 |
| #define regJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 1 |
| #define regJPEG_DEC_UV_GFX8_TILING_SURFACE 0x0606 |
| #define regJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 1 |
| #define regJPEG_DEC_GFX8_ADDR_CONFIG 0x0607 |
| #define regJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 1 |
| #define regJPEG_DEC_Y_GFX10_TILING_SURFACE 0x0608 |
| #define regJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 1 |
| #define regJPEG_DEC_UV_GFX10_TILING_SURFACE 0x0609 |
| #define regJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 1 |
| #define regJPEG_DEC_GFX10_ADDR_CONFIG 0x060a |
| #define regJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 1 |
| #define regJPEG_DEC_ADDR_MODE 0x060b |
| #define regJPEG_DEC_ADDR_MODE_BASE_IDX 1 |
| #define regUVD_JPEG_OUTPUT_XY 0x060c |
| #define regUVD_JPEG_OUTPUT_XY_BASE_IDX 1 |
| #define regUVD_JPEG_GPCOM_CMD 0x060d |
| #define regUVD_JPEG_GPCOM_CMD_BASE_IDX 1 |
| #define regUVD_JPEG_GPCOM_DATA0 0x060e |
| #define regUVD_JPEG_GPCOM_DATA0_BASE_IDX 1 |
| #define regUVD_JPEG_GPCOM_DATA1 0x060f |
| #define regUVD_JPEG_GPCOM_DATA1_BASE_IDX 1 |
| #define regUVD_JPEG_SCRATCH1 0x0610 |
| #define regUVD_JPEG_SCRATCH1_BASE_IDX 1 |
| #define regUVD_JPEG_DEC_SOFT_RST 0x0611 |
| #define regUVD_JPEG_DEC_SOFT_RST_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_uvd_jrbc0_uvd_jrbc_dec |
| // base address: 0x21100 |
| #define regUVD_JRBC_RB_WPTR 0x0640 |
| #define regUVD_JRBC_RB_WPTR_BASE_IDX 1 |
| #define regUVD_JRBC_RB_CNTL 0x0641 |
| #define regUVD_JRBC_RB_CNTL_BASE_IDX 1 |
| #define regUVD_JRBC_IB_SIZE 0x0642 |
| #define regUVD_JRBC_IB_SIZE_BASE_IDX 1 |
| #define regUVD_JRBC_URGENT_CNTL 0x0643 |
| #define regUVD_JRBC_URGENT_CNTL_BASE_IDX 1 |
| #define regUVD_JRBC_RB_REF_DATA 0x0644 |
| #define regUVD_JRBC_RB_REF_DATA_BASE_IDX 1 |
| #define regUVD_JRBC_RB_COND_RD_TIMER 0x0645 |
| #define regUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 |
| #define regUVD_JRBC_SOFT_RESET 0x0648 |
| #define regUVD_JRBC_SOFT_RESET_BASE_IDX 1 |
| #define regUVD_JRBC_STATUS 0x0649 |
| #define regUVD_JRBC_STATUS_BASE_IDX 1 |
| #define regUVD_JRBC_RB_RPTR 0x064a |
| #define regUVD_JRBC_RB_RPTR_BASE_IDX 1 |
| #define regUVD_JRBC_RB_BUF_STATUS 0x064b |
| #define regUVD_JRBC_RB_BUF_STATUS_BASE_IDX 1 |
| #define regUVD_JRBC_IB_BUF_STATUS 0x064c |
| #define regUVD_JRBC_IB_BUF_STATUS_BASE_IDX 1 |
| #define regUVD_JRBC_IB_SIZE_UPDATE 0x064d |
| #define regUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 1 |
| #define regUVD_JRBC_IB_COND_RD_TIMER 0x064e |
| #define regUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 1 |
| #define regUVD_JRBC_IB_REF_DATA 0x064f |
| #define regUVD_JRBC_IB_REF_DATA_BASE_IDX 1 |
| #define regUVD_JPEG_PREEMPT_CMD 0x0650 |
| #define regUVD_JPEG_PREEMPT_CMD_BASE_IDX 1 |
| #define regUVD_JPEG_PREEMPT_FENCE_DATA0 0x0651 |
| #define regUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 1 |
| #define regUVD_JPEG_PREEMPT_FENCE_DATA1 0x0652 |
| #define regUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 1 |
| #define regUVD_JRBC_RB_SIZE 0x0653 |
| #define regUVD_JRBC_RB_SIZE_BASE_IDX 1 |
| #define regUVD_JRBC_SCRATCH0 0x0654 |
| #define regUVD_JRBC_SCRATCH0_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_uvd_jmi0_uvd_jmi_dec |
| // base address: 0x21180 |
| #define regUVD_JPEG_DEC_PF_CTRL 0x0660 |
| #define regUVD_JPEG_DEC_PF_CTRL_BASE_IDX 1 |
| #define regUVD_LMI_JRBC_CTRL 0x0661 |
| #define regUVD_LMI_JRBC_CTRL_BASE_IDX 1 |
| #define regUVD_LMI_JPEG_CTRL 0x0662 |
| #define regUVD_LMI_JPEG_CTRL_BASE_IDX 1 |
| #define regJPEG_LMI_DROP 0x0663 |
| #define regJPEG_LMI_DROP_BASE_IDX 1 |
| #define regUVD_LMI_JRBC_IB_VMID 0x0664 |
| #define regUVD_LMI_JRBC_IB_VMID_BASE_IDX 1 |
| #define regUVD_LMI_JRBC_RB_VMID 0x0665 |
| #define regUVD_LMI_JRBC_RB_VMID_BASE_IDX 1 |
| #define regUVD_LMI_JPEG_VMID 0x0666 |
| #define regUVD_LMI_JPEG_VMID_BASE_IDX 1 |
| #define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0667 |
| #define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0668 |
| #define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0669 |
| #define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x066a |
| #define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x066b |
| #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x066c |
| #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_JPEG_PREEMPT_VMID 0x066d |
| #define regUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 1 |
| #define regUVD_JMI_DEC_SWAP_CNTL 0x066e |
| #define regUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 1 |
| #define regUVD_JMI_ATOMIC_CNTL 0x066f |
| #define regUVD_JMI_ATOMIC_CNTL_BASE_IDX 1 |
| #define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x0670 |
| #define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x0671 |
| #define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0672 |
| #define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0673 |
| #define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0674 |
| #define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0675 |
| #define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0676 |
| #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0677 |
| #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0678 |
| #define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0679 |
| #define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_JMI_ATOMIC_CNTL2 0x067d |
| #define regUVD_JMI_ATOMIC_CNTL2_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_uvd_jmi_common_dec |
| // base address: 0x21300 |
| #define regUVD_JADP_MCIF_URGENT_CTRL 0x06c1 |
| #define regUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX 1 |
| #define regUVD_JMI_URGENT_CTRL 0x06c2 |
| #define regUVD_JMI_URGENT_CTRL_BASE_IDX 1 |
| #define regUVD_JMI_CTRL 0x06c3 |
| #define regUVD_JMI_CTRL_BASE_IDX 1 |
| #define regJPEG_MEMCHECK_CLAMPING_CNTL 0x06c4 |
| #define regJPEG_MEMCHECK_CLAMPING_CNTL_BASE_IDX 1 |
| #define regJPEG_MEMCHECK_SAFE_ADDR 0x06c5 |
| #define regJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX 1 |
| #define regJPEG_MEMCHECK_SAFE_ADDR_64BIT 0x06c6 |
| #define regJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX 1 |
| #define regUVD_JMI_LAT_CTRL 0x06c7 |
| #define regUVD_JMI_LAT_CTRL_BASE_IDX 1 |
| #define regUVD_JMI_LAT_CNTR 0x06c8 |
| #define regUVD_JMI_LAT_CNTR_BASE_IDX 1 |
| #define regUVD_JMI_AVG_LAT_CNTR 0x06c9 |
| #define regUVD_JMI_AVG_LAT_CNTR_BASE_IDX 1 |
| #define regUVD_JMI_PERFMON_CTRL 0x06ca |
| #define regUVD_JMI_PERFMON_CTRL_BASE_IDX 1 |
| #define regUVD_JMI_PERFMON_COUNT_LO 0x06cb |
| #define regUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 1 |
| #define regUVD_JMI_PERFMON_COUNT_HI 0x06cc |
| #define regUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 1 |
| #define regUVD_JMI_CLEAN_STATUS 0x06cd |
| #define regUVD_JMI_CLEAN_STATUS_BASE_IDX 1 |
| #define regUVD_JMI_CNTL 0x06ce |
| #define regUVD_JMI_CNTL_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_uvd_jpeg_common_dec |
| // base address: 0x21400 |
| #define regJPEG_SOFT_RESET_STATUS 0x0700 |
| #define regJPEG_SOFT_RESET_STATUS_BASE_IDX 1 |
| #define regJPEG_SYS_INT_EN 0x0701 |
| #define regJPEG_SYS_INT_EN_BASE_IDX 1 |
| #define regJPEG_SYS_INT_EN1 0x0702 |
| #define regJPEG_SYS_INT_EN1_BASE_IDX 1 |
| #define regJPEG_SYS_INT_STATUS 0x0703 |
| #define regJPEG_SYS_INT_STATUS_BASE_IDX 1 |
| #define regJPEG_SYS_INT_STATUS1 0x0704 |
| #define regJPEG_SYS_INT_STATUS1_BASE_IDX 1 |
| #define regJPEG_SYS_INT_ACK 0x0705 |
| #define regJPEG_SYS_INT_ACK_BASE_IDX 1 |
| #define regJPEG_SYS_INT_ACK1 0x0706 |
| #define regJPEG_SYS_INT_ACK1_BASE_IDX 1 |
| #define regJPEG_MEMCHECK_SYS_INT_EN 0x0707 |
| #define regJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX 1 |
| #define regJPEG_MEMCHECK_SYS_INT_EN1 0x0708 |
| #define regJPEG_MEMCHECK_SYS_INT_EN1_BASE_IDX 1 |
| #define regJPEG_MEMCHECK_SYS_INT_STAT 0x0709 |
| #define regJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX 1 |
| #define regJPEG_MEMCHECK_SYS_INT_STAT1 0x070a |
| #define regJPEG_MEMCHECK_SYS_INT_STAT1_BASE_IDX 1 |
| #define regJPEG_MEMCHECK_SYS_INT_STAT2 0x070b |
| #define regJPEG_MEMCHECK_SYS_INT_STAT2_BASE_IDX 1 |
| #define regJPEG_MEMCHECK_SYS_INT_ACK 0x070c |
| #define regJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX 1 |
| #define regJPEG_MEMCHECK_SYS_INT_ACK1 0x070d |
| #define regJPEG_MEMCHECK_SYS_INT_ACK1_BASE_IDX 1 |
| #define regJPEG_MEMCHECK_SYS_INT_ACK2 0x070e |
| #define regJPEG_MEMCHECK_SYS_INT_ACK2_BASE_IDX 1 |
| #define regJPEG_MASTINT_EN 0x070f |
| #define regJPEG_MASTINT_EN_BASE_IDX 1 |
| #define regJPEG_IH_CTRL 0x0710 |
| #define regJPEG_IH_CTRL_BASE_IDX 1 |
| #define regJRBBM_ARB_CTRL 0x0712 |
| #define regJRBBM_ARB_CTRL_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_uvd_jpeg_common_sclk_dec |
| // base address: 0x21480 |
| #define regJPEG_CGC_GATE 0x0720 |
| #define regJPEG_CGC_GATE_BASE_IDX 1 |
| #define regJPEG_CGC_CTRL 0x0721 |
| #define regJPEG_CGC_CTRL_BASE_IDX 1 |
| #define regJPEG_CGC_STATUS 0x0722 |
| #define regJPEG_CGC_STATUS_BASE_IDX 1 |
| #define regJPEG_COMN_CGC_MEM_CTRL 0x0723 |
| #define regJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 1 |
| #define regJPEG_DEC_CGC_MEM_CTRL 0x0724 |
| #define regJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 1 |
| #define regJPEG_ENC_CGC_MEM_CTRL 0x0726 |
| #define regJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 1 |
| #define regJPEG_PERF_BANK_CONF 0x0727 |
| #define regJPEG_PERF_BANK_CONF_BASE_IDX 1 |
| #define regJPEG_PERF_BANK_EVENT_SEL 0x0728 |
| #define regJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 1 |
| #define regJPEG_PERF_BANK_COUNT0 0x0729 |
| #define regJPEG_PERF_BANK_COUNT0_BASE_IDX 1 |
| #define regJPEG_PERF_BANK_COUNT1 0x072a |
| #define regJPEG_PERF_BANK_COUNT1_BASE_IDX 1 |
| #define regJPEG_PERF_BANK_COUNT2 0x072b |
| #define regJPEG_PERF_BANK_COUNT2_BASE_IDX 1 |
| #define regJPEG_PERF_BANK_COUNT3 0x072c |
| #define regJPEG_PERF_BANK_COUNT3_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_uvd_pg_dec |
| // base address: 0x1f800 |
| #define regUVD_IPX_DLDO_CONFIG 0x0000 |
| #define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1 |
| #define regUVD_IPX_DLDO_STATUS 0x0001 |
| #define regUVD_IPX_DLDO_STATUS_BASE_IDX 1 |
| #define regUVD_POWER_STATUS 0x0002 |
| #define regUVD_POWER_STATUS_BASE_IDX 1 |
| #define regUVD_JPEG_POWER_STATUS 0x0003 |
| #define regUVD_JPEG_POWER_STATUS_BASE_IDX 1 |
| #define regUVD_MC_DJPEG_RD_SPACE 0x0007 |
| #define regUVD_MC_DJPEG_RD_SPACE_BASE_IDX 1 |
| #define regUVD_MC_DJPEG_WR_SPACE 0x0008 |
| #define regUVD_MC_DJPEG_WR_SPACE_BASE_IDX 1 |
| #define regUVD_PG_IND_INDEX 0x000c |
| #define regUVD_PG_IND_INDEX_BASE_IDX 1 |
| #define regUVD_PG_IND_DATA 0x000e |
| #define regUVD_PG_IND_DATA_BASE_IDX 1 |
| #define regCC_UVD_HARVESTING 0x000f |
| #define regCC_UVD_HARVESTING_BASE_IDX 1 |
| #define regUVD_DPG_LMA_CTL 0x0011 |
| #define regUVD_DPG_LMA_CTL_BASE_IDX 1 |
| #define regUVD_DPG_LMA_DATA 0x0012 |
| #define regUVD_DPG_LMA_DATA_BASE_IDX 1 |
| #define regUVD_DPG_LMA_MASK 0x0013 |
| #define regUVD_DPG_LMA_MASK_BASE_IDX 1 |
| #define regUVD_DPG_PAUSE 0x0014 |
| #define regUVD_DPG_PAUSE_BASE_IDX 1 |
| #define regUVD_SCRATCH1 0x0015 |
| #define regUVD_SCRATCH1_BASE_IDX 1 |
| #define regUVD_SCRATCH2 0x0016 |
| #define regUVD_SCRATCH2_BASE_IDX 1 |
| #define regUVD_SCRATCH3 0x0017 |
| #define regUVD_SCRATCH3_BASE_IDX 1 |
| #define regUVD_SCRATCH4 0x0018 |
| #define regUVD_SCRATCH4_BASE_IDX 1 |
| #define regUVD_SCRATCH5 0x0019 |
| #define regUVD_SCRATCH5_BASE_IDX 1 |
| #define regUVD_SCRATCH6 0x001a |
| #define regUVD_SCRATCH6_BASE_IDX 1 |
| #define regUVD_SCRATCH7 0x001b |
| #define regUVD_SCRATCH7_BASE_IDX 1 |
| #define regUVD_SCRATCH8 0x001c |
| #define regUVD_SCRATCH8_BASE_IDX 1 |
| #define regUVD_SCRATCH9 0x001d |
| #define regUVD_SCRATCH9_BASE_IDX 1 |
| #define regUVD_SCRATCH10 0x001e |
| #define regUVD_SCRATCH10_BASE_IDX 1 |
| #define regUVD_SCRATCH11 0x001f |
| #define regUVD_SCRATCH11_BASE_IDX 1 |
| #define regUVD_SCRATCH12 0x0020 |
| #define regUVD_SCRATCH12_BASE_IDX 1 |
| #define regUVD_SCRATCH13 0x0021 |
| #define regUVD_SCRATCH13_BASE_IDX 1 |
| #define regUVD_SCRATCH14 0x0022 |
| #define regUVD_SCRATCH14_BASE_IDX 1 |
| #define regUVD_FREE_COUNTER_REG 0x0023 |
| #define regUVD_FREE_COUNTER_REG_BASE_IDX 1 |
| #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0024 |
| #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0025 |
| #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_DPG_VCPU_CACHE_OFFSET0 0x0026 |
| #define regUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 |
| #define regUVD_DPG_LMI_VCPU_CACHE_VMID 0x0027 |
| #define regUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 |
| #define regUVD_REG_FILTER_EN 0x0028 |
| #define regUVD_REG_FILTER_EN_BASE_IDX 1 |
| #define regUVD_SECURITY_REG_VIO_REPORT 0x0029 |
| #define regUVD_SECURITY_REG_VIO_REPORT_BASE_IDX 1 |
| #define regUVD_FW_VERSION 0x002a |
| #define regUVD_FW_VERSION_BASE_IDX 1 |
| #define regUVD_PF_STATUS 0x002c |
| #define regUVD_PF_STATUS_BASE_IDX 1 |
| #define regUVD_DPG_CLK_EN_VCPU_REPORT 0x002e |
| #define regUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 |
| #define regCC_UVD_VCPU_ERR_DETECT_BOT_LO 0x002f |
| #define regCC_UVD_VCPU_ERR_DETECT_BOT_LO_BASE_IDX 1 |
| #define regCC_UVD_VCPU_ERR_DETECT_BOT_HI 0x0030 |
| #define regCC_UVD_VCPU_ERR_DETECT_BOT_HI_BASE_IDX 1 |
| #define regCC_UVD_VCPU_ERR_DETECT_TOP_LO 0x0031 |
| #define regCC_UVD_VCPU_ERR_DETECT_TOP_LO_BASE_IDX 1 |
| #define regCC_UVD_VCPU_ERR_DETECT_TOP_HI 0x0032 |
| #define regCC_UVD_VCPU_ERR_DETECT_TOP_HI_BASE_IDX 1 |
| #define regCC_UVD_VCPU_ERR 0x0033 |
| #define regCC_UVD_VCPU_ERR_BASE_IDX 1 |
| #define regCC_UVD_VCPU_ERR_INST_ADDR_LO 0x0034 |
| #define regCC_UVD_VCPU_ERR_INST_ADDR_LO_BASE_IDX 1 |
| #define regCC_UVD_VCPU_ERR_INST_ADDR_HI 0x0035 |
| #define regCC_UVD_VCPU_ERR_INST_ADDR_HI_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC_SPACE 0x003d |
| #define regUVD_LMI_MMSCH_NC_SPACE_BASE_IDX 1 |
| #define regUVD_LMI_ATOMIC_SPACE 0x003e |
| #define regUVD_LMI_ATOMIC_SPACE_BASE_IDX 1 |
| #define regUVD_GFX8_ADDR_CONFIG 0x0041 |
| #define regUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 |
| #define regUVD_GFX10_ADDR_CONFIG 0x0042 |
| #define regUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 |
| #define regUVD_GPCNT2_CNTL 0x0043 |
| #define regUVD_GPCNT2_CNTL_BASE_IDX 1 |
| #define regUVD_GPCNT2_TARGET_LOWER 0x0044 |
| #define regUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 |
| #define regUVD_GPCNT2_STATUS_LOWER 0x0045 |
| #define regUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 |
| #define regUVD_GPCNT2_TARGET_UPPER 0x0046 |
| #define regUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 |
| #define regUVD_GPCNT2_STATUS_UPPER 0x0047 |
| #define regUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 |
| #define regUVD_GPCNT3_CNTL 0x0048 |
| #define regUVD_GPCNT3_CNTL_BASE_IDX 1 |
| #define regUVD_GPCNT3_TARGET_LOWER 0x0049 |
| #define regUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 |
| #define regUVD_GPCNT3_STATUS_LOWER 0x004a |
| #define regUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 |
| #define regUVD_GPCNT3_TARGET_UPPER 0x004b |
| #define regUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 |
| #define regUVD_GPCNT3_STATUS_UPPER 0x004c |
| #define regUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 |
| #define regUVD_VCLK_DS_CNTL 0x004d |
| #define regUVD_VCLK_DS_CNTL_BASE_IDX 1 |
| #define regUVD_DCLK_DS_CNTL 0x004e |
| #define regUVD_DCLK_DS_CNTL_BASE_IDX 1 |
| #define regUVD_TSC_LOWER 0x004f |
| #define regUVD_TSC_LOWER_BASE_IDX 1 |
| #define regUVD_TSC_UPPER 0x0050 |
| #define regUVD_TSC_UPPER_BASE_IDX 1 |
| #define regVCN_FEATURES 0x0051 |
| #define regVCN_FEATURES_BASE_IDX 1 |
| #define regUVD_GPUIOV_STATUS 0x0055 |
| #define regUVD_GPUIOV_STATUS_BASE_IDX 1 |
| #define regUVD_SCRATCH15 0x005c |
| #define regUVD_SCRATCH15_BASE_IDX 1 |
| #define regUVD_VERSION 0x005d |
| #define regUVD_VERSION_BASE_IDX 1 |
| #define regVCN_UMSCH_CNTL 0x005e |
| #define regVCN_UMSCH_CNTL_BASE_IDX 1 |
| #define regVCN_JPEG_DB_CTRL 0x0068 |
| #define regVCN_JPEG_DB_CTRL_BASE_IDX 1 |
| #define regVCN_RB1_DB_CTRL 0x0072 |
| #define regVCN_RB1_DB_CTRL_BASE_IDX 1 |
| #define regVCN_RB2_DB_CTRL 0x0073 |
| #define regVCN_RB2_DB_CTRL_BASE_IDX 1 |
| #define regVCN_RB3_DB_CTRL 0x0074 |
| #define regVCN_RB3_DB_CTRL_BASE_IDX 1 |
| #define regVCN_RB4_DB_CTRL 0x0075 |
| #define regVCN_RB4_DB_CTRL_BASE_IDX 1 |
| #define regVCN_UMSCH_RB_DB_CTRL 0x0076 |
| #define regVCN_UMSCH_RB_DB_CTRL_BASE_IDX 1 |
| #define regVCN_RB_DB_CTRL 0x0077 |
| #define regVCN_RB_DB_CTRL_BASE_IDX 1 |
| #define regVCN_AGDB_CTRL0 0x0079 |
| #define regVCN_AGDB_CTRL0_BASE_IDX 1 |
| #define regVCN_AGDB_CTRL1 0x007a |
| #define regVCN_AGDB_CTRL1_BASE_IDX 1 |
| #define regVCN_AGDB_CTRL2 0x007b |
| #define regVCN_AGDB_CTRL2_BASE_IDX 1 |
| #define regVCN_AGDB_CTRL3 0x007c |
| #define regVCN_AGDB_CTRL3_BASE_IDX 1 |
| #define regVCN_AGDB_CTRL4 0x007d |
| #define regVCN_AGDB_CTRL4_BASE_IDX 1 |
| #define regVCN_AGDB_CTRL5 0x007e |
| #define regVCN_AGDB_CTRL5_BASE_IDX 1 |
| #define regVCN_AGDB_MASK0 0x007f |
| #define regVCN_AGDB_MASK0_BASE_IDX 1 |
| #define regVCN_AGDB_MASK1 0x0080 |
| #define regVCN_AGDB_MASK1_BASE_IDX 1 |
| #define regVCN_AGDB_MASK2 0x0081 |
| #define regVCN_AGDB_MASK2_BASE_IDX 1 |
| #define regVCN_AGDB_MASK3 0x0082 |
| #define regVCN_AGDB_MASK3_BASE_IDX 1 |
| #define regVCN_AGDB_MASK4 0x0083 |
| #define regVCN_AGDB_MASK4_BASE_IDX 1 |
| #define regVCN_AGDB_MASK5 0x0084 |
| #define regVCN_AGDB_MASK5_BASE_IDX 1 |
| #define regVCN_RB_ENABLE 0x0085 |
| #define regVCN_RB_ENABLE_BASE_IDX 1 |
| #define regVCN_RB_WPTR_CTRL 0x0086 |
| #define regVCN_RB_WPTR_CTRL_BASE_IDX 1 |
| #define regUVD_RB_RPTR 0x00ac |
| #define regUVD_RB_RPTR_BASE_IDX 1 |
| #define regUVD_RB_WPTR 0x00ad |
| #define regUVD_RB_WPTR_BASE_IDX 1 |
| #define regUVD_RB_RPTR2 0x00ae |
| #define regUVD_RB_RPTR2_BASE_IDX 1 |
| #define regUVD_RB_WPTR2 0x00af |
| #define regUVD_RB_WPTR2_BASE_IDX 1 |
| #define regUVD_RB_RPTR3 0x00b0 |
| #define regUVD_RB_RPTR3_BASE_IDX 1 |
| #define regUVD_RB_WPTR3 0x00b1 |
| #define regUVD_RB_WPTR3_BASE_IDX 1 |
| #define regUVD_RB_RPTR4 0x00b2 |
| #define regUVD_RB_RPTR4_BASE_IDX 1 |
| #define regUVD_RB_WPTR4 0x00b3 |
| #define regUVD_RB_WPTR4_BASE_IDX 1 |
| #define regUVD_OUT_RB_RPTR 0x00b4 |
| #define regUVD_OUT_RB_RPTR_BASE_IDX 1 |
| #define regUVD_OUT_RB_WPTR 0x00b5 |
| #define regUVD_OUT_RB_WPTR_BASE_IDX 1 |
| #define regUVD_AUDIO_RB_RPTR 0x00b6 |
| #define regUVD_AUDIO_RB_RPTR_BASE_IDX 1 |
| #define regUVD_AUDIO_RB_WPTR 0x00b7 |
| #define regUVD_AUDIO_RB_WPTR_BASE_IDX 1 |
| #define regUVD_RBC_RB_RPTR 0x00b8 |
| #define regUVD_RBC_RB_RPTR_BASE_IDX 1 |
| #define regUVD_RBC_RB_WPTR 0x00b9 |
| #define regUVD_RBC_RB_WPTR_BASE_IDX 1 |
| #define regUVD_DPG_LMA_CTL2 0x00bb |
| #define regUVD_DPG_LMA_CTL2_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_vcn_umsch_dec |
| // base address: 0x21500 |
| #define regVCN_UMSCH_MES_CNTL 0x0740 |
| #define regVCN_UMSCH_MES_CNTL_BASE_IDX 1 |
| #define regUMSCH_CTL 0x0741 |
| #define regUMSCH_CTL_BASE_IDX 1 |
| #define regUMSCH_CTL2 0x0742 |
| #define regUMSCH_CTL2_BASE_IDX 1 |
| #define regVCN_UMSCH_AGDB_WPTR0 0x0743 |
| #define regVCN_UMSCH_AGDB_WPTR0_BASE_IDX 1 |
| #define regVCN_UMSCH_AGDB_WPTR1 0x0744 |
| #define regVCN_UMSCH_AGDB_WPTR1_BASE_IDX 1 |
| #define regVCN_UMSCH_AGDB_WPTR2 0x0745 |
| #define regVCN_UMSCH_AGDB_WPTR2_BASE_IDX 1 |
| #define regVCN_UMSCH_AGDB_WPTR3 0x0746 |
| #define regVCN_UMSCH_AGDB_WPTR3_BASE_IDX 1 |
| #define regVCN_UMSCH_AGDB_WPTR4 0x0747 |
| #define regVCN_UMSCH_AGDB_WPTR4_BASE_IDX 1 |
| #define regVCN_UMSCH_AGDB_WPTR5 0x0748 |
| #define regVCN_UMSCH_AGDB_WPTR5_BASE_IDX 1 |
| #define regVCN_UMSCH_MAILBOX0 0x0749 |
| #define regVCN_UMSCH_MAILBOX0_BASE_IDX 1 |
| #define regVCN_UMSCH_MAILBOX_RESP0 0x074a |
| #define regVCN_UMSCH_MAILBOX_RESP0_BASE_IDX 1 |
| #define regVCN_UMSCH_MAILBOX1 0x074b |
| #define regVCN_UMSCH_MAILBOX1_BASE_IDX 1 |
| #define regVCN_UMSCH_MAILBOX_RESP1 0x074c |
| #define regVCN_UMSCH_MAILBOX_RESP1_BASE_IDX 1 |
| #define regVCN_UMSCH_MAILBOX2 0x074d |
| #define regVCN_UMSCH_MAILBOX2_BASE_IDX 1 |
| #define regVCN_UMSCH_MAILBOX_RESP2 0x074e |
| #define regVCN_UMSCH_MAILBOX_RESP2_BASE_IDX 1 |
| #define regVCN_UMSCH_MAILBOX3 0x074f |
| #define regVCN_UMSCH_MAILBOX3_BASE_IDX 1 |
| #define regVCN_UMSCH_MAILBOX_RESP3 0x0750 |
| #define regVCN_UMSCH_MAILBOX_RESP3_BASE_IDX 1 |
| #define regVCN_UMSCH_SPARE_REGISTER0 0x0751 |
| #define regVCN_UMSCH_SPARE_REGISTER0_BASE_IDX 1 |
| #define regVCN_UMSCH_SPARE_REGISTER1 0x0752 |
| #define regVCN_UMSCH_SPARE_REGISTER1_BASE_IDX 1 |
| #define regVCN_UMSCH_SPARE_REGISTER2 0x0753 |
| #define regVCN_UMSCH_SPARE_REGISTER2_BASE_IDX 1 |
| #define regVCN_UMSCH_SPARE_REGISTER3 0x0754 |
| #define regVCN_UMSCH_SPARE_REGISTER3_BASE_IDX 1 |
| #define regVCN_UMSCH_SPARE_REGISTER4 0x0755 |
| #define regVCN_UMSCH_SPARE_REGISTER4_BASE_IDX 1 |
| #define regVCN_UMSCH_SPARE_REGISTER5 0x0756 |
| #define regVCN_UMSCH_SPARE_REGISTER5_BASE_IDX 1 |
| #define regVCN_UMSCH_SPARE_REGISTER6 0x0757 |
| #define regVCN_UMSCH_SPARE_REGISTER6_BASE_IDX 1 |
| #define regVCN_UMSCH_SPARE_REGISTER7 0x0758 |
| #define regVCN_UMSCH_SPARE_REGISTER7_BASE_IDX 1 |
| #define regVCN_UMSCH_MES_UTCL1_CNTL 0x0759 |
| #define regVCN_UMSCH_MES_UTCL1_CNTL_BASE_IDX 1 |
| #define regVCN_UMSCH_MES_BUSY 0x075a |
| #define regVCN_UMSCH_MES_BUSY_BASE_IDX 1 |
| #define regVCN_UMSCH_RB_BASE_LO 0x075b |
| #define regVCN_UMSCH_RB_BASE_LO_BASE_IDX 1 |
| #define regVCN_UMSCH_RB_BASE_HI 0x075c |
| #define regVCN_UMSCH_RB_BASE_HI_BASE_IDX 1 |
| #define regVCN_UMSCH_RB_SIZE 0x075d |
| #define regVCN_UMSCH_RB_SIZE_BASE_IDX 1 |
| #define regVCN_UMSCH_RB_RPTR 0x075e |
| #define regVCN_UMSCH_RB_RPTR_BASE_IDX 1 |
| #define regVCN_UMSCH_RB_WPTR 0x075f |
| #define regVCN_UMSCH_RB_WPTR_BASE_IDX 1 |
| #define regVCN_UMSCH_MASTINT_EN 0x0760 |
| #define regVCN_UMSCH_MASTINT_EN_BASE_IDX 1 |
| #define regVCN_UMSCH_IH_CTRL 0x0761 |
| #define regVCN_UMSCH_IH_CTRL_BASE_IDX 1 |
| #define regVCN_UMSCH_SYS_INT_EN 0x0762 |
| #define regVCN_UMSCH_SYS_INT_EN_BASE_IDX 1 |
| #define regVCN_UMSCH_SYS_INT_STATUS 0x0763 |
| #define regVCN_UMSCH_SYS_INT_STATUS_BASE_IDX 1 |
| #define regVCN_UMSCH_SYS_INT_ACK 0x0764 |
| #define regVCN_UMSCH_SYS_INT_ACK_BASE_IDX 1 |
| #define regVCN_UMSCH_SYS_INT_SRC 0x0765 |
| #define regVCN_UMSCH_SYS_INT_SRC_BASE_IDX 1 |
| #define regVCN_UMSCH_IH_CTX_CTRL 0x0766 |
| #define regVCN_UMSCH_IH_CTX_CTRL_BASE_IDX 1 |
| #define regUVD_UMSCH_FORCE 0x076b |
| #define regUVD_UMSCH_FORCE_BASE_IDX 1 |
| #define regUMSCH_MES_RESET_CTRL 0x0770 |
| #define regUMSCH_MES_RESET_CTRL_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_vcn_cprs64dec |
| // base address: 0x21600 |
| #define regVCN_MES_PRGRM_CNTR_START 0x0780 |
| #define regVCN_MES_PRGRM_CNTR_START_BASE_IDX 1 |
| #define regVCN_MES_INTR_ROUTINE_START 0x0781 |
| #define regVCN_MES_INTR_ROUTINE_START_BASE_IDX 1 |
| #define regVCN_MES_MTVEC_LO 0x0781 |
| #define regVCN_MES_MTVEC_LO_BASE_IDX 1 |
| #define regVCN_MES_INTR_ROUTINE_START_HI 0x0782 |
| #define regVCN_MES_INTR_ROUTINE_START_HI_BASE_IDX 1 |
| #define regVCN_MES_MTVEC_HI 0x0782 |
| #define regVCN_MES_MTVEC_HI_BASE_IDX 1 |
| #define regVCN_MES_CNTL 0x0787 |
| #define regVCN_MES_CNTL_BASE_IDX 1 |
| #define regVCN_MES_PIPE_PRIORITY_CNTS 0x0788 |
| #define regVCN_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 |
| #define regVCN_MES_PIPE0_PRIORITY 0x0789 |
| #define regVCN_MES_PIPE0_PRIORITY_BASE_IDX 1 |
| #define regVCN_MES_PIPE1_PRIORITY 0x078a |
| #define regVCN_MES_PIPE1_PRIORITY_BASE_IDX 1 |
| #define regVCN_MES_PIPE2_PRIORITY 0x078b |
| #define regVCN_MES_PIPE2_PRIORITY_BASE_IDX 1 |
| #define regVCN_MES_PIPE3_PRIORITY 0x078c |
| #define regVCN_MES_PIPE3_PRIORITY_BASE_IDX 1 |
| #define regVCN_MES_HEADER_DUMP 0x078d |
| #define regVCN_MES_HEADER_DUMP_BASE_IDX 1 |
| #define regVCN_MES_MIE_LO 0x078e |
| #define regVCN_MES_MIE_LO_BASE_IDX 1 |
| #define regVCN_MES_MIE_HI 0x078f |
| #define regVCN_MES_MIE_HI_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT 0x0790 |
| #define regVCN_MES_INTERRUPT_BASE_IDX 1 |
| #define regVCN_MES_SCRATCH_INDEX 0x0791 |
| #define regVCN_MES_SCRATCH_INDEX_BASE_IDX 1 |
| #define regVCN_MES_SCRATCH_DATA 0x0792 |
| #define regVCN_MES_SCRATCH_DATA_BASE_IDX 1 |
| #define regVCN_MES_INSTR_PNTR 0x0793 |
| #define regVCN_MES_INSTR_PNTR_BASE_IDX 1 |
| #define regVCN_MES_MSCRATCH_HI 0x0794 |
| #define regVCN_MES_MSCRATCH_HI_BASE_IDX 1 |
| #define regVCN_MES_MSCRATCH_LO 0x0795 |
| #define regVCN_MES_MSCRATCH_LO_BASE_IDX 1 |
| #define regVCN_MES_MSTATUS_LO 0x0796 |
| #define regVCN_MES_MSTATUS_LO_BASE_IDX 1 |
| #define regVCN_MES_MSTATUS_HI 0x0797 |
| #define regVCN_MES_MSTATUS_HI_BASE_IDX 1 |
| #define regVCN_MES_MEPC_LO 0x0798 |
| #define regVCN_MES_MEPC_LO_BASE_IDX 1 |
| #define regVCN_MES_MEPC_HI 0x0799 |
| #define regVCN_MES_MEPC_HI_BASE_IDX 1 |
| #define regVCN_MES_MCAUSE_LO 0x079a |
| #define regVCN_MES_MCAUSE_LO_BASE_IDX 1 |
| #define regVCN_MES_MCAUSE_HI 0x079b |
| #define regVCN_MES_MCAUSE_HI_BASE_IDX 1 |
| #define regVCN_MES_MBADADDR_LO 0x079c |
| #define regVCN_MES_MBADADDR_LO_BASE_IDX 1 |
| #define regVCN_MES_MBADADDR_HI 0x079d |
| #define regVCN_MES_MBADADDR_HI_BASE_IDX 1 |
| #define regVCN_MES_MIP_LO 0x079e |
| #define regVCN_MES_MIP_LO_BASE_IDX 1 |
| #define regVCN_MES_MIP_HI 0x079f |
| #define regVCN_MES_MIP_HI_BASE_IDX 1 |
| #define regVCN_MES_IC_OP_CNTL 0x07a0 |
| #define regVCN_MES_IC_OP_CNTL_BASE_IDX 1 |
| #define regVCN_MES_MCYCLE_LO 0x07a6 |
| #define regVCN_MES_MCYCLE_LO_BASE_IDX 1 |
| #define regVCN_MES_MCYCLE_HI 0x07a7 |
| #define regVCN_MES_MCYCLE_HI_BASE_IDX 1 |
| #define regVCN_MES_MTIME_LO 0x07a8 |
| #define regVCN_MES_MTIME_LO_BASE_IDX 1 |
| #define regVCN_MES_MTIME_HI 0x07a9 |
| #define regVCN_MES_MTIME_HI_BASE_IDX 1 |
| #define regVCN_MES_MINSTRET_LO 0x07aa |
| #define regVCN_MES_MINSTRET_LO_BASE_IDX 1 |
| #define regVCN_MES_MINSTRET_HI 0x07ab |
| #define regVCN_MES_MINSTRET_HI_BASE_IDX 1 |
| #define regVCN_MES_MISA_LO 0x07ac |
| #define regVCN_MES_MISA_LO_BASE_IDX 1 |
| #define regVCN_MES_MISA_HI 0x07ad |
| #define regVCN_MES_MISA_HI_BASE_IDX 1 |
| #define regVCN_MES_MVENDORID_LO 0x07ae |
| #define regVCN_MES_MVENDORID_LO_BASE_IDX 1 |
| #define regVCN_MES_MVENDORID_HI 0x07af |
| #define regVCN_MES_MVENDORID_HI_BASE_IDX 1 |
| #define regVCN_MES_MARCHID_LO 0x07b0 |
| #define regVCN_MES_MARCHID_LO_BASE_IDX 1 |
| #define regVCN_MES_MARCHID_HI 0x07b1 |
| #define regVCN_MES_MARCHID_HI_BASE_IDX 1 |
| #define regVCN_MES_MIMPID_LO 0x07b2 |
| #define regVCN_MES_MIMPID_LO_BASE_IDX 1 |
| #define regVCN_MES_MIMPID_HI 0x07b3 |
| #define regVCN_MES_MIMPID_HI_BASE_IDX 1 |
| #define regVCN_MES_MHARTID_LO 0x07b4 |
| #define regVCN_MES_MHARTID_LO_BASE_IDX 1 |
| #define regVCN_MES_MHARTID_HI 0x07b5 |
| #define regVCN_MES_MHARTID_HI_BASE_IDX 1 |
| #define regVCN_MES_DC_BASE_CNTL 0x07b6 |
| #define regVCN_MES_DC_BASE_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_OP_CNTL 0x07b7 |
| #define regVCN_MES_DC_OP_CNTL_BASE_IDX 1 |
| #define regVCN_MES_MTIMECMP_LO 0x07b8 |
| #define regVCN_MES_MTIMECMP_LO_BASE_IDX 1 |
| #define regVCN_MES_MTIMECMP_HI 0x07b9 |
| #define regVCN_MES_MTIMECMP_HI_BASE_IDX 1 |
| #define regVCN_MES_GP0_LO 0x07c3 |
| #define regVCN_MES_GP0_LO_BASE_IDX 1 |
| #define regVCN_MES_GP0_HI 0x07c4 |
| #define regVCN_MES_GP0_HI_BASE_IDX 1 |
| #define regVCN_MES_GP1_LO 0x07c5 |
| #define regVCN_MES_GP1_LO_BASE_IDX 1 |
| #define regVCN_MES_GP1_HI 0x07c6 |
| #define regVCN_MES_GP1_HI_BASE_IDX 1 |
| #define regVCN_MES_GP2_LO 0x07c7 |
| #define regVCN_MES_GP2_LO_BASE_IDX 1 |
| #define regVCN_MES_GP2_HI 0x07c8 |
| #define regVCN_MES_GP2_HI_BASE_IDX 1 |
| #define regVCN_MES_GP3_LO 0x07c9 |
| #define regVCN_MES_GP3_LO_BASE_IDX 1 |
| #define regVCN_MES_GP3_HI 0x07ca |
| #define regVCN_MES_GP3_HI_BASE_IDX 1 |
| #define regVCN_MES_GP4_LO 0x07cb |
| #define regVCN_MES_GP4_LO_BASE_IDX 1 |
| #define regVCN_MES_GP4_HI 0x07cc |
| #define regVCN_MES_GP4_HI_BASE_IDX 1 |
| #define regVCN_MES_GP5_LO 0x07cd |
| #define regVCN_MES_GP5_LO_BASE_IDX 1 |
| #define regVCN_MES_GP5_HI 0x07ce |
| #define regVCN_MES_GP5_HI_BASE_IDX 1 |
| #define regVCN_MES_GP6_LO 0x07cf |
| #define regVCN_MES_GP6_LO_BASE_IDX 1 |
| #define regVCN_MES_GP6_HI 0x07d0 |
| #define regVCN_MES_GP6_HI_BASE_IDX 1 |
| #define regVCN_MES_GP7_LO 0x07d1 |
| #define regVCN_MES_GP7_LO_BASE_IDX 1 |
| #define regVCN_MES_GP7_HI 0x07d2 |
| #define regVCN_MES_GP7_HI_BASE_IDX 1 |
| #define regVCN_MES_GP8_LO 0x07d3 |
| #define regVCN_MES_GP8_LO_BASE_IDX 1 |
| #define regVCN_MES_GP8_HI 0x07d4 |
| #define regVCN_MES_GP8_HI_BASE_IDX 1 |
| #define regVCN_MES_GP9_LO 0x07d5 |
| #define regVCN_MES_GP9_LO_BASE_IDX 1 |
| #define regVCN_MES_GP9_HI 0x07d6 |
| #define regVCN_MES_GP9_HI_BASE_IDX 1 |
| #define regVCN_MES_DM_INDEX_ADDR 0x0800 |
| #define regVCN_MES_DM_INDEX_ADDR_BASE_IDX 1 |
| #define regVCN_MES_DM_INDEX_DATA 0x0801 |
| #define regVCN_MES_DM_INDEX_DATA_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_BASE0_LO 0x0803 |
| #define regVCN_MES_LOCAL_BASE0_LO_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_BASE0_HI 0x0804 |
| #define regVCN_MES_LOCAL_BASE0_HI_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_MASK0_LO 0x0805 |
| #define regVCN_MES_LOCAL_MASK0_LO_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_MASK0_HI 0x0806 |
| #define regVCN_MES_LOCAL_MASK0_HI_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_APERTURE 0x0807 |
| #define regVCN_MES_LOCAL_APERTURE_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_INSTR_BASE_LO 0x0808 |
| #define regVCN_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_INSTR_BASE_HI 0x0809 |
| #define regVCN_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_INSTR_MASK_LO 0x080a |
| #define regVCN_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_INSTR_MASK_HI 0x080b |
| #define regVCN_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_INSTR_APERTURE 0x080c |
| #define regVCN_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_SCRATCH_APERTURE 0x080d |
| #define regVCN_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_SCRATCH_BASE_LO 0x080e |
| #define regVCN_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 |
| #define regVCN_MES_LOCAL_SCRATCH_BASE_HI 0x080f |
| #define regVCN_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 |
| #define regVCN_MES_PERFCOUNT_CNTL 0x0819 |
| #define regVCN_MES_PERFCOUNT_CNTL_BASE_IDX 1 |
| #define regVCN_MES_PENDING_INTERRUPT 0x081a |
| #define regVCN_MES_PENDING_INTERRUPT_BASE_IDX 1 |
| #define regVCN_MES_PRGRM_CNTR_START_HI 0x081d |
| #define regVCN_MES_PRGRM_CNTR_START_HI_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_16 0x081f |
| #define regVCN_MES_INTERRUPT_DATA_16_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_17 0x0820 |
| #define regVCN_MES_INTERRUPT_DATA_17_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_18 0x0821 |
| #define regVCN_MES_INTERRUPT_DATA_18_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_19 0x0822 |
| #define regVCN_MES_INTERRUPT_DATA_19_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_20 0x0823 |
| #define regVCN_MES_INTERRUPT_DATA_20_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_21 0x0824 |
| #define regVCN_MES_INTERRUPT_DATA_21_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_22 0x0825 |
| #define regVCN_MES_INTERRUPT_DATA_22_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_23 0x0826 |
| #define regVCN_MES_INTERRUPT_DATA_23_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_24 0x0827 |
| #define regVCN_MES_INTERRUPT_DATA_24_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_25 0x0828 |
| #define regVCN_MES_INTERRUPT_DATA_25_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_26 0x0829 |
| #define regVCN_MES_INTERRUPT_DATA_26_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_27 0x082a |
| #define regVCN_MES_INTERRUPT_DATA_27_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_28 0x082b |
| #define regVCN_MES_INTERRUPT_DATA_28_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_29 0x082c |
| #define regVCN_MES_INTERRUPT_DATA_29_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_30 0x082d |
| #define regVCN_MES_INTERRUPT_DATA_30_BASE_IDX 1 |
| #define regVCN_MES_INTERRUPT_DATA_31 0x082e |
| #define regVCN_MES_INTERRUPT_DATA_31_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE0_BASE 0x082f |
| #define regVCN_MES_DC_APERTURE0_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE0_MASK 0x0830 |
| #define regVCN_MES_DC_APERTURE0_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE0_CNTL 0x0831 |
| #define regVCN_MES_DC_APERTURE0_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE1_BASE 0x0832 |
| #define regVCN_MES_DC_APERTURE1_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE1_MASK 0x0833 |
| #define regVCN_MES_DC_APERTURE1_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE1_CNTL 0x0834 |
| #define regVCN_MES_DC_APERTURE1_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE2_BASE 0x0835 |
| #define regVCN_MES_DC_APERTURE2_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE2_MASK 0x0836 |
| #define regVCN_MES_DC_APERTURE2_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE2_CNTL 0x0837 |
| #define regVCN_MES_DC_APERTURE2_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE3_BASE 0x0838 |
| #define regVCN_MES_DC_APERTURE3_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE3_MASK 0x0839 |
| #define regVCN_MES_DC_APERTURE3_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE3_CNTL 0x083a |
| #define regVCN_MES_DC_APERTURE3_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE4_BASE 0x083b |
| #define regVCN_MES_DC_APERTURE4_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE4_MASK 0x083c |
| #define regVCN_MES_DC_APERTURE4_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE4_CNTL 0x083d |
| #define regVCN_MES_DC_APERTURE4_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE5_BASE 0x083e |
| #define regVCN_MES_DC_APERTURE5_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE5_MASK 0x083f |
| #define regVCN_MES_DC_APERTURE5_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE5_CNTL 0x0840 |
| #define regVCN_MES_DC_APERTURE5_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE6_BASE 0x0841 |
| #define regVCN_MES_DC_APERTURE6_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE6_MASK 0x0842 |
| #define regVCN_MES_DC_APERTURE6_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE6_CNTL 0x0843 |
| #define regVCN_MES_DC_APERTURE6_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE7_BASE 0x0844 |
| #define regVCN_MES_DC_APERTURE7_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE7_MASK 0x0845 |
| #define regVCN_MES_DC_APERTURE7_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE7_CNTL 0x0846 |
| #define regVCN_MES_DC_APERTURE7_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE8_BASE 0x0847 |
| #define regVCN_MES_DC_APERTURE8_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE8_MASK 0x0848 |
| #define regVCN_MES_DC_APERTURE8_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE8_CNTL 0x0849 |
| #define regVCN_MES_DC_APERTURE8_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE9_BASE 0x084a |
| #define regVCN_MES_DC_APERTURE9_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE9_MASK 0x084b |
| #define regVCN_MES_DC_APERTURE9_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE9_CNTL 0x084c |
| #define regVCN_MES_DC_APERTURE9_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE10_BASE 0x084d |
| #define regVCN_MES_DC_APERTURE10_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE10_MASK 0x084e |
| #define regVCN_MES_DC_APERTURE10_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE10_CNTL 0x084f |
| #define regVCN_MES_DC_APERTURE10_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE11_BASE 0x0850 |
| #define regVCN_MES_DC_APERTURE11_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE11_MASK 0x0851 |
| #define regVCN_MES_DC_APERTURE11_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE11_CNTL 0x0852 |
| #define regVCN_MES_DC_APERTURE11_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE12_BASE 0x0853 |
| #define regVCN_MES_DC_APERTURE12_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE12_MASK 0x0854 |
| #define regVCN_MES_DC_APERTURE12_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE12_CNTL 0x0855 |
| #define regVCN_MES_DC_APERTURE12_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE13_BASE 0x0856 |
| #define regVCN_MES_DC_APERTURE13_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE13_MASK 0x0857 |
| #define regVCN_MES_DC_APERTURE13_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE13_CNTL 0x0858 |
| #define regVCN_MES_DC_APERTURE13_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE14_BASE 0x0859 |
| #define regVCN_MES_DC_APERTURE14_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE14_MASK 0x085a |
| #define regVCN_MES_DC_APERTURE14_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE14_CNTL 0x085b |
| #define regVCN_MES_DC_APERTURE14_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE15_BASE 0x085c |
| #define regVCN_MES_DC_APERTURE15_BASE_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE15_MASK 0x085d |
| #define regVCN_MES_DC_APERTURE15_MASK_BASE_IDX 1 |
| #define regVCN_MES_DC_APERTURE15_CNTL 0x085e |
| #define regVCN_MES_DC_APERTURE15_CNTL_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_vcn_hypdec |
| // base address: 0x21a00 |
| #define regVCN_MES_IC_BASE_LO 0x08d0 |
| #define regVCN_MES_IC_BASE_LO_BASE_IDX 1 |
| #define regVCN_MES_MIBASE_LO 0x08d0 |
| #define regVCN_MES_MIBASE_LO_BASE_IDX 1 |
| #define regVCN_MES_IC_BASE_HI 0x08d1 |
| #define regVCN_MES_IC_BASE_HI_BASE_IDX 1 |
| #define regVCN_MES_MIBASE_HI 0x08d1 |
| #define regVCN_MES_MIBASE_HI_BASE_IDX 1 |
| #define regVCN_MES_IC_BASE_CNTL 0x08d2 |
| #define regVCN_MES_IC_BASE_CNTL_BASE_IDX 1 |
| #define regVCN_MES_DC_BASE_LO 0x08d4 |
| #define regVCN_MES_DC_BASE_LO_BASE_IDX 1 |
| #define regVCN_MES_MDBASE_LO 0x08d4 |
| #define regVCN_MES_MDBASE_LO_BASE_IDX 1 |
| #define regVCN_MES_DC_BASE_HI 0x08d5 |
| #define regVCN_MES_DC_BASE_HI_BASE_IDX 1 |
| #define regVCN_MES_MDBASE_HI 0x08d5 |
| #define regVCN_MES_MDBASE_HI_BASE_IDX 1 |
| #define regVCN_MES_MIBOUND_LO 0x08db |
| #define regVCN_MES_MIBOUND_LO_BASE_IDX 1 |
| #define regVCN_MES_MIBOUND_HI 0x08dc |
| #define regVCN_MES_MIBOUND_HI_BASE_IDX 1 |
| #define regVCN_MES_MDBOUND_LO 0x08dd |
| #define regVCN_MES_MDBOUND_LO_BASE_IDX 1 |
| #define regVCN_MES_MDBOUND_HI 0x08de |
| #define regVCN_MES_MDBOUND_HI_BASE_IDX 1 |
| |
| |
| // addressBlock: uvd_slmi_adpdec |
| // base address: 0x21c00 |
| #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x0900 |
| #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x0901 |
| #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x0902 |
| #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0903 |
| #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0904 |
| #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0905 |
| #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0906 |
| #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0907 |
| #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0908 |
| #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0909 |
| #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x090a |
| #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x090b |
| #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x090c |
| #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x090d |
| #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x090e |
| #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x090f |
| #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_NC_VMID 0x0910 |
| #define regUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 |
| #define regUVD_LMI_MMSCH_CTRL 0x0911 |
| #define regUVD_LMI_MMSCH_CTRL_BASE_IDX 1 |
| #define regUVD_MMSCH_LMI_STATUS 0x0912 |
| #define regUVD_MMSCH_LMI_STATUS_BASE_IDX 1 |
| #define regUMSCH_IOV_ACTIVE_FCN_ID 0x0920 |
| #define regUMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX 1 |
| #define regUVD_UMSCH_LMI_STATUS 0x0923 |
| #define regUVD_UMSCH_LMI_STATUS_BASE_IDX 1 |
| |
| |
| // addressBlock: uvdctxind |
| // base address: 0x0 |
| #define ixUVD_CGC_MEM_CTRL 0x0000 |
| #define ixUVD_CGC_CTRL2 0x0001 |
| #define ixUVD_CGC_MEM_DS_CTRL 0x0002 |
| #define ixUVD_CGC_MEM_SD_CTRL 0x0003 |
| #define ixUVD_SW_SCRATCH_00 0x0004 |
| #define ixUVD_SW_SCRATCH_01 0x0005 |
| #define ixUVD_SW_SCRATCH_02 0x0006 |
| #define ixUVD_SW_SCRATCH_03 0x0007 |
| #define ixUVD_SW_SCRATCH_04 0x0008 |
| #define ixUVD_SW_SCRATCH_05 0x0009 |
| #define ixUVD_SW_SCRATCH_06 0x000a |
| #define ixUVD_SW_SCRATCH_07 0x000b |
| #define ixUVD_SW_SCRATCH_08 0x000c |
| #define ixUVD_SW_SCRATCH_09 0x000d |
| #define ixUVD_SW_SCRATCH_10 0x000e |
| #define ixUVD_SW_SCRATCH_11 0x000f |
| #define ixUVD_SW_SCRATCH_12 0x0010 |
| #define ixUVD_SW_SCRATCH_13 0x0011 |
| #define ixUVD_SW_SCRATCH_14 0x0012 |
| #define ixUVD_SW_SCRATCH_15 0x0013 |
| #define ixUVD_IH_SEM_CTRL 0x001e |
| |
| |
| // addressBlock: lmi_adp_indirect |
| // base address: 0x0 |
| #define ixUVD_LMI_CRC0 0x0000 |
| #define ixUVD_LMI_CRC1 0x0001 |
| #define ixUVD_LMI_CRC2 0x0002 |
| #define ixUVD_LMI_CRC3 0x0003 |
| #define ixUVD_LMI_CRC10 0x000a |
| #define ixUVD_LMI_CRC11 0x000b |
| #define ixUVD_LMI_CRC12 0x000c |
| #define ixUVD_LMI_CRC13 0x000d |
| #define ixUVD_LMI_CRC14 0x000e |
| #define ixUVD_LMI_CRC15 0x000f |
| #define ixUVD_LMI_SWAP_CNTL2 0x0029 |
| #define ixUVD_MEMCHECK_SYS_INT_EN 0x0134 |
| #define ixUVD_MEMCHECK_SYS_INT_STAT 0x0135 |
| #define ixUVD_MEMCHECK_SYS_INT_ACK 0x0136 |
| #define ixUVD_MEMCHECK_VCPU_INT_EN 0x0137 |
| #define ixUVD_MEMCHECK_VCPU_INT_STAT 0x0138 |
| #define ixUVD_MEMCHECK_VCPU_INT_ACK 0x0139 |
| #define ixUVD_MEMCHECK2_SYS_INT_STAT 0x0140 |
| #define ixUVD_MEMCHECK2_SYS_INT_ACK 0x0141 |
| #define ixUVD_MEMCHECK2_VCPU_INT_STAT 0x0142 |
| #define ixUVD_MEMCHECK2_VCPU_INT_ACK 0x0143 |
| |
| |
| #endif |
