| // SPDX-License-Identifier: MIT |
| /* |
| * Copyright (C) 2021 Advanced Micro Devices, Inc. |
| * |
| * Authors: AMD |
| */ |
| |
| #ifndef __DCN303_DCCG_H__ |
| #define __DCN303_DCCG_H__ |
| |
| #include "dcn30/dcn30_dccg.h" |
| |
| |
| #define DCCG_REG_LIST_DCN3_03() \ |
| SR(DPPCLK_DTO_CTRL),\ |
| DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ |
| DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ |
| SR(REFCLK_CNTL) |
| |
| #define DCCG_MASK_SH_LIST_DCN3_03(mask_sh) \ |
| DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ |
| DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ |
| DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ |
| DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ |
| DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ |
| DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ |
| DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\ |
| DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh) |
| |
| #endif //__DCN303_DCCG_H__ |