blob: 52caba1b8cb57c21059ad5c8b65dd90e5fcec1b3 [file] [log] [blame]
/*
* Copyright (C) 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _dcn_3_0_1_OFFSET_HEADER
#define _dcn_3_0_1_OFFSET_HEADER
// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
// base address: 0x48
#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
// base address: 0x3b4
#define mmCRTC8_IDX 0x002d
#define mmCRTC8_IDX_BASE_IDX 1
#define mmCRTC8_DATA 0x002d
#define mmCRTC8_DATA_BASE_IDX 1
#define mmGENFC_WT 0x002e
#define mmGENFC_WT_BASE_IDX 1
#define mmGENS1 0x002e
#define mmGENS1_BASE_IDX 1
#define mmATTRDW 0x0030
#define mmATTRDW_BASE_IDX 1
#define mmATTRX 0x0030
#define mmATTRX_BASE_IDX 1
#define mmATTRDR 0x0030
#define mmATTRDR_BASE_IDX 1
#define mmGENMO_WT 0x0030
#define mmGENMO_WT_BASE_IDX 1
#define mmGENS0 0x0030
#define mmGENS0_BASE_IDX 1
#define mmGENENB 0x0030
#define mmGENENB_BASE_IDX 1
#define mmSEQ8_IDX 0x0031
#define mmSEQ8_IDX_BASE_IDX 1
#define mmSEQ8_DATA 0x0031
#define mmSEQ8_DATA_BASE_IDX 1
#define mmDAC_MASK 0x0031
#define mmDAC_MASK_BASE_IDX 1
#define mmDAC_R_INDEX 0x0031
#define mmDAC_R_INDEX_BASE_IDX 1
#define mmDAC_W_INDEX 0x0032
#define mmDAC_W_INDEX_BASE_IDX 1
#define mmDAC_DATA 0x0032
#define mmDAC_DATA_BASE_IDX 1
#define mmGENFC_RD 0x0032
#define mmGENFC_RD_BASE_IDX 1
#define mmGENMO_RD 0x0033
#define mmGENMO_RD_BASE_IDX 1
#define mmGRPH8_IDX 0x0033
#define mmGRPH8_IDX_BASE_IDX 1
#define mmGRPH8_DATA 0x0033
#define mmGRPH8_DATA_BASE_IDX 1
#define mmCRTC8_IDX_1 0x0035
#define mmCRTC8_IDX_1_BASE_IDX 1
#define mmCRTC8_DATA_1 0x0035
#define mmCRTC8_DATA_1_BASE_IDX 1
#define mmGENFC_WT_1 0x0036
#define mmGENFC_WT_1_BASE_IDX 1
#define mmGENS1_1 0x0036
#define mmGENS1_1_BASE_IDX 1
// addressBlock: dce_dc_hda_azcontroller_azdec
// base address: 0x0
#define mmCORB_WRITE_POINTER 0x0000
#define mmCORB_WRITE_POINTER_BASE_IDX 0
#define mmCORB_READ_POINTER 0x0000
#define mmCORB_READ_POINTER_BASE_IDX 0
#define mmCORB_CONTROL 0x0001
#define mmCORB_CONTROL_BASE_IDX 0
#define mmCORB_STATUS 0x0001
#define mmCORB_STATUS_BASE_IDX 0
#define mmCORB_SIZE 0x0001
#define mmCORB_SIZE_BASE_IDX 0
#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmRIRB_WRITE_POINTER 0x0004
#define mmRIRB_WRITE_POINTER_BASE_IDX 0
#define mmRESPONSE_INTERRUPT_COUNT 0x0004
#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
#define mmRIRB_CONTROL 0x0005
#define mmRIRB_CONTROL_BASE_IDX 0
#define mmRIRB_STATUS 0x0005
#define mmRIRB_STATUS_BASE_IDX 0
#define mmRIRB_SIZE 0x0005
#define mmRIRB_SIZE_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_STATUS 0x0008
#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_hda_azendpoint_azdec
// base address: 0x0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
// addressBlock: dce_dc_hda_azinputendpoint_azdec
// base address: 0x0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
// addressBlock: dce_dc_mmhubbub_vga_dispdec
// base address: 0x0
#define mmVGA_RENDER_CONTROL 0x0000
#define mmVGA_RENDER_CONTROL_BASE_IDX 1
#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
#define mmVGA_MODE_CONTROL 0x0002
#define mmVGA_MODE_CONTROL_BASE_IDX 1
#define mmVGA_SURFACE_PITCH_SELECT 0x0003
#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
#define mmVGA_HDP_CONTROL 0x000a
#define mmVGA_HDP_CONTROL_BASE_IDX 1
#define mmVGA_CACHE_CONTROL 0x000b
#define mmVGA_CACHE_CONTROL_BASE_IDX 1
#define mmD1VGA_CONTROL 0x000c
#define mmD1VGA_CONTROL_BASE_IDX 1
#define mmD2VGA_CONTROL 0x000e
#define mmD2VGA_CONTROL_BASE_IDX 1
#define mmVGA_STATUS 0x0010
#define mmVGA_STATUS_BASE_IDX 1
#define mmVGA_INTERRUPT_CONTROL 0x0011
#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
#define mmVGA_STATUS_CLEAR 0x0012
#define mmVGA_STATUS_CLEAR_BASE_IDX 1
#define mmVGA_INTERRUPT_STATUS 0x0013
#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
#define mmVGA_MAIN_CONTROL 0x0014
#define mmVGA_MAIN_CONTROL_BASE_IDX 1
#define mmVGA_TEST_CONTROL 0x0015
#define mmVGA_TEST_CONTROL_BASE_IDX 1
#define mmVGA_QOS_CTRL 0x0018
#define mmVGA_QOS_CTRL_BASE_IDX 1
#define mmD3VGA_CONTROL 0x0038
#define mmD3VGA_CONTROL_BASE_IDX 1
#define mmD4VGA_CONTROL 0x0039
#define mmD4VGA_CONTROL_BASE_IDX 1
#define mmD5VGA_CONTROL 0x003a
#define mmD5VGA_CONTROL_BASE_IDX 1
#define mmD6VGA_CONTROL 0x003b
#define mmD6VGA_CONTROL_BASE_IDX 1
#define mmVGA_SOURCE_SELECT 0x003c
#define mmVGA_SOURCE_SELECT_BASE_IDX 1
// addressBlock: dce_dc_dccg_dccg_dispdec
// base address: 0x0
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDP_DTO_DBUF_EN 0x0044
#define mmDP_DTO_DBUF_EN_BASE_IDX 1
#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmREFCLK_CNTL 0x0049
#define mmREFCLK_CNTL_BASE_IDX 1
#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL2 0x004e
#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
#define mmDCCG_DS_DTO_INCR 0x0053
#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
#define mmDCCG_DS_DTO_MODULO 0x0054
#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
#define mmDCCG_DS_CNTL 0x0055
#define mmDCCG_DS_CNTL_BASE_IDX 1
#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
#define mmDPREFCLK_CNTL 0x0058
#define mmDPREFCLK_CNTL_BASE_IDX 1
#define mmDCE_VERSION 0x005e
#define mmDCE_VERSION_BASE_IDX 1
#define mmDCCG_GTC_CNTL 0x0060
#define mmDCCG_GTC_CNTL_BASE_IDX 1
#define mmDCCG_GTC_DTO_INCR 0x0061
#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
#define mmDCCG_GTC_DTO_MODULO 0x0062
#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
#define mmDCCG_GTC_CURRENT 0x0063
#define mmDCCG_GTC_CURRENT_BASE_IDX 1
#define mmDSCCLK0_DTO_PARAM 0x006c
#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1
#define mmDSCCLK1_DTO_PARAM 0x006d
#define mmDSCCLK1_DTO_PARAM_BASE_IDX 1
#define mmDSCCLK2_DTO_PARAM 0x006e
#define mmDSCCLK2_DTO_PARAM_BASE_IDX 1
#define mmMILLISECOND_TIME_BASE_DIV 0x0070
#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL 0x0073
#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL 0x0074
#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076
#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_CAC_STATUS 0x0077
#define mmDCCG_CAC_STATUS_BASE_IDX 1
#define mmMICROSECOND_TIME_BASE_DIV 0x007b
#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_DISP_CNTL_REG 0x007f
#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
#define mmOTG0_PIXEL_RATE_CNTL 0x0080
#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO0_PHASE 0x0081
#define mmDP_DTO0_PHASE_BASE_IDX 1
#define mmDP_DTO0_MODULO 0x0082
#define mmDP_DTO0_MODULO_BASE_IDX 1
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG1_PIXEL_RATE_CNTL 0x0084
#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO1_PHASE 0x0085
#define mmDP_DTO1_PHASE_BASE_IDX 1
#define mmDP_DTO1_MODULO 0x0086
#define mmDP_DTO1_MODULO_BASE_IDX 1
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG2_PIXEL_RATE_CNTL 0x0088
#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO2_PHASE 0x0089
#define mmDP_DTO2_PHASE_BASE_IDX 1
#define mmDP_DTO2_MODULO 0x008a
#define mmDP_DTO2_MODULO_BASE_IDX 1
#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b
#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG3_PIXEL_RATE_CNTL 0x008c
#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO3_PHASE 0x008d
#define mmDP_DTO3_PHASE_BASE_IDX 1
#define mmDP_DTO3_MODULO 0x008e
#define mmDP_DTO3_MODULO_BASE_IDX 1
#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f
#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098
#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDPPCLK0_DTO_PARAM 0x0099
#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1
#define mmDPPCLK1_DTO_PARAM 0x009a
#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1
#define mmDPPCLK2_DTO_PARAM 0x009b
#define mmDPPCLK2_DTO_PARAM_BASE_IDX 1
#define mmDPPCLK3_DTO_PARAM 0x009c
#define mmDPPCLK3_DTO_PARAM_BASE_IDX 1
#define mmDCCG_CAC_STATUS2 0x009f
#define mmDCCG_CAC_STATUS2_BASE_IDX 1
#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
#define mmDCCG_SOFT_RESET 0x00a6
#define mmDCCG_SOFT_RESET_BASE_IDX 1
#define mmDSCCLK_DTO_CTRL 0x00a7
#define mmDSCCLK_DTO_CTRL_BASE_IDX 1
#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1
#define mmDPPCLK_DTO_CTRL 0x00b6
#define mmDPPCLK_DTO_CTRL_BASE_IDX 1
#define mmDCCG_VSYNC_CNT_CTRL 0x00b8
#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1
#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9
#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1
#define mmFORCE_SYMCLK_DISABLE 0x00ba
#define mmFORCE_SYMCLK_DISABLE_BASE_IDX 1
#define mmPHYASYMCLK_CLOCK_CNTL 0x0052
#define mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2
#define mmPHYBSYMCLK_CLOCK_CNTL 0x0053
#define mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2
#define mmPHYCSYMCLK_CLOCK_CNTL 0x0054
#define mmPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2
#define mmPHYDSYMCLK_CLOCK_CNTL 0x0055
#define mmPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
// base address: 0x0
#define mmDENTIST_DISPCLK_CNTL 0x0064
#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
// base address: 0x0
#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000
#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002
#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CNTL 0x0003
#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004
#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_HI 0x0007
#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_LOW 0x0008
#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
// base address: 0x30
#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c
#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e
#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CNTL 0x000f
#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010
#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_HI 0x0013
#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_LOW 0x0014
#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmu_dc_pg_dispdec
// base address: 0x0
#define mmDOMAIN0_PG_CONFIG 0x0080
#define mmDOMAIN0_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN0_PG_STATUS 0x0081
#define mmDOMAIN0_PG_STATUS_BASE_IDX 2
#define mmDOMAIN1_PG_CONFIG 0x0082
#define mmDOMAIN1_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN1_PG_STATUS 0x0083
#define mmDOMAIN1_PG_STATUS_BASE_IDX 2
#define mmDOMAIN2_PG_CONFIG 0x0084
#define mmDOMAIN2_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN2_PG_STATUS 0x0085
#define mmDOMAIN2_PG_STATUS_BASE_IDX 2
#define mmDOMAIN3_PG_CONFIG 0x0086
#define mmDOMAIN3_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN3_PG_STATUS 0x0087
#define mmDOMAIN3_PG_STATUS_BASE_IDX 2
#define mmDOMAIN4_PG_CONFIG 0x0088
#define mmDOMAIN4_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN4_PG_STATUS 0x0089
#define mmDOMAIN4_PG_STATUS_BASE_IDX 2
#define mmDOMAIN5_PG_CONFIG 0x008a
#define mmDOMAIN5_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN5_PG_STATUS 0x008b
#define mmDOMAIN5_PG_STATUS_BASE_IDX 2
#define mmDOMAIN6_PG_CONFIG 0x008c
#define mmDOMAIN6_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN6_PG_STATUS 0x008d
#define mmDOMAIN6_PG_STATUS_BASE_IDX 2
#define mmDOMAIN7_PG_CONFIG 0x008e
#define mmDOMAIN7_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN7_PG_STATUS 0x008f
#define mmDOMAIN7_PG_STATUS_BASE_IDX 2
#define mmDOMAIN16_PG_CONFIG 0x00a1
#define mmDOMAIN16_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN16_PG_STATUS 0x00a2
#define mmDOMAIN16_PG_STATUS_BASE_IDX 2
#define mmDOMAIN17_PG_CONFIG 0x00a3
#define mmDOMAIN17_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN17_PG_STATUS 0x00a4
#define mmDOMAIN17_PG_STATUS_BASE_IDX 2
#define mmDOMAIN18_PG_CONFIG 0x00a5
#define mmDOMAIN18_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN18_PG_STATUS 0x00a6
#define mmDOMAIN18_PG_STATUS_BASE_IDX 2
#define mmDCPG_INTERRUPT_STATUS 0x00ad
#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCPG_INTERRUPT_STATUS_2 0x00ae
#define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX 2
#define mmDCPG_INTERRUPT_CONTROL_1 0x00af
#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2
#define mmDCPG_INTERRUPT_CONTROL_2 0x00b0
#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2
#define mmDCPG_INTERRUPT_CONTROL_3 0x00b1
#define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2
#define mmDC_IP_REQUEST_CNTL 0x00b2
#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
// base address: 0x2f8
#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be
#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0
#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CNTL 0x00c1
#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2
#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_HI 0x00c5
#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_LOW 0x00c6
#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmu_dmu_misc_dispdec
// base address: 0x0
#define mmCC_DC_PIPE_DIS 0x00ca
#define mmCC_DC_PIPE_DIS_BASE_IDX 2
#define mmDMU_CLK_CNTL 0x00cb
#define mmDMU_CLK_CNTL_BASE_IDX 2
#define mmDMU_MEM_PWR_CNTL 0x00cc
#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2
#define mmDMU_MISC_ALLOW_DS_FORCE 0x00d6
#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2
// addressBlock: dce_dc_dmu_dmcu_dispdec
// base address: 0x0
#define mmDMCU_CTRL 0x00da
#define mmDMCU_CTRL_BASE_IDX 2
#define mmDMCU_STATUS 0x00db
#define mmDMCU_STATUS_BASE_IDX 2
#define mmDMCU_PC_START_ADDR 0x00dc
#define mmDMCU_PC_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_START_ADDR 0x00dd
#define mmDMCU_FW_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_END_ADDR 0x00de
#define mmDMCU_FW_END_ADDR_BASE_IDX 2
#define mmDMCU_FW_ISR_START_ADDR 0x00df
#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_CS_HI 0x00e0
#define mmDMCU_FW_CS_HI_BASE_IDX 2
#define mmDMCU_FW_CS_LO 0x00e1
#define mmDMCU_FW_CS_LO_BASE_IDX 2
#define mmDMCU_RAM_ACCESS_CTRL 0x00e2
#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_WR_CTRL 0x00e3
#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_WR_DATA 0x00e4
#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
#define mmDMCU_ERAM_RD_CTRL 0x00e5
#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_RD_DATA 0x00e6
#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
#define mmDMCU_IRAM_WR_CTRL 0x00e7
#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
#define mmDMCU_IRAM_WR_DATA 0x00e8
#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
#define mmDMCU_IRAM_RD_CTRL 0x00e9
#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
#define mmDMCU_IRAM_RD_DATA 0x00ea
#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
#define mmDMCU_EVENT_TRIGGER 0x00eb
#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec
#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS 0x00ee
#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS_1 0x00ef
#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
#define mmDC_DMCU_SCRATCH 0x00f5
#define mmDC_DMCU_SCRATCH_BASE_IDX 2
#define mmDMCU_INT_CNT 0x00f6
#define mmDMCU_INT_CNT_BASE_IDX 2
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8
#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG1 0x00f9
#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG2 0x00fa
#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG3 0x00fb
#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
#define mmMASTER_COMM_CMD_REG 0x00fc
#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
#define mmMASTER_COMM_CNTL_REG 0x00fd
#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG1 0x00fe
#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG2 0x00ff
#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG3 0x0100
#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
#define mmSLAVE_COMM_CMD_REG 0x0101
#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
#define mmSLAVE_COMM_CNTL_REG 0x0102
#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105
#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106
#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107
#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108
#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109
#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114
#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119
#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2
#define mmDMCU_INT_CNT_CONTINUE 0x011c
#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS_2 0x011e
#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2
#define mmDMCU_INT_CNT_CONT2 0x0120
#define mmDMCU_INT_CNT_CONT2_BASE_IDX 2
#define mmDMCU_INT_CNT_CONT3 0x0121
#define mmDMCU_INT_CNT_CONT3_BASE_IDX 2
// addressBlock: dce_dc_dmu_ihc_dispdec
// base address: 0x0
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2
#define mmDC_GPU_TIMER_READ 0x0128
#define mmDC_GPU_TIMER_READ_BASE_IDX 2
#define mmDC_GPU_TIMER_READ_CNTL 0x0129
#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS 0x012a
#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b
#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c
#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d
#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e
#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f
#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130
#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131
#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132
#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133
#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134
#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135
#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136
#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137
#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138
#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139
#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a
#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b
#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c
#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d
#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e
#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f
#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140
#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141
#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142
#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE23 0x0145
#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE24 0x0146
#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE25 0x0147
#define mmDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2
#define mmDCCG_INTERRUPT_DEST 0x0148
#define mmDCCG_INTERRUPT_DEST_BASE_IDX 2
#define mmDMU_INTERRUPT_DEST 0x0149
#define mmDMU_INTERRUPT_DEST_BASE_IDX 2
#define mmDMU_INTERRUPT_DEST2 0x014a
#define mmDMU_INTERRUPT_DEST2_BASE_IDX 2
#define mmDCPG_INTERRUPT_DEST 0x014b
#define mmDCPG_INTERRUPT_DEST_BASE_IDX 2
#define mmDCPG_INTERRUPT_DEST2 0x014c
#define mmDCPG_INTERRUPT_DEST2_BASE_IDX 2
#define mmMMHUBBUB_INTERRUPT_DEST 0x014d
#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2
#define mmWB_INTERRUPT_DEST 0x014e
#define mmWB_INTERRUPT_DEST_BASE_IDX 2
#define mmDCHUB_INTERRUPT_DEST 0x014f
#define mmDCHUB_INTERRUPT_DEST_BASE_IDX 2
#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150
#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
#define mmDCHUB_INTERRUPT_DEST2 0x0151
#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX 2
#define mmDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152
#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
#define mmMPC_INTERRUPT_DEST 0x0153
#define mmMPC_INTERRUPT_DEST_BASE_IDX 2
#define mmOPP_INTERRUPT_DEST 0x0154
#define mmOPP_INTERRUPT_DEST_BASE_IDX 2
#define mmOPTC_INTERRUPT_DEST 0x0155
#define mmOPTC_INTERRUPT_DEST_BASE_IDX 2
#define mmOTG0_INTERRUPT_DEST 0x0156
#define mmOTG0_INTERRUPT_DEST_BASE_IDX 2
#define mmOTG1_INTERRUPT_DEST 0x0157
#define mmOTG1_INTERRUPT_DEST_BASE_IDX 2
#define mmOTG2_INTERRUPT_DEST 0x0158
#define mmOTG2_INTERRUPT_DEST_BASE_IDX 2
#define mmOTG3_INTERRUPT_DEST 0x0159
#define mmOTG3_INTERRUPT_DEST_BASE_IDX 2
#define mmOTG4_INTERRUPT_DEST 0x015a
#define mmOTG4_INTERRUPT_DEST_BASE_IDX 2
#define mmOTG5_INTERRUPT_DEST 0x015b
#define mmOTG5_INTERRUPT_DEST_BASE_IDX 2
#define mmDIG_INTERRUPT_DEST 0x015c
#define mmDIG_INTERRUPT_DEST_BASE_IDX 2
#define mmI2C_DDC_HPD_INTERRUPT_DEST 0x015d
#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2
#define mmDIO_INTERRUPT_DEST 0x015f
#define mmDIO_INTERRUPT_DEST_BASE_IDX 2
#define mmDCIO_INTERRUPT_DEST 0x0160
#define mmDCIO_INTERRUPT_DEST_BASE_IDX 2
#define mmHPD_INTERRUPT_DEST 0x0161
#define mmHPD_INTERRUPT_DEST_BASE_IDX 2
#define mmAZ_INTERRUPT_DEST 0x0162
#define mmAZ_INTERRUPT_DEST_BASE_IDX 2
#define mmAUX_INTERRUPT_DEST 0x0163
#define mmAUX_INTERRUPT_DEST_BASE_IDX 2
#define mmDSC_INTERRUPT_DEST 0x0164
#define mmDSC_INTERRUPT_DEST_BASE_IDX 2
// addressBlock: dce_dc_dmu_fgsec_dispdec
// base address: 0x0
#define mmDMCUB_RBBMIF_SEC_CNTL 0x017a
#define mmDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dmu_rbbmif_dispdec
// base address: 0x0
#define mmRBBMIF_TIMEOUT 0x017f
#define mmRBBMIF_TIMEOUT_BASE_IDX 2
#define mmRBBMIF_STATUS 0x0180
#define mmRBBMIF_STATUS_BASE_IDX 2
#define mmRBBMIF_STATUS_2 0x0181
#define mmRBBMIF_STATUS_2_BASE_IDX 2
#define mmRBBMIF_INT_STATUS 0x0182
#define mmRBBMIF_INT_STATUS_BASE_IDX 2
#define mmRBBMIF_TIMEOUT_DIS 0x0183
#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
#define mmRBBMIF_TIMEOUT_DIS_2 0x0184
#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2
#define mmRBBMIF_STATUS_FLAG 0x0185
#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
// addressBlock: dce_dc_dmu_dmcub_dispdec
// base address: 0x0
#define mmDMCUB_REGION0_OFFSET 0x018e
#define mmDMCUB_REGION0_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION0_OFFSET_HIGH 0x018f
#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION1_OFFSET 0x0190
#define mmDMCUB_REGION1_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION1_OFFSET_HIGH 0x0191
#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION2_OFFSET 0x0192
#define mmDMCUB_REGION2_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION2_OFFSET_HIGH 0x0193
#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION4_OFFSET 0x0196
#define mmDMCUB_REGION4_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION4_OFFSET_HIGH 0x0197
#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION5_OFFSET 0x0198
#define mmDMCUB_REGION5_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION5_OFFSET_HIGH 0x0199
#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION6_OFFSET 0x019a
#define mmDMCUB_REGION6_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION6_OFFSET_HIGH 0x019b
#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION7_OFFSET 0x019c
#define mmDMCUB_REGION7_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION7_OFFSET_HIGH 0x019d
#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION0_TOP_ADDRESS 0x019e
#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION1_TOP_ADDRESS 0x019f
#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION2_TOP_ADDRESS 0x01a0
#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION4_TOP_ADDRESS 0x01a1
#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION5_TOP_ADDRESS 0x01a2
#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION6_TOP_ADDRESS 0x01a3
#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION7_TOP_ADDRESS 0x01a4
#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5
#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6
#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7
#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8
#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9
#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa
#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab
#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac
#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad
#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae
#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af
#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0
#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1
#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2
#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3
#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4
#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW0_OFFSET 0x01b5
#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6
#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW1_OFFSET 0x01b7
#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8
#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW2_OFFSET 0x01b9
#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba
#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW3_OFFSET 0x01bb
#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc
#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW4_OFFSET 0x01bd
#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be
#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW5_OFFSET 0x01bf
#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0
#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW6_OFFSET 0x01c1
#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2
#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW7_OFFSET 0x01c3
#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4
#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_INTERRUPT_ENABLE 0x01c5
#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX 2
#define mmDMCUB_INTERRUPT_ACK 0x01c6
#define mmDMCUB_INTERRUPT_ACK_BASE_IDX 2
#define mmDMCUB_INTERRUPT_STATUS 0x01c7
#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX 2
#define mmDMCUB_INTERRUPT_TYPE 0x01c8
#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX 2
#define mmDMCUB_EXT_INTERRUPT_STATUS 0x01c9
#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDMCUB_EXT_INTERRUPT_CTXID 0x01ca
#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2
#define mmDMCUB_EXT_INTERRUPT_ACK 0x01cb
#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2
#define mmDMCUB_INST_FETCH_FAULT_ADDR 0x01cc
#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2
#define mmDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd
#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2
#define mmDMCUB_SEC_CNTL 0x01ce
#define mmDMCUB_SEC_CNTL_BASE_IDX 2
#define mmDMCUB_MEM_CNTL 0x01cf
#define mmDMCUB_MEM_CNTL_BASE_IDX 2
#define mmDMCUB_INBOX0_BASE_ADDRESS 0x01d0
#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_INBOX0_SIZE 0x01d1
#define mmDMCUB_INBOX0_SIZE_BASE_IDX 2
#define mmDMCUB_INBOX0_WPTR 0x01d2
#define mmDMCUB_INBOX0_WPTR_BASE_IDX 2
#define mmDMCUB_INBOX0_RPTR 0x01d3
#define mmDMCUB_INBOX0_RPTR_BASE_IDX 2
#define mmDMCUB_INBOX1_BASE_ADDRESS 0x01d4
#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_INBOX1_SIZE 0x01d5
#define mmDMCUB_INBOX1_SIZE_BASE_IDX 2
#define mmDMCUB_INBOX1_WPTR 0x01d6
#define mmDMCUB_INBOX1_WPTR_BASE_IDX 2
#define mmDMCUB_INBOX1_RPTR 0x01d7
#define mmDMCUB_INBOX1_RPTR_BASE_IDX 2
#define mmDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8
#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_OUTBOX0_SIZE 0x01d9
#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX 2
#define mmDMCUB_OUTBOX0_WPTR 0x01da
#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX 2
#define mmDMCUB_OUTBOX0_RPTR 0x01db
#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX 2
#define mmDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc
#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_OUTBOX1_SIZE 0x01dd
#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX 2
#define mmDMCUB_OUTBOX1_WPTR 0x01de
#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX 2
#define mmDMCUB_OUTBOX1_RPTR 0x01df
#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX 2
#define mmDMCUB_TIMER_TRIGGER0 0x01e0
#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX 2
#define mmDMCUB_TIMER_TRIGGER1 0x01e1
#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX 2
#define mmDMCUB_TIMER_WINDOW 0x01e2
#define mmDMCUB_TIMER_WINDOW_BASE_IDX 2
#define mmDMCUB_SCRATCH0 0x01e3
#define mmDMCUB_SCRATCH0_BASE_IDX 2
#define mmDMCUB_SCRATCH1 0x01e4
#define mmDMCUB_SCRATCH1_BASE_IDX 2
#define mmDMCUB_SCRATCH2 0x01e5
#define mmDMCUB_SCRATCH2_BASE_IDX 2
#define mmDMCUB_SCRATCH3 0x01e6
#define mmDMCUB_SCRATCH3_BASE_IDX 2
#define mmDMCUB_SCRATCH4 0x01e7
#define mmDMCUB_SCRATCH4_BASE_IDX 2
#define mmDMCUB_SCRATCH5 0x01e8
#define mmDMCUB_SCRATCH5_BASE_IDX 2
#define mmDMCUB_SCRATCH6 0x01e9
#define mmDMCUB_SCRATCH6_BASE_IDX 2
#define mmDMCUB_SCRATCH7 0x01ea
#define mmDMCUB_SCRATCH7_BASE_IDX 2
#define mmDMCUB_SCRATCH8 0x01eb
#define mmDMCUB_SCRATCH8_BASE_IDX 2
#define mmDMCUB_SCRATCH9 0x01ec
#define mmDMCUB_SCRATCH9_BASE_IDX 2
#define mmDMCUB_SCRATCH10 0x01ed
#define mmDMCUB_SCRATCH10_BASE_IDX 2
#define mmDMCUB_SCRATCH11 0x01ee
#define mmDMCUB_SCRATCH11_BASE_IDX 2
#define mmDMCUB_SCRATCH12 0x01ef
#define mmDMCUB_SCRATCH12_BASE_IDX 2
#define mmDMCUB_SCRATCH13 0x01f0
#define mmDMCUB_SCRATCH13_BASE_IDX 2
#define mmDMCUB_SCRATCH14 0x01f1
#define mmDMCUB_SCRATCH14_BASE_IDX 2
#define mmDMCUB_SCRATCH15 0x01f2
#define mmDMCUB_SCRATCH15_BASE_IDX 2
#define mmDMCUB_CNTL 0x01f6
#define mmDMCUB_CNTL_BASE_IDX 2
#define mmDMCUB_GPINT_DATAIN0 0x01f7
#define mmDMCUB_GPINT_DATAIN0_BASE_IDX 2
#define mmDMCUB_GPINT_DATAIN1 0x01f8
#define mmDMCUB_GPINT_DATAIN1_BASE_IDX 2
#define mmDMCUB_GPINT_DATAOUT 0x01f9
#define mmDMCUB_GPINT_DATAOUT_BASE_IDX 2
#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa
#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2
#define mmDMCUB_LS_WAKE_INT_ENABLE 0x01fb
#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2
#define mmDMCUB_MEM_PWR_CNTL 0x01fc
#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX 2
#define mmDMCUB_TIMER_CURRENT 0x01fd
#define mmDMCUB_TIMER_CURRENT_BASE_IDX 2
#define mmDMCUB_PROC_ID 0x01ff
#define mmDMCUB_PROC_ID_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
// base address: 0x0
#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x0272
#define mmMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
#define mmMCIF_WB_BUFMGR_STATUS 0x0274
#define mmMCIF_WB_BUFMGR_STATUS_BASE_IDX 2
#define mmMCIF_WB_BUF_PITCH 0x0275
#define mmMCIF_WB_BUF_PITCH_BASE_IDX 2
#define mmMCIF_WB_BUF_1_STATUS 0x0276
#define mmMCIF_WB_BUF_1_STATUS_BASE_IDX 2
#define mmMCIF_WB_BUF_1_STATUS2 0x0277
#define mmMCIF_WB_BUF_1_STATUS2_BASE_IDX 2
#define mmMCIF_WB_BUF_2_STATUS 0x0278
#define mmMCIF_WB_BUF_2_STATUS_BASE_IDX 2
#define mmMCIF_WB_BUF_2_STATUS2 0x0279
#define mmMCIF_WB_BUF_2_STATUS2_BASE_IDX 2
#define mmMCIF_WB_BUF_3_STATUS 0x027a
#define mmMCIF_WB_BUF_3_STATUS_BASE_IDX 2
#define mmMCIF_WB_BUF_3_STATUS2 0x027b
#define mmMCIF_WB_BUF_3_STATUS2_BASE_IDX 2
#define mmMCIF_WB_BUF_4_STATUS 0x027c
#define mmMCIF_WB_BUF_4_STATUS_BASE_IDX 2
#define mmMCIF_WB_BUF_4_STATUS2 0x027d
#define mmMCIF_WB_BUF_4_STATUS2_BASE_IDX 2
#define mmMCIF_WB_ARBITRATION_CONTROL 0x027e
#define mmMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
#define mmMCIF_WB_SCLK_CHANGE 0x027f
#define mmMCIF_WB_SCLK_CHANGE_BASE_IDX 2
#define mmMCIF_WB_TEST_DEBUG_INDEX 0x0280
#define mmMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmMCIF_WB_TEST_DEBUG_DATA 0x0281
#define mmMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2
#define mmMCIF_WB_BUF_1_ADDR_Y 0x0282
#define mmMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB_BUF_1_ADDR_C 0x0284
#define mmMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
#define mmMCIF_WB_BUF_2_ADDR_Y 0x0286
#define mmMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB_BUF_2_ADDR_C 0x0288
#define mmMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
#define mmMCIF_WB_BUF_3_ADDR_Y 0x028a
#define mmMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB_BUF_3_ADDR_C 0x028c
#define mmMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
#define mmMCIF_WB_BUF_4_ADDR_Y 0x028e
#define mmMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB_BUF_4_ADDR_C 0x0290
#define mmMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x0292
#define mmMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
#define mmMCIF_WB_NB_PSTATE_CONTROL 0x0293
#define mmMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
#define mmMCIF_WB_CLOCK_GATER_CONTROL 0x0294
#define mmMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
#define mmMCIF_WB_SELF_REFRESH_CONTROL 0x0296
#define mmMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
#define mmMULTI_LEVEL_QOS_CTRL 0x0297
#define mmMULTI_LEVEL_QOS_CTRL_BASE_IDX 2
#define mmMCIF_WB_BUF_LUMA_SIZE 0x0299
#define mmMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
#define mmMCIF_WB_BUF_CHROMA_SIZE 0x029a
#define mmMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b
#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c
#define mmMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d
#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e
#define mmMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f
#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0
#define mmMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1
#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2
#define mmMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_1_RESOLUTION 0x02a3
#define mmMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
#define mmMCIF_WB_BUF_2_RESOLUTION 0x02a4
#define mmMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
#define mmMCIF_WB_BUF_3_RESOLUTION 0x02a5
#define mmMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
#define mmMCIF_WB_BUF_4_RESOLUTION 0x02a6
#define mmMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7
#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2
#define mmMCIF_WB_VMID_CONTROL 0x02a8
#define mmMCIF_WB_VMID_CONTROL_BASE_IDX 2
#define mmMCIF_WB_MIN_TTO 0x02a9
#define mmMCIF_WB_MIN_TTO_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
// base address: 0x0
#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa
#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
#define mmMCIF_WB_WATERMARK 0x02ab
#define mmMCIF_WB_WATERMARK_BASE_IDX 2
#define mmMMHUBBUB_WARMUP_CONFIG 0x02ac
#define mmMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2
#define mmMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad
#define mmMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2
#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae
#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2
#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af
#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2
#define mmMMHUBBUB_WARMUP_ADDR_REGION 0x02b0
#define mmMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2
#define mmMMHUBBUB_MIN_TTO 0x02b1
#define mmMMHUBBUB_MIN_TTO_BASE_IDX 2
#define mmWBIF0_MISC_CTRL 0x0334
#define mmWBIF0_MISC_CTRL_BASE_IDX 2
#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335
#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336
#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmVGA_SRC_SPLIT_CNTL 0x033d
#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2
#define mmMMHUBBUB_MEM_PWR_STATUS 0x033e
#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2
#define mmMMHUBBUB_MEM_PWR_CNTL 0x033f
#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2
#define mmMMHUBBUB_CLOCK_CNTL 0x0340
#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2
#define mmMMHUBBUB_SOFT_RESET 0x0341
#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2
#define mmDMU_IF_ERR_STATUS 0x0345
#define mmDMU_IF_ERR_STATUS_BASE_IDX 2
#define mmMMHUBBUB_CLIENT_UNIT_ID 0x0346
#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2
#define mmMMHUBBUB_WARMUP_VMID_CONTROL 0x0348
#define mmMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
// base address: 0x0
#define mmMCIF_CONTROL 0x034a
#define mmMCIF_CONTROL_BASE_IDX 2
#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b
#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
// base address: 0xd48
#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x0352
#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x0353
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x0354
#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CNTL 0x0355
#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CNTL2 0x0356
#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0357
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0358
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_HI 0x0359
#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_LOW 0x035a
#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream0_dispdec
// base address: 0x0
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f
#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream1_dispdec
// base address: 0x8
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361
#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream2_dispdec
// base address: 0x10
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363
#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream3_dispdec
// base address: 0x18
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365
#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream4_dispdec
// base address: 0x20
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367
#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream5_dispdec
// base address: 0x28
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369
#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream6_dispdec
// base address: 0x30
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b
#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream7_dispdec
// base address: 0x38
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d
#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_az_misc_dispdec
// base address: 0x0
#define mmAZ_CLOCK_CNTL 0x0372
#define mmAZ_CLOCK_CNTL_BASE_IDX 2
// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
// base address: 0xde8
#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x037a
#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x037b
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x037c
#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CNTL 0x037d
#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CNTL2 0x037e
#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x037f
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0380
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_HI 0x0381
#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_LOW 0x0382
#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
// base address: 0x0
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
// base address: 0x18
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
// base address: 0x30
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
// base address: 0x48
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
// base address: 0x60
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
// base address: 0x78
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
// base address: 0x90
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
// base address: 0xa8
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0controller_dispdec
// base address: 0x0
#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2
#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
#define mmAZALIA_AUDIO_DTO 0x03c3
#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4
#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
#define mmAZALIA_SOCCLK_CONTROL 0x03c5
#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
#define mmAZALIA_DATA_DMA_CONTROL 0x03c7
#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_BDL_DMA_CONTROL 0x03c8
#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9
#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
#define mmAZALIA_CORB_DMA_CONTROL 0x03ca
#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2
#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3
#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9
#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da
#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db
#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc
#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd
#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de
#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df
#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0
#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1
#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2
#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL0 0x03e3
#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL1 0x03e4
#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL2 0x03e5
#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL3 0x03e6
#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
#define mmAZALIA_CRC0_RESULT 0x03e7
#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL0 0x03e8
#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL1 0x03e9
#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL2 0x03ea
#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL3 0x03eb
#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
#define mmAZALIA_CRC1_RESULT 0x03ec
#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
#define mmAZALIA_MEM_PWR_CTRL 0x03ee
#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
#define mmAZALIA_MEM_PWR_STATUS 0x03ef
#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0root_dispdec
// base address: 0x0
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415
#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416
#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417
#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418
#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419
#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a
#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b
#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream8_dispdec
// base address: 0x320
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427
#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream9_dispdec
// base address: 0x328
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429
#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream10_dispdec
// base address: 0x330
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b
#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream11_dispdec
// base address: 0x338
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d
#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream12_dispdec
// base address: 0x340
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f
#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream13_dispdec
// base address: 0x348
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431
#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream14_dispdec
// base address: 0x350
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433
#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream15_dispdec
// base address: 0x358
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435
#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
// base address: 0x0
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
// base address: 0x10
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
// base address: 0x20
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
// base address: 0x30
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
// base address: 0x40
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
// base address: 0x50
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
// base address: 0x60
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
// base address: 0x70
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
// base address: 0x0
#define mmDCHUBBUB_SDPIF_CFG0 0x048f
#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2
#define mmVM_REQUEST_PHYSICAL 0x0490
#define mmVM_REQUEST_PHYSICAL_BASE_IDX 2
#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491
#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2
#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492
#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2
#define mmDCN_VM_FB_LOCATION_BASE 0x0493
#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX 2
#define mmDCN_VM_FB_LOCATION_TOP 0x0494
#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX 2
#define mmDCN_VM_FB_OFFSET 0x0495
#define mmDCN_VM_FB_OFFSET_BASE_IDX 2
#define mmDCN_VM_AGP_BOT 0x0496
#define mmDCN_VM_AGP_BOT_BASE_IDX 2
#define mmDCN_VM_AGP_TOP 0x0497
#define mmDCN_VM_AGP_TOP_BASE_IDX 2
#define mmDCN_VM_AGP_BASE 0x0498
#define mmDCN_VM_AGP_BASE_BASE_IDX 2
#define mmDCN_VM_LOCAL_HBM_ADDRESS_START 0x0499
#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2
#define mmDCN_VM_LOCAL_HBM_ADDRESS_END 0x049a
#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2
#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x049b
#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04ba
#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04bb
#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_CFG1 0x04bf
#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_CFG2 0x04c0
#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
// base address: 0x0
#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf
#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef
#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0
#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCHUBBUB_CRC_CTRL 0x04f1
#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2
#define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2
#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2
#define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3
#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2
#define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4
#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2
#define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5
#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_hubbub_dispdec
// base address: 0x0
#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505
#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2
#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506
#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2
#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507
#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2
#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508
#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x050a
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x050f
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0514
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d
#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2
#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e
#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2
#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f
#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2
#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520
#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2
#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521
#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2
#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522
#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2
#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523
#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2
#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524
#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2
#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525
#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2
#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526
#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2
#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527
#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2
#define mmVTG0_CONTROL 0x0528
#define mmVTG0_CONTROL_BASE_IDX 2
#define mmVTG1_CONTROL 0x0529
#define mmVTG1_CONTROL_BASE_IDX 2
#define mmVTG2_CONTROL 0x052a
#define mmVTG2_CONTROL_BASE_IDX 2
#define mmVTG3_CONTROL 0x052b
#define mmVTG3_CONTROL_BASE_IDX 2
#define mmDCHUBBUB_SOFT_RESET 0x052e
#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2
#define mmDCHUBBUB_CLOCK_CNTL 0x052f
#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2
#define mmDCFCLK_CNTL 0x0530
#define mmDCFCLK_CNTL_BASE_IDX 2
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2
#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533
#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2
#define mmDCHUBBUB_CTRL_STATUS 0x0534
#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2
#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c
#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d
#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e
#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x053f
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0540
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0541
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0542
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0543
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0544
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0545
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0546
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_HOSTVM_CNTL 0x0547
#define mmDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2
#define mmFMON_CTRL 0x0548
#define mmFMON_CTRL_BASE_IDX 2
#define mmFMON_CTRL_1 0x0548
#define mmFMON_CTRL_1_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
// base address: 0x1534
#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x054d
#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x054e
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x054f
#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CNTL 0x0550
#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CNTL2 0x0551
#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0552
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0553
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_HI 0x0554
#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_LOW 0x0555
#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
// base address: 0x0
#define mmDCN_VM_CONTEXT0_CNTL 0x0559
#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_CNTL 0x0560
#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_CNTL 0x0567
#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_CNTL 0x056e
#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_CNTL 0x0575
#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_CNTL 0x057c
#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_CNTL 0x0583
#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_CNTL 0x058a
#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_CNTL 0x0591
#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_CNTL 0x0598
#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_CNTL 0x059f
#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_CNTL 0x05a6
#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_CNTL 0x05ad
#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_CNTL 0x05b4
#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_CNTL 0x05bb
#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_CNTL 0x05c2
#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_DEFAULT_ADDR_MSB 0x05c9
#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2
#define mmDCN_VM_DEFAULT_ADDR_LSB 0x05ca
#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2
#define mmDCN_VM_FAULT_CNTL 0x05cb
#define mmDCN_VM_FAULT_CNTL_BASE_IDX 2
#define mmDCN_VM_FAULT_STATUS 0x05cc
#define mmDCN_VM_FAULT_STATUS_BASE_IDX 2
#define mmDCN_VM_FAULT_ADDR_MSB 0x05cd
#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2
#define mmDCN_VM_FAULT_ADDR_LSB 0x05ce
#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
// base address: 0x0
#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5
#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6
#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7
#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP0_DCHUBP_CNTL 0x05f3
#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP0_HUBP_CLK_CNTL 0x05f4
#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x05f5
#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6
#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP0_HUBPREQ_DEBUG 0x05f7
#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
// base address: 0x0
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ0_VMID_SETTINGS_0 0x0609
#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x0629
#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062a
#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634
#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643
#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define mmHUBPREQ0_BLANK_OFFSET_0 0x0644
#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ0_BLANK_OFFSET_1 0x0645
#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ0_DST_DIMENSIONS 0x0646
#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ0_DST_AFTER_SCALER 0x0647
#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ0_PREFETCH_SETTINGS 0x0648
#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2
#define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x0649
#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064a
#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064b
#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064c
#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064d
#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x064e
#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_0 0x064f
#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_1 0x0650
#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0651
#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_0 0x0652
#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_1 0x0653
#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_2 0x0654
#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_3 0x0655
#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_4 0x0656
#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_5 0x0657
#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_6 0x0658
#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_7 0x0659
#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ0_PER_LINE_DELIVERY 0x065b
#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ0_CURSOR_SETTINGS 0x065c
#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e
#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_5 0x0663
#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_6 0x0664
#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_3 0x0665
#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_4 0x0666
#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_5 0x0667
#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_6 0x0668
#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
// base address: 0x0
#define mmHUBPRET0_HUBPRET_CONTROL 0x066c
#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE0 0x0671
#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE1 0x0672
#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_INTERRUPT 0x0673
#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674
#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675
#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
// base address: 0x0
#define mmCURSOR0_0_CURSOR_CONTROL 0x0678
#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_SIZE 0x067b
#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_POSITION 0x067c
#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d
#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e
#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f
#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680
#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681
#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682
#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683
#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_CNTL 0x0684
#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685
#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_STATUS 0x0686
#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687
#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_SW_DATA 0x0688
#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x1a74
#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x069d
#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x069e
#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x069f
#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CNTL 0x06a0
#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CNTL2 0x06a1
#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x06a2
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x06a3
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_HI 0x06a4
#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_LOW 0x06a5
#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
// base address: 0x370
#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1
#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2
#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3
#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP1_DCHUBP_CNTL 0x06cf
#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP1_HUBP_CLK_CNTL 0x06d0
#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x06d1
#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2
#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP1_HUBPREQ_DEBUG 0x06d3
#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
// base address: 0x370
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ1_VMID_SETTINGS_0 0x06e5
#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6
#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc
#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0705
#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0706
#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707
#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710
#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f
#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define mmHUBPREQ1_BLANK_OFFSET_0 0x0720
#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ1_BLANK_OFFSET_1 0x0721
#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ1_DST_DIMENSIONS 0x0722
#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ1_DST_AFTER_SCALER 0x0723
#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ1_PREFETCH_SETTINGS 0x0724
#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2
#define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0725
#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0726
#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0727
#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0728
#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0729
#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072a
#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072b
#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_1 0x072c
#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072d
#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_0 0x072e
#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_1 0x072f
#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0730
#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0731
#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0732
#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_5 0x0733
#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_6 0x0734
#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_7 0x0735
#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736
#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ1_PER_LINE_DELIVERY 0x0737
#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ1_CURSOR_SETTINGS 0x0738
#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2
#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739
#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a
#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_5 0x073f
#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_6 0x0740
#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_3 0x0741
#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_4 0x0742
#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_5 0x0743
#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_6 0x0744
#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
// base address: 0x370
#define mmHUBPRET1_HUBPRET_CONTROL 0x0748
#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749
#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a
#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE0 0x074d
#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE1 0x074e
#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_INTERRUPT 0x074f
#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750
#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751
#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
// base address: 0x370
#define mmCURSOR0_1_CURSOR_CONTROL 0x0754
#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_SIZE 0x0757
#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_POSITION 0x0758
#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759
#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a
#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b
#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c
#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d
#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e
#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f
#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_CNTL 0x0760
#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761
#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_STATUS 0x0762
#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763
#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_SW_DATA 0x0764
#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x1de4
#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0779
#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x077a
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x077b
#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CNTL 0x077c
#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CNTL2 0x077d
#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x077e
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x077f
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_HI 0x0780
#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_LOW 0x0781
#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
// base address: 0x6e0
#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x079d
#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP2_DCSURF_ADDR_CONFIG 0x079e
#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX