blob: 7155312326e8abd80524323f1754df35a9c976da [file] [log] [blame]
/*
*
* Copyright (C) 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef GMC_6_0_SH_MASK_H
#define GMC_6_0_SH_MASK_H
#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x00000004L
#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x00000002
#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x00004000L
#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0x0000000e
#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x00000080L
#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x00000007
#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x00000002L
#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x00000001
#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x00008000L
#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0x0000000f
#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x00000001L
#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x00000000
#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x00010000L
#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x00000010
#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x00003c00L
#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0x0000000a
#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x00000100L
#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x00000008
#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x00000020L
#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x00000005
#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x00000040L
#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x00000006
#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x00000200L
#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x00000009
#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x0000003cL
#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x00000002
#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x00000001L
#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x00000000
#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffffL
#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x00000000
#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x03f00000L
#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x00000014
#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0000fc00L
#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0x0000000a
#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x0000003fL
#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x00000000
#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000100L
#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000008
#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x00010000L
#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x00000010
#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x0000001fL
#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x00000000
#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffffL
#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x00000000
#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L
#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x00000010
#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L
#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0x0000000f
#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x0000003fL
#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x00000000
#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L
#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x00000011
#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0f000000L
#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x00000018
#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L
#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x00000012
#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00f80000L
#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x00000013
#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007c00L
#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0x0000000a
#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L
#define ATC_ATS_STATUS__BUSY__SHIFT 0x00000000
#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L
#define ATC_ATS_STATUS__CRASHED__SHIFT 0x00000001
#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L
#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000002
#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffffL
#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x00000000
#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x00000003L
#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x00000000
#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x00000004L
#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x00000002
#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x00000010L
#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x00000004
#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x0003f000L
#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0x0000000c
#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0x0ff00000L
#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x00000014
#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000L
#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x0000001c
#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x00000001L
#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x00000000
#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0x000000f0L
#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x00000004
#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L
#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000008
#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000L
#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x0000001e
#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x00000100L
#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x00000008
#define ATC_L1RD_STATUS__BUSY_MASK 0x00000001L
#define ATC_L1RD_STATUS__BUSY__SHIFT 0x00000000
#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x00000002L
#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000001
#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x0003f000L
#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0x0000000c
#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0x0ff00000L
#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x00000014
#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000L
#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x0000001c
#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x00000001L
#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x00000000
#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0x000000f0L
#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x00000004
#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L
#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000008
#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000L
#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x0000001e
#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x00000100L
#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x00000008
#define ATC_L1WR_STATUS__BUSY_MASK 0x00000001L
#define ATC_L1WR_STATUS__BUSY__SHIFT 0x00000000
#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x00000002L
#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000001
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x00000000
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000400L
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x0000000a
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000030L
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x00000004
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000800L
#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x0000000b
#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x0000003fL
#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x00000000
#define ATC_MISC_CG__ENABLE_MASK 0x00040000L
#define ATC_MISC_CG__ENABLE__SHIFT 0x00000012
#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x00000013
#define ATC_MISC_CG__OFFDLY_MASK 0x00000fc0L
#define ATC_MISC_CG__OFFDLY__SHIFT 0x00000006
#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0x0000ffffL
#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x00000000
#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x00000003L
#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x00000000
#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL
#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000
#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL
#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000
#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0x0000ffffL
#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x00000000
#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x00000003L
#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x00000000
#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL
#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000
#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL
#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000
#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000ffffL
#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x00000000
#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L
#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x0000001f
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x00000000
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0x0000000a
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0x0000000b
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0x0000000c
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0x0000000d
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0x0000000e
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0x0000000f
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x00000001
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x00000002
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x00000003
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x00000004
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x00000005
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x00000006
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x00000007
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x00000008
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L
#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x00000009
#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x0000001eL
#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x00000001
#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x003ff000L
#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0x0000000c
#define DLL_CNTL__DLL_RESET_TIME_MASK 0x000003ffL
#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x00000000
#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x01000000L
#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x00000018
#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x02000000L
#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x00000019
#define DLL_CNTL__PWR2_MODE_MASK 0x04000000L
#define DLL_CNTL__PWR2_MODE__SHIFT 0x0000001a
#define GMCON_DEBUG__GFX_CLEAR_MASK 0x00000002L
#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x00000001
#define GMCON_DEBUG__GFX_STALL_MASK 0x00000001L
#define GMCON_DEBUG__GFX_STALL__SHIFT 0x00000000
#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffcL
#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x00000002
#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0_MASK 0x00000007L
#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0__SHIFT 0x00000000
#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1_MASK 0x00000038L
#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1__SHIFT 0x00000003
#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x0000fc00L
#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0x0000000a
#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x20000000L
#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x0000001d
#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x10000000L
#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x0000001c
#define GMCON_MISC2__STCTRL_LPT_TARGET_MASK 0x0fff0000L
#define GMCON_MISC2__STCTRL_LPT_TARGET__SHIFT 0x00000010
#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0x0000003fL
#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x00000000
#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0x00000fc0L
#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x00000006
#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00fff000L
#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x0000000c
#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x30000000L
#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0000001c
#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x08000000L
#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x0000001b
#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x00000400L
#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0x0000000a
#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00000800L
#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x0000000b
#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0x0000f000L
#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0x0000000c
#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x02000000L
#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x00000019
#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x04000000L
#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x0000001a
#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x40000000L
#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x0000001e
#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x00060000L
#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x00000011
#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x00400000L
#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x00000016
#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x00200000L
#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x00000015
#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x01000000L
#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x00000018
#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x00800000L
#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x00000017
#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x00180000L
#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x00000013
#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x00010000L
#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x00000010
#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000L
#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x0000001c
#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x03000000L
#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x00000018
#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0x00000fffL
#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x00000000
#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0x0c000000L
#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x0000001a
#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0x00fff000L
#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0x0000000c
#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x00fc0000L
#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x00000012
#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0x3f000000L
#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x00000018
#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0x00000fc0L
#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x00000006
#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x0003f000L
#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x0000000c
#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x0000003fL
#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x00000000
#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffffL
#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x00000000
#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffffL
#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x00000000
#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000ffL
#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x00000000
#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0x0000000a
#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0x0000000b
#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x00000008
#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x00000009
#define GMCON_PGFSM_CONFIG__READ_MASK 0x00002000L
#define GMCON_PGFSM_CONFIG__READ__SHIFT 0x0000000d
#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000L
#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x0000001c
#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x07ffc000L
#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0x0000000e
#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x0000001b
#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x00001000L
#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0x0000000c
#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0x0f000000L
#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x00000018
#define GMCON_PGFSM_READ__READ_VALUE_MASK 0x00ffffffL
#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x00000000
#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000L
#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x0000001c
#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffffL
#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x00000000
#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x003ff000L
#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0x0000000c
#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000L
#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x00000016
#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L
#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x00000001
#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000ffcL
#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x00000002
#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L
#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x00000000
#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffffL
#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x00000000
#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003ffL
#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x00000000
#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000ffffL
#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x00000000
#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000L
#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x00000010
#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000ffffL
#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x00000000
#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000L
#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x00000010
#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0x0000ffffL
#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x00000000
#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000L
#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x00000010
#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0x0000ffffL
#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x00000000
#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000L
#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x00000010
#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0x0000ffffL
#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x00000000
#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000L
#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x00000010
#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0x0000000fL
#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x00000000
#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0x00000ff0L
#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x00000004
#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0x0ffff000L
#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0x0000000c
#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x01000000L
#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x00000018
#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x02000000L
#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x00000019
#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x04000000L
#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x0000001a
#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x08000000L
#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x0000001b
#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000L
#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x0000001c
#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000L
#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x0000001d
#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000L
#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x0000001e
#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000L
#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x0000001f
#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x00010000L
#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x00000010
#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x00020000L
#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x00000011
#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x00040000L
#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x00000012
#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x00080000L
#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x00000013
#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x00100000L
#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x00000014
#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x00200000L
#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x00000015
#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x00400000L
#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x00000016
#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x00800000L
#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x00000017
#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x00000003L
#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x00000000
#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0x0000000cL
#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x00000002
#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x00000030L
#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x00000004
#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0x000000c0L
#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x00000006
#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x00000300L
#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x00000008
#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0x00000c00L
#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0x0000000a
#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x00003000L
#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0x0000000c
#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0x0000c000L
#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0x0000000e
#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x01000000L
#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x00000018
#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x02000000L
#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x00000019
#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x04000000L
#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x0000001a
#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x08000000L
#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x0000001b
#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000L
#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x0000001c
#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000L
#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x0000001d
#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000L
#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x0000001e
#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000L
#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x0000001f
#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x00010000L
#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x00000010
#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x00020000L
#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x00000011
#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x00040000L
#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x00000012
#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x00080000L
#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x00000013
#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x00100000L
#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x00000014
#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x00200000L
#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x00000015
#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x00400000L
#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x00000016
#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x00800000L
#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x00000017
#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x00000003L
#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x00000000
#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0x0000000cL
#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x00000002
#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x00000030L
#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x00000004
#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0x000000c0L
#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x00000006
#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x00000300L
#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x00000008
#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0x00000c00L
#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0x0000000a
#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x00003000L
#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0x0000000c
#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0x0000c000L
#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0x0000000e
#define MC_ARB_BANKMAP__BANK0_MASK 0x0000000fL
#define MC_ARB_BANKMAP__BANK0__SHIFT 0x00000000
#define MC_ARB_BANKMAP__BANK1_MASK 0x000000f0L
#define MC_ARB_BANKMAP__BANK1__SHIFT 0x00000004
#define MC_ARB_BANKMAP__BANK2_MASK 0x00000f00L
#define MC_ARB_BANKMAP__BANK2__SHIFT 0x00000008
#define MC_ARB_BANKMAP__BANK3_MASK 0x0000f000L
#define MC_ARB_BANKMAP__BANK3__SHIFT 0x0000000c
#define MC_ARB_BANKMAP__RANK_MASK 0x000f0000L
#define MC_ARB_BANKMAP__RANK__SHIFT 0x00000010
#define MC_ARB_BURST_TIME__STATE0_MASK 0x0000001fL
#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x00000000
#define MC_ARB_BURST_TIME__STATE1_MASK 0x000003e0L
#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x00000005
#define MC_ARB_BURST_TIME__STATE2_MASK 0x00007c00L
#define MC_ARB_BURST_TIME__STATE2__SHIFT 0x0000000a
#define MC_ARB_BURST_TIME__STATE3_MASK 0x000f8000L
#define MC_ARB_BURST_TIME__STATE3__SHIFT 0x0000000f
#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x00002000L
#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0x0000000d
#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x00000001L
#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x00000000
#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x0000007eL
#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x00000001
#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x00001f80L
#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x00000007
#define MC_ARB_CG__CG_ARB_REQ_MASK 0x000000ffL
#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x00000000
#define MC_ARB_CG__CG_ARB_RESP_MASK 0x0000ff00L
#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x00000008
#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0x000000ffL
#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x00000000
#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0x0000ff00L
#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x00000008
#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0x00ff0000L
#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x00000010
#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000L
#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x00000018
#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000L
#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x00000018
#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0x000000ffL
#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x00000000
#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0x0000ff00L
#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x00000008
#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0x00ff0000L
#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x00000010
#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000L
#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x00000018
#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0x000000ffL
#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x00000000
#define MC_ARB_DRAM_TIMING2__RP_MASK 0x0000ff00L
#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x00000008
#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0x00ff0000L
#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x00000010
#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0x000000ffL
#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x00000000
#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0x0000ff00L
#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x00000008
#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0x00ff0000L
#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x00000010
#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000L
#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x00000018
#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x00000010L
#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x00000004
#define MC_ARB_FED_CNTL__MODE_MASK 0x00000003L
#define MC_ARB_FED_CNTL__MODE__SHIFT 0x00000000
#define MC_ARB_FED_CNTL__WR_ERR_MASK 0x0000000cL
#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x00000002
#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0x0000000fL
#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x00000000
#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0x000000f0L
#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x00000004
#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L
#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a
#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x00000100L
#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x00000008
#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x00000200L
#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x00000009
#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0x0000000fL
#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x00000000
#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0x000000f0L
#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x00000004
#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L
#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a
#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x00000100L
#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x00000008
#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x00000200L
#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x00000009
#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0x000000ffL
#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x00000000
#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0x0000ff00L
#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x00000008
#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0x00ff0000L
#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x00000010
#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000L
#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x00000018
#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x00004000L
#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0x0000000e
#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x001f8000L
#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0x0000000f
#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0x0000ff00L
#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x00000008
#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0x00ff0000L
#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x00000010
#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000L
#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x00000018
#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0x000000ffL
#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x00000000
#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x00000018L
#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x00000003
#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x00000004L
#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x00000002
#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x00000003L
#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x00000000
#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x00000020L
#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x00000005
#define MC_ARB_GECC2__ECC_MODE_MASK 0x00000006L
#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x00000001
#define MC_ARB_GECC2__ENABLE_MASK 0x00000001L
#define MC_ARB_GECC2__ENABLE__SHIFT 0x00000000
#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x00000060L
#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x00000005
#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0x0000000fL
#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x00000000
#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x00000780L
#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x00000007
#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x00000018L
#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x00000003
#define MC_ARB_GECC2__READ_ERR_MASK 0x00003800L
#define MC_ARB_GECC2__READ_ERR__SHIFT 0x0000000b
#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x00000100L
#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x00000008
#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x00001000L
#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0x0000000c
#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x00000001L
#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x00000000
#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x00000010L
#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x00000004
#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x00000400L
#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0x0000000a
#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x00004000L
#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0x0000000e
#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x00000004L
#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x00000002
#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x00000040L
#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x00000006
#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x00000008L
#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x00000003
#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x00000080L
#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x00000007
#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x00000800L
#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0x0000000b
#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x00000200L
#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x00000009
#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x00002000L
#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0x0000000d
#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x00000002L
#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x00000001
#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x00000020L
#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x00000005
#define MC_ARB_LAZY0_RD__GROUP0_MASK 0x000000ffL
#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x00000000
#define MC_ARB_LAZY0_RD__GROUP1_MASK 0x0000ff00L
#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x00000008
#define MC_ARB_LAZY0_RD__GROUP2_MASK 0x00ff0000L
#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x00000010
#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000L
#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x00000018
#define MC_ARB_LAZY0_WR__GROUP0_MASK 0x000000ffL
#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x00000000
#define MC_ARB_LAZY0_WR__GROUP1_MASK 0x0000ff00L
#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x00000008
#define MC_ARB_LAZY0_WR__GROUP2_MASK 0x00ff0000L
#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x00000010
#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000L
#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x00000018
#define MC_ARB_LAZY1_RD__GROUP4_MASK 0x000000ffL
#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x00000000
#define MC_ARB_LAZY1_RD__GROUP5_MASK 0x0000ff00L
#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x00000008
#define MC_ARB_LAZY1_RD__GROUP6_MASK 0x00ff0000L
#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x00000010
#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000L
#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x00000018
#define MC_ARB_LAZY1_WR__GROUP4_MASK 0x000000ffL
#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x00000000
#define MC_ARB_LAZY1_WR__GROUP5_MASK 0x0000ff00L
#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x00000008
#define MC_ARB_LAZY1_WR__GROUP6_MASK 0x00ff0000L
#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x00000010
#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000L
#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x00000018
#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0x00e00000L
#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x00000015
#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x00040000L
#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x00000012
#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x00080000L
#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x00000013
#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x00100000L
#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x00000014
#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x00010000L
#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x00000010
#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0x000000ffL
#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x00000000
#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0x0000ff00L
#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x00000008
#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x00020000L
#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x00000011
#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0x00e00000L
#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x00000015
#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x00040000L
#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x00000012
#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x00080000L
#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x00000013
#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x00100000L
#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x00000014
#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x00010000L
#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x00000010
#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0x000000ffL
#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x00000000
#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0x0000ff00L
#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x00000008
#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x00020000L
#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x00000011
#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x00010000L
#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x00000010
#define MC_ARB_MINCLKS__READ_CLKS_MASK 0x000000ffL
#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x00000000
#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0x0000ff00L
#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x00000008
#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000L
#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x0000001d
#define MC_ARB_MISC2__GECC_MASK 0x00040000L
#define MC_ARB_MISC2__GECC_RST_MASK 0x00080000L
#define MC_ARB_MISC2__GECC_RST__SHIFT 0x00000013
#define MC_ARB_MISC2__GECC__SHIFT 0x00000012
#define MC_ARB_MISC2__GECC_STATUS_MASK 0x00100000L
#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x00000014
#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x00000800L
#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0x0000000b
#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x00002000L
#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0x0000000d
#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x00001000L
#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0x0000000c
#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x0003c000L
#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0x0000000e
#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000L
#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x0000001c
#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000L
#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x0000001e
#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x01e00000L
#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x00000015
#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x00000040L
#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x00000006
#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x00000080L
#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x00000007
#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x00000100L
#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x00000008
#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x00000200L
#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x00000009
#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x00000400L
#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0x0000000a
#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x00000020L
#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x00000005
#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000L
#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x0000001f
#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0x0e000000L
#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x00000019
#define MC_ARB_MISC__CALI_ENABLE_MASK 0x00100000L
#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x00000014
#define MC_ARB_MISC__CALI_RATES_MASK 0x00600000L
#define MC_ARB_MISC__CALI_RATES__SHIFT 0x00000015
#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x000007f8L
#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x00000003
#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x01000000L
#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x00000018
#define MC_ARB_MISC__DISPURG_STALL_MASK 0x02000000L
#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x00000019
#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000L
#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x0000001a
#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x00800000L
#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x00000017
#define MC_ARB_MISC__HARSHNESS_MASK 0x0007f800L
#define MC_ARB_MISC__HARSHNESS__SHIFT 0x0000000b
#define MC_ARB_MISC__IDLE_RFSH_MASK 0x00000002L
#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x00000001
#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x00080000L
#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x00000013
#define MC_ARB_MISC__STICKY_RFSH_MASK 0x00000001L
#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x00000000
#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x00000004L
#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x00000002
#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x00000020L
#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x00000005
#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0x00f00000L
#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x00000014
#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x00000040L
#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x00000006
#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x00040000L
#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x00000012
#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x00080000L
#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x00000013
#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x00000003L
#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x00000000
#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x00000004L
#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x00000002
#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x00000008L
#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x00000003
#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x00000080L
#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x00000007
#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x00000300L
#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x00000008
#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x00000400L
#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0x0000000a
#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x00000800L
#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0x0000000b
#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x00004000L
#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0x0000000e
#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x00008000L
#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0x0000000f
#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x00001000L
#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0x0000000c
#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x00002000L
#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0x0000000d
#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x00000010L
#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x00000004
#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x00080000L
#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x00000013
#define MC_ARB_POP__ENABLE_ARB_MASK 0x00000001L
#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x00000000
#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x00040000L
#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x00000012
#define MC_ARB_POP__POP_DEPTH_MASK 0x0000003cL
#define MC_ARB_POP__POP_DEPTH__SHIFT 0x00000002
#define MC_ARB_POP__QUICK_STOP_MASK 0x00020000L
#define MC_ARB_POP__QUICK_STOP__SHIFT 0x00000011
#define MC_ARB_POP__SKID_DEPTH_MASK 0x00007000L
#define MC_ARB_POP__SKID_DEPTH__SHIFT 0x0000000c
#define MC_ARB_POP__SPEC_OPEN_MASK 0x00000002L
#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x00000001
#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x00018000L
#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0x0000000f
#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0x00000fc0L
#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x00000006
#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x00000100L
#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x00000008
#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x00000003L
#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x00000000
#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0x000000c0L
#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x00000006
#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x00001000L
#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0x0000000c
#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x00000004L
#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x00000002
#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x00000038L
#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x00000003
#define MC_ARB_REMREQ__RD_WATER_MASK 0x000000ffL
#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x00000000
#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0x00f00000L
#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x00000014
#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0x000f0000L
#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x00000010
#define MC_ARB_REMREQ__WR_WATER_MASK 0x0000ff00L
#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x00000008
#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x00000080L
#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x00000007
#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x00007f00L
#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x00000008
#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x00000040L
#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x00000006
#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x00000001L
#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x00000000
#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x00000002L
#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x00000001
#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x00000020L
#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x00000005
#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x00000010L
#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x00000004
#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x00000008L
#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x00000003
#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x00000004L
#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x00000002
#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0x00ff0000L
#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x00000010
#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0x0000ff00L
#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x00000008
#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0x000000ffL
#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x00000000
#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000L
#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x00000018
#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0x0000ff00L
#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x00000008
#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0x000000ffL
#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x00000000
#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0x00ff0000L
#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x00000010
#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0x0f000000L
#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x00000018
#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x00000800L
#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0x0000000b
#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x00000001L
#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x00000000
#define MC_ARB_RFSH_CNTL__URG0_MASK 0x0000003eL
#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x00000001
#define MC_ARB_RFSH_CNTL__URG1_MASK 0x000007c0L
#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x00000006
#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0x000000ffL
#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x00000000
#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x00000100L
#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x00000008
#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x00000200L
#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x00000009
#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x00000400L
#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0x0000000a
#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x01000000L
#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x00000018
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x00008000L
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0x0000000f
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x00010000L
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x00000010
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x00020000L
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x00000011
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x00040000L
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x00000012
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x00080000L
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x00000013
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x00100000L
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x00000014
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x00200000L
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x00000015
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x00400000L
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x00000016
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x00800000L
#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x00000017
#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x00000001L
#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x00000000
#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x00000010L
#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x00000004
#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x00000020L
#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x00000005
#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x02000000L
#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x00000019
#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x00000002L
#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x00000001
#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0x0000000cL
#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x00004000L
#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0x0000000e
#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x00000002
#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x00000040L
#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x00000006
#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x00003800L
#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0x0000000b
#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x00000080L
#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x00000007
#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0x000fe000L
#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0x0000000d
#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x00001fc0L
#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x00000006
#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x0000001fL
#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x01f00000L
#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x00000014
#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000L
#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x00000019
#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x00000000
#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000L
#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x0000001e
#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x00000020L
#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x00000005
#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x00002000L
#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0x0000000d
#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x00001000L
#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0x0000000c
#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0x00000fc0L
#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x00000006
#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x0000003fL
#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x00000000
#define MC_ARB_RTT_DATA__PATTERN_MASK 0x000000ffL
#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x00000000
#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x00000003L
#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x00000000
#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0x0000000cL
#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x00000002
#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0x00000ff0L
#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x00000004
#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x01fe0000L
#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x00000011
#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x0001f000L
#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0x0000000c
#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000L
#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x00000019
#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x00000100L
#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x00000008
#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0x000000ffL
#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x00000000
#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000L
#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x00000018
#define MC_ARB_SQM_CNTL__RATIO_MASK 0x00ff0000L
#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x00000010
#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0x0000fe00L
#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0x00000009
#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x00000006L
#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x00000001
#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x00000001L
#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x00000000
#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x00000010L
#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x00000004
#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x00000008L
#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x00000003
#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x00000006L
#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x00000001
#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x00000001L
#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x00000000
#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x00000010L
#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x00000004
#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x00000008L
#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x00000003
#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x00000200L
#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x00000009
#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x00000400L
#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0x0000000a
#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x00000800L
#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0x0000000b
#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x00001000L
#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0x0000000c
#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x00002000L
#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0x0000000d
#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x00004000L
#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0x0000000e
#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0x0000000fL
#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x00000000
#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x000001f0L
#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x00000004
#define MC_ARB_WCDR__IDLE_BURST_MASK 0x00001f80L
#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x00002000L
#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0x0000000d
#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x00000007
#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x00010000L
#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x00000010
#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x00000001L
#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x00000000
#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x0000007cL
#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x00000002
#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0x0000c000L
#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0x0000000e
#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x00000002L
#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x00000001
#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x00020000L
#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x00000011
#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x02000000L
#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x00000019
#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x08000000L
#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x0000001b
#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x04000000L
#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x0000001a
#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x01c00000L
#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x00000016
#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x003c0000L
#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x00000012
#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000L
#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x0000001c
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x00000008L
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x00000003
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x00000010L
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x00000004
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x00000020L
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x00000005
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x00000040L
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x00000006
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x00000080L
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x00000007
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x00000100L
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x00000008
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x00000200L
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x00000009
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x00000400L
#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a
#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x00000004L
#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x00000002
#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x00000003L
#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x00000000
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x00000008L
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x00000003
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x00000010L
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x00000004
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x00000020L
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x00000005
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x00000040L
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x00000006
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x00000080L
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x00000007
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x00000100L
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x00000008
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x00000200L
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x00000009
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x00000400L
#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a
#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x00000004L
#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x00000002
#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x00000003L
#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x00000000
#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x00000003L
#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x00000000
#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0x0000000cL
#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x00000002
#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x00000030L
#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x00000004
#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0x000000c0L
#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x00000006
#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x00000300L
#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x00000008
#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0x00000c00L
#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0x0000000a
#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x00003000L
#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0x0000000c
#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0x0000c000L
#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0x0000000e
#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0x00ff0000L
#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x00000010
#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x00000003L
#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x00000000
#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0x0000000cL
#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x00000002
#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x00000030L
#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x00000004
#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0x000000c0L
#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x00000006
#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x00000300L
#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x00000008
#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0x00000c00L
#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0x0000000a
#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x00003000L
#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0x0000000c
#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0x0000c000L
#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0x0000000e
#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0x00ff0000L
#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x00000010
#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0x000000f0L
#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x00000004
#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x02000000L
#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x00000019
#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0x00ffff00L
#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x00000008
#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x01000000L
#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x00000018
#define MC_BIST_AUTO_CNTL__MOP_MASK 0x00000003L
#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x00000000
#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x00000004L
#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x00000002
#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x00000002L
#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x00000001
#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x00010000L
#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x00000010
#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x00020000L
#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x00000011
#define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000L
#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x0000001f
#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000L
#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x0000001c
#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000L
#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x0000001d
#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0x0000fff0L
#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x00000004
#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0x0ffc0000L
#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x00000012
#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x00000008L
#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x00000003
#define MC_BIST_CMD_CNTL__RESET_MASK 0x00000001L
#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x00000000
#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000L
#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x0000001e
#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x0000001fL
#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x00000100L
#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x00000008
#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x00000000
#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x0001f000L
#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x00100000L
#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x00000014
#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0x0000000c
#define MC_BIST_CMP_CNTL__CMP_MASK 0x00030000L
#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0x00000ff0L
#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x00000004
#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0x0000000fL
#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x00000000
#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x00000010
#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x00300000L
#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x00000014
#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x00002000L
#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0x0000000d
#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x00040000L
#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x00000012
#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x00080000L
#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x00000013
#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x00004000L
#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0x0000000e
#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x00008000L
#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0x0000000f
#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x00001000L
#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0x0000000c
#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000L
#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x00000016
#define MC_BIST_CNTL__ADR_MODE_MASK 0x00000020L
#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x00000005
#define MC_BIST_CNTL__DAT_MODE_MASK 0x00000040L
#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x00000006
#define MC_BIST_CNTL__DONE_MASK 0x40000000L
#define MC_BIST_CNTL__DONE__SHIFT 0x0000001e
#define MC_BIST_CNTL__ENABLE_D0_MASK 0x00001000L
#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0x0000000c
#define MC_BIST_CNTL__ENABLE_D1_MASK 0x00002000L
#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0x0000000d
#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x00004000L
#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0x0000000e
#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000L
#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x0000001f
#define MC_BIST_CNTL__LOOP_CNT_MASK 0x0fff0000L
#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x00000010
#define MC_BIST_CNTL__LOOP_MASK 0x00000c00L
#define MC_BIST_CNTL__LOOP__SHIFT 0x0000000a
#define MC_BIST_CNTL__MOP_MODE_MASK 0x00000010L
#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x00000004
#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x00000004L
#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x00000002
#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x00000008L
#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x00000003
#define MC_BIST_CNTL__RESET_MASK 0x00000001L
#define MC_BIST_CNTL__RESET__SHIFT 0x00000000
#define MC_BIST_CNTL__RUN_MASK 0x00000002L
#define MC_BIST_CNTL__RUN__SHIFT 0x00000001
#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffffL
#define MC_BIST_DATA_MASK__MASK__SHIFT 0x00000000
#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffffL
#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x00000000
#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffffL
#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x00000000
#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffffL
#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x00000000
#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffffL
#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x00000000
#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffffL
#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x00000000
#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffffL
#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x00000000
#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffffL
#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x00000000
#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffffL
#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x00000000
#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x00000040L
#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x00000006
#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x00000100L
#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x00000008
#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x00000020L
#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x00000005
#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x00000080L
#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x00000007
#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x00000200L
#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x00000009
#define MC_BIST_DIR_CNTL__EOB_MASK 0x00000008L
#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x00000003
#define MC_BIST_DIR_CNTL__MOP3_MASK 0x00000400L
#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0x0000000a
#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x00000010L
#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x00000004
#define MC_BIST_DIR_CNTL__MOP_MASK 0x00000007L
#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x00000000
#define MC_BIST_EADDR__BANK_MASK 0x0f000000L
#define MC_BIST_EADDR__BANK__SHIFT 0x00000018
#define MC_BIST_EADDR__COLH_MASK 0x20000000L
#define MC_BIST_EADDR__COLH__SHIFT 0x0000001d
#define MC_BIST_EADDR__COL_MASK 0x000003ffL
#define MC_BIST_EADDR__COL__SHIFT 0x00000000
#define MC_BIST_EADDR__RANK_MASK 0x10000000L
#define MC_BIST_EADDR__RANK__SHIFT 0x0000001c
#define MC_BIST_EADDR__ROWH_MASK 0xc0000000L
#define MC_BIST_EADDR__ROWH__SHIFT 0x0000001e
#define MC_BIST_EADDR__ROW_MASK 0x00fffc00L
#define MC_BIST_EADDR__ROW__SHIFT 0x0000000a
#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0x0f000000L
#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x00000018
#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000L
#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x0000001d
#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x000003ffL
#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x00000000
#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000L
#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x0000001c
#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000L
#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x0000001e
#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0x00fffc00L
#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0x0000000a
#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffffL
#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x00000000
#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffffL
#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x00000000
#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffffL
#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x00000000
#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffffL
#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x00000000
#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffffL
#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x00000000
#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffffL
#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x00000000
#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffffL
#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x00000000
#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffffL
#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x00000000
#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffffL
#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x00000000
#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffffL
#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x00000000
#define MC_BIST_SADDR__BANK_MASK 0x0f000000L
#define MC_BIST_SADDR__BANK__SHIFT 0x00000018
#define MC_BIST_SADDR__COLH_MASK 0x20000000L
#define MC_BIST_SADDR__COLH__SHIFT 0x0000001d
#define MC_BIST_SADDR__COL_MASK 0x000003ffL
#define MC_BIST_SADDR__COL__SHIFT 0x00000000
#define MC_BIST_SADDR__RANK_MASK 0x10000000L
#define MC_BIST_SADDR__RANK__SHIFT 0x0000001c
#define MC_BIST_SADDR__ROWH_MASK 0xc0000000L
#define MC_BIST_SADDR__ROWH__SHIFT 0x0000001e
#define MC_BIST_SADDR__ROW_MASK 0x00fffc00L
#define MC_BIST_SADDR__ROW__SHIFT 0x0000000a
#define MC_CG_CONFIG__INDEX_MASK 0x003fffc0L
#define MC_CG_CONFIG__INDEX__SHIFT 0x00000006
#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000L
#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0x0000000d
#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L
#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000
#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L
#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001
#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L
#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002
#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L
#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003
#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L
#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004
#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L
#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005
#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L
#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008
#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L
#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000
#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L
#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001
#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L
#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002
#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L
#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003
#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x00000030L
#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004
#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffffL
#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x00000000
#define MC_CITF_CNTL__EXEMPTPM_MASK 0x00000008L
#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x00000003
#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x00000030L
#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x00000004
#define MC_CITF_CNTL__IGNOREPM_MASK 0x00000004L
#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x00000002
#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x00000040L
#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x00000006
#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x02000000L
#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x00000019
#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x01000000L
#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x00000018
#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0x0000ff00L
#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x00000008
#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0x000000ffL
#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x00000000
#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0x00ff0000L
#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x00000010
#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x00010000L
#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x00000010
#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x00020000L
#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x00000011
#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0x0000ff00L
#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x00000008
#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0x000000ffL
#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x00000000
#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x0000003fL
#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x00000000
#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0x00000fc0L
#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x00000006
#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0x000000ffL
#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x00000000
#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0x0000ff00L
#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x00000008
#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x0000001eL
#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x00000001
#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x000003c0L
#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x00000006
#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x00000020L
#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x00000005
#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x00000001L
#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x00000000
#define MC_CITF_DAGB_DLY__CLI_MASK 0x001f0000L
#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x00000010
#define MC_CITF_DAGB_DLY__DLY_MASK 0x0000001fL
#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x00000000
#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000L
#define MC_CITF_DAGB_DLY__POS__SHIFT 0x00000018
#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0x00fc0000L
#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x00000012
#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x0003f000L
#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0x0000000c
#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000L
#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x00000018
#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x0000003fL
#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x00000000
#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x0000003fL
#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x00000000
#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0x00000fc0L
#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x00000006
#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x00040000L
#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x00000012
#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x00080000L
#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x00000013
#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0x00000fc0L
#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x00000006
#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x0000003fL
#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x00000000
#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x0003f000L
#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0x0000000c
#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x00040000L
#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x00000012
#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L
#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013
#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L
#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x00000006
#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x0000003fL
#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x00000000
#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x0003f000L
#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c
#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x00040000L
#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x00000012
#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x00080000L
#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x00000013
#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0x00000fc0L
#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x00000006
#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x0000003fL
#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x00000000
#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x0003f000L
#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0x0000000c
#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0x000001ffL
#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x00000000
#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x00000040L
#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x00000006
#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x00001000L
#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x0000000c
#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x00000080L
#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x00000007
#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x00002000L
#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x0000000d
#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x00004000L
#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x0000000e
#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x00000100L
#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x00000008
#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x00010000L
#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x00000010
#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x00000400L
#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x0000000a
#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x00020000L
#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x00000011
#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x00008000L
#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0x0000000f
#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x00040000L
#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x00000012
#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x00000200L
#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x00000009
#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x00000800L
#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x0000000b
#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x00004000L
#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0x0000000e
#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x0000007fL
#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x00000000
#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x00003f80L
#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x00000007
#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x00000001L
#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x00000000
#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x00000002L
#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x00000001
#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x00000010L
#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x00000004
#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x00000020L
#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x00000005
#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x00000004L
#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x00000002
#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x00000008L
#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x00000003
#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x01000000L
#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x00000018
#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x00000007L
#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000
#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x00000038L
#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003
#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L
#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006
#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L
#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009
#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x00007000L
#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c
#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x00038000L
#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f
#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L
#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012
#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L
#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015
#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x01000000L
#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x00000018
#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x00000007L
#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000
#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x00000038L
#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003
#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L
#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006
#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L
#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009
#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x00007000L
#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c
#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x00038000L
#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f
#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L
#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012
#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L
#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015
#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0x00000f00L
#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x00000008
#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x00000001L
#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x00000000
#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x00000002L
#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x00000001
#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x00000004L
#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x00000002
#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x00000008L
#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x00000003
#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x00000010L
#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x00000004
#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x00001000L
#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0x0000000c
#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000L
#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x0000001f
#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L
#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000
#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L
#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001
#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L
#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002
#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L
#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003
#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L
#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004
#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L
#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005
#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000L
#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x0000001f
#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L
#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008
#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L
#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000
#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L
#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001
#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L
#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002
#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L
#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003
#define MC_CONFIG__MC_RD_ENABLE_MASK 0x00000030L
#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004
#define MC_HUB_MISC_DBG__SELECT0_MASK 0x0000000fL
#define MC_HUB_MISC_DBG__SELECT0__SHIFT 0x00000000
#define MC_HUB_MISC_DBG__SELECT1_MASK 0x000000f0L
#define MC_HUB_MISC_DBG__SELECT1__SHIFT 0x00000004
#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffffL
#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x00000000
#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x00040000L
#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x00000012
#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x00080000L
#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x00000013
#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0x00000fc0L
#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x00000006
#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x0000003fL
#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x00000000
#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x0003f000L
#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0x0000000c
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x00000001L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x00000000
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x00000002L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x00000001
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x00000400L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x0000000a
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x00000800L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x0000000b
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x00000004L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x00000002
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x00000008L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x00000003
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x00010000L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0x00000010
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x00020000L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0x00000011
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x00040000L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x00000012
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x00080000L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x00000013
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x00000040L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x00000006
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x00000080L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x00000007
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x00004000L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0x0000000e
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x00008000L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0x0000000f
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x00001000L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0x0000000c
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x00002000L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0x0000000d
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x01000000L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x00000018
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x02000000L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x00000019
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x00100000L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x00000014
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x00200000L
#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x00000015
#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x00000003L
#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x00000000
#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x00000018L
#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x00000003
#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x00000004L
#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x00000002
#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x00040000L
#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x00000012
#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x00080000L
#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x00000013
#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0x00000fc0L
#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x00000006
#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x0000003fL
#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x00000000
#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x0003f000L
#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0x0000000c
#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x00002000L
#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x0000000d
#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x00000004L
#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x00000002
#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x00000008L
#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x00000003
#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x00000010L
#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x00000004
#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x00000020L
#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x00000005
#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x00000100L
#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x00000008
#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x00000200L
#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x00000009
#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x00000001L
#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x00000000
#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x00000040L
#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x00000006
#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x00000080L
#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x00000007
#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x00000002L
#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x00000001
#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x00001000L
#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x0000000c
#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x00000400L
#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0x0000000a
#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x00000800L
#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x0000000b
#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x00040000L
#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x00000012
#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L
#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013
#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L
#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x00000006
#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x0000003fL
#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x00000000
#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x0003f000L
#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c
#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x00000200L
#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0x00000009
#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x0001fc00L
#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0x0000000a
#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00020000L
#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x00000011
#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00040000L
#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x00000012
#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x00000004L
#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000002
#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x00000008L
#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000003
#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x00000020L
#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x00000005
#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x00000040L
#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x00000006
#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x00000080L
#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x00000007
#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x00000100L
#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x00000008
#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L
#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004
#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x00080000L
#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x00000013
#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x00000001L
#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x00000000
#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0x000000ffL
#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x00000000
#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0x00ff0000L
#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x00000010
#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000L
#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x00000018
#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0x000000ffL
#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x00000000
#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0x0000ff00L
#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x00000008
#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x00000003L
#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x0000007cL
#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x00000002
#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x00000780L
#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x00000007
#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x00000006L
#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x00000001
#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x00000030L
#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0x000000ffL
#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x00000000
#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0x000000ffL
#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x00000000
#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x00000780L
#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x00000007
#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x00000006L
#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x00000001
#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x00000030L
#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x0003f800L
#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0x0000000b
#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L
#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001
#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x00000004L
#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x00000002
#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x01fc0000L
#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x00000012
#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x00000780L
#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x00000007
#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x00000078L
#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x00000003
#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000L
#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x00000019
#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x0003f800L
#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0x0000000b
#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L
#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001
#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x00000004L
#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x00000002
#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x01fc0000L
#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x00000012
#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x00000780L
#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x00000007
#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x00000078L
#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x00000003
#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000L
#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x00000019
#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x0003f800L
#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0x0000000b
#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L
#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001
#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x00000004L
#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x00000002
#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x01fc0000L
#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x00000012
#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x00000780L
#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x00000007
#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x00000078L
#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x00000003
#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000L
#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x00000019
#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x0003f800L
#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0x0000000b
#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L
#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001
#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x00000004L
#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x00000002
#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x01fc0000L
#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x00000012
#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x00000780L
#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x00000007
#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x00000078L
#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x00000003
#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000L
#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x00000019
#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x00000780L
#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x00000007
#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x00000006L
#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x00000001
#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x00000030L
#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x00000780L
#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x00000007
#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x00000006L
#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x00000001
#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x00000030L
#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x00000780L
#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x00000007
#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x00000006L
#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x00000001
#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x00000030L
#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x0000007fL
#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x00000000
#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x00007f00L
#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x00000008
#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x00000080L
#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x00000007
#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x00000780L
#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x00000007
#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x00000006L
#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x00000001
#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x00000030L
#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x00000080L
#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x00000007
#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x00000040L
#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0x00000006
#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x00000020L
#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x00000005
#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x00000400L
#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x0000000a
#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x00000200L
#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0x00000009
#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x00000100L
#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0x00000008
#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L
#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001
#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L
#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002
#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L
#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003
#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L
#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004
#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x00000800L
#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0x0000000b
#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x00000001L
#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x00000000
#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x00000780L
#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x00000007
#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x00000006L
#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x00000001
#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x00000030L
#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x00000780L
#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x00000007
#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x00000006L
#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x00000001
#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x00000030L
#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x00010000L
#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x00000010
#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x00000780L
#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x00000007
#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x00000006L
#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x00000001
#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x00000030L
#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x00000780L
#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x00000007
#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x00000006L
#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x00000001
#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x00000030L
#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x00000780L
#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x00000007
#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x00000006L
#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x00000001
#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x00000030L
#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L
#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000
#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L
#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003
#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L
#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006
#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L
#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009
#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L
#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c
#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L
#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f
#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L
#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012
#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L
#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015
#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x00000001L
#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x00000000
#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x00000780L
#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x00000007
#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x00000006L
#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x00000001
#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x00000030L
#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x001f0000L
#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x00000010
#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x0000003fL
#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x00000000
#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000L
#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x00000018
#define MC_HUB_WDP_BP__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_BP__RDRET_MASK 0x0003fffeL
#define MC_HUB_WDP_BP__RDRET__SHIFT 0x00000001
#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000L
#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x00000012
#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x00001fe0L
#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x00000005
#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00002000L
#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x0000000d
#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00004000L
#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x0000000e
#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x00008000L
#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0x0000000f
#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x00040000L
#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x00000012
#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x00010000L
#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x00000010
#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x00000002L
#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000001
#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x00000004L
#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000002
#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x00000008L
#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x00000003
#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x00020000L
#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x00000011
#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x00080000L
#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x00000013
#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L
#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004
#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x00100000L
#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x00000014
#define MC_HUB_WDP_CREDITS__STOR0_MASK 0x00ff0000L
#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x00000010
#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000L
#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x00000018
#define MC_HUB_WDP_CREDITS__VM0_MASK 0x000000ffL
#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x00000000
#define MC_HUB_WDP_CREDITS__VM1_MASK 0x0000ff00L
#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x00000008
#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x00000001L
#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x00000000
#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x00000002L
#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x00000001
#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0x000000f0L
#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x00000004
#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0x0000000fL
#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x00000000
#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x00010000L
#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x00000010
#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0x0000ff00L
#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x00000008
#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0x000000f0L
#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x00000004
#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0x0000000fL
#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x00000000
#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x00010000L
#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x00000010
#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0x0000ff00L
#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x00000008
#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_HDP__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_IH__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_IH__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_IH__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x00001f80L
#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x00000007
#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000L
#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x00000018
#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L
#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001
#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x0001e000L
#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0x0000000d
#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x00000078L
#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x00000003
#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x00000004L
#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x00000002
#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0x00fe0000L
#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x00000011
#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x00001f80L
#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x00000007
#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000L
#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x00000018
#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L
#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001
#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x0001e000L
#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0x0000000d
#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x00000078L
#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x00000003
#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x00000004L
#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x00000002
#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0x00fe0000L
#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x00000011
#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x00001f80L
#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x00000007
#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000L
#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x00000018
#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L
#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001
#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x0001e000L
#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0x0000000d
#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x00000078L
#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x00000003
#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x00000004L
#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x00000002
#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0x00fe0000L
#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x00000011
#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x00001f80L
#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x00000007
#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000L
#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x00000018
#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L
#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001
#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x0001e000L
#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0x0000000d
#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x00000078L
#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x00000003
#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x00000004L
#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x00000002
#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0x00fe0000L
#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x00000011
#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_MGPU2__CID2_MASK 0x000000ffL
#define MC_HUB_WDP_MGPU2__CID2__SHIFT 0x00000000
#define MC_HUB_WDP_MGPU__CID_MASK 0x0000ff00L
#define MC_HUB_WDP_MGPU__CID__SHIFT 0x00000008
#define MC_HUB_WDP_MGPU__ENABLE_MASK 0x00800000L
#define MC_HUB_WDP_MGPU__ENABLE__SHIFT 0x00000017
#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME_MASK 0x007f0000L
#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME__SHIFT 0x00000010
#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME_MASK 0x7f000000L
#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME__SHIFT 0x00000018
#define MC_HUB_WDP_MGPU__STOR_MASK 0x000000ffL
#define MC_HUB_WDP_MGPU__STOR__SHIFT 0x00000000
#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_RLC__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_SEM__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_SH0__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_SH1__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x000001fcL
#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x00000002
#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x00000003L
#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x00000000
#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_SMU__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x00000080L
#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x00000007
#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x00000040L
#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x00000006
#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x00000020L
#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x00000005
#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x00000400L
#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x0000000a
#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x00000200L
#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x00000009
#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x00000100L
#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x00000008
#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L
#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001
#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x00000800L
#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x0000000b
#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L
#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002
#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x00001000L
#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0x0000000c
#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L
#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003
#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x00002000L
#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0x0000000d
#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L
#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004
#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x00004000L
#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0x0000000e
#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x00000001L
#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x00000000
#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_UMC__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_UVD__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x00010000L
#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x00000010
#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_VCE__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L
#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000
#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L
#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003
#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L
#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006
#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L
#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009
#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L
#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c
#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L
#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f
#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L
#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012
#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L
#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015
#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L
#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010
#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L
#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010
#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x00000008L
#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x00000003
#define MC_HUB_WDP_XDP__ENABLE_MASK 0x00000001L
#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x00000000
#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x00007800L
#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0x0000000b
#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x00000780L
#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x00000007
#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x00000006L
#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x00000001
#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x00000030L
#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x00000004
#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x00000040L
#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x00000006
#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x00008000L
#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x00200000L
#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x00000015
#define MC_HUB_WRRET_CNTL__BP_MASK 0x001ffffeL
#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x00000001
#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000L
#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x00000016
#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000L
#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x0000001e
#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000L
#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x0000001f
#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x00000001L
#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x00000000
#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0x000000feL
#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x00000001
#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x00000001L
#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x00000000
#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0x000000feL
#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x00000001
#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x00000001L
#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x00000000
#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0x000000feL
#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x00000001
#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x00000001L
#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x00000000
#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0x000000feL
#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x00000001
#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x00000001L
#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x00000000
#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x00000001L
#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x00000000
#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x00000002L
#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x00000001
#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x00000004L
#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x00000002
#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x00000008L
#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x00000003
#define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000L
#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x0000001f
#define MC_IMP_CNTL__CAL_VREF_MASK 0x007f0000L
#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x00000040L
#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x00000006
#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x00000020L
#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x00000005
#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x00000010
#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000L
#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x0000001d
#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000L
#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x0000001e
#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x00000200L
#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x00000009
#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0x0000e000L
#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0x0000000d
#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x0000001fL
#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x00000000
#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x00000100L
#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x00000008
#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000L
#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x0000001f
#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000L
#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x0000001c
#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000L
#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x0000001e
#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000L
#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x0000001d
#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0x0fff0000L
#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x00000010
#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0x0000ff00L
#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x00000008
#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0x000000ffL
#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x00000000
#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0x0000ff00L
#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x00000008
#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0x000000ffL
#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x00000000
#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000L
#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x00000018
#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0x00ff0000L
#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x00000010
#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000L
#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x00000018
#define MC_IMP_STATUS__NSTR_CAL_MASK 0x00ff0000L
#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x00000010
#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0x0000ff00L
#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x00000008
#define MC_IMP_STATUS__PSTR_CAL_MASK 0x000000ffL
#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x00000000
#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0x0c000000L
#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x0000001a
#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000L
#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x0000001c
#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000L
#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x0000001d
#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0x00000fc0L
#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x00000006
#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x0000003fL
#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x00000000
#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x0003f000L
#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0x0000000c
#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x01000000L
#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x00000018
#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x02000000L
#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x00000019
#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0x0c000000L
#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x0000001a
#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000L
#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x0000001c
#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000L
#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x0000001d
#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0x00000fc0L
#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x00000006
#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x0000003fL
#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x00000000
#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x0003f000L
#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0x0000000c
#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x01000000L
#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x00000018
#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x02000000L
#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x00000019
#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0x000000ffL
#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x00000000
#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0x0000ff00L
#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x00000008
#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0x00ff0000L
#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x00000010
#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000L
#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x00000018
#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0x000000ffL
#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x00000000
#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0x0000ff00L
#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x00000008
#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0x00ff0000L
#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x00000010
#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000L
#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x00000018
#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x00000001L
#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x00000000
#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x00000002L
#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x00000001
#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x00000004L
#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x00000002
#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x00000008L
#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x00000003
#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x00000010L
#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x00000004
#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x00000020L
#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x00000005
#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x00000040L
#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x00000006
#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x00000080L
#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x00000007
#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x00000001L
#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x00000000
#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x00000002L
#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x00000001
#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x00000004L
#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x00000002
#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x00000008L
#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x00000003
#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x00000010L
#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x00000004
#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x00000020L
#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x00000005
#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x00000040L
#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x00000006
#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x00000080L
#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x00000007
#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x00400000L
#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x00000016
#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x00800000L
#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x00000017
#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000L
#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x0000001c
#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000L
#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x0000001d
#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x00100000L
#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x00000014
#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x00200000L
#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x00000015
#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000L
#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x0000001e
#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000L
#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x0000001f
#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x00000400L
#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0x0000000a
#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x00000800L
#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0x0000000b
#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x00000100L
#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x00000008
#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x00000200L
#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x00000009
#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0x0000f000L
#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0x0000000c
#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0x000f0000L
#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x00000010
#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0x0000000fL
#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x00000000
#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0x000000f0L
#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x00000004
#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x04000000L
#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x0000001a
#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x08000000L
#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x0000001b
#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x01000000L
#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x00000018
#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x02000000L
#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x00000019
#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x00400000L
#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x00000016
#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x00800000L
#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x00000017
#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000L
#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x0000001c
#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000L
#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x0000001d
#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x00100000L
#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x00000014
#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x00200000L
#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x00000015
#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000L
#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x0000001e
#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000L
#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x0000001f
#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x00000400L
#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0x0000000a
#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x00000800L
#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0x0000000b
#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x00000100L
#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x00000008
#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x00000200L
#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x00000009
#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0x0000f000L
#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0x0000000c
#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0x000f0000L
#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x00000010
#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0x0000000fL
#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x00000000
#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0x000000f0L
#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x00000004
#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x04000000L
#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x0000001a
#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x08000000L
#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x0000001b
#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x01000000L
#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x00000018
#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x02000000L
#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x00000019
#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000L
#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L