blob: adb7a21e2a103276a645aa14ee4e6341332e7d71 [file] [log] [blame]
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _mmhub_1_7_OFFSET_HEADER
#define _mmhub_1_7_OFFSET_HEADER
// addressBlock: mmhub_dagb_dagbdec0
// base address: 0x68000
#define regDAGB0_RDCLI0 0x0000
#define regDAGB0_RDCLI0_BASE_IDX 0
#define regDAGB0_RDCLI1 0x0001
#define regDAGB0_RDCLI1_BASE_IDX 0
#define regDAGB0_RDCLI2 0x0002
#define regDAGB0_RDCLI2_BASE_IDX 0
#define regDAGB0_RDCLI3 0x0003
#define regDAGB0_RDCLI3_BASE_IDX 0
#define regDAGB0_RDCLI4 0x0004
#define regDAGB0_RDCLI4_BASE_IDX 0
#define regDAGB0_RDCLI5 0x0005
#define regDAGB0_RDCLI5_BASE_IDX 0
#define regDAGB0_RDCLI6 0x0006
#define regDAGB0_RDCLI6_BASE_IDX 0
#define regDAGB0_RDCLI7 0x0007
#define regDAGB0_RDCLI7_BASE_IDX 0
#define regDAGB0_RDCLI8 0x0008
#define regDAGB0_RDCLI8_BASE_IDX 0
#define regDAGB0_RDCLI9 0x0009
#define regDAGB0_RDCLI9_BASE_IDX 0
#define regDAGB0_RDCLI10 0x000a
#define regDAGB0_RDCLI10_BASE_IDX 0
#define regDAGB0_RDCLI11 0x000b
#define regDAGB0_RDCLI11_BASE_IDX 0
#define regDAGB0_RDCLI12 0x000c
#define regDAGB0_RDCLI12_BASE_IDX 0
#define regDAGB0_RDCLI13 0x000d
#define regDAGB0_RDCLI13_BASE_IDX 0
#define regDAGB0_RDCLI14 0x000e
#define regDAGB0_RDCLI14_BASE_IDX 0
#define regDAGB0_RDCLI15 0x000f
#define regDAGB0_RDCLI15_BASE_IDX 0
#define regDAGB0_RD_CNTL 0x0010
#define regDAGB0_RD_CNTL_BASE_IDX 0
#define regDAGB0_RD_GMI_CNTL 0x0011
#define regDAGB0_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB 0x0012
#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013
#define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014
#define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB0_RD_CGTT_CLK_CTRL 0x0015
#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016
#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017
#define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB0_RD_VC0_CNTL 0x001c
#define regDAGB0_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC1_CNTL 0x001d
#define regDAGB0_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC2_CNTL 0x001e
#define regDAGB0_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC3_CNTL 0x001f
#define regDAGB0_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC4_CNTL 0x0020
#define regDAGB0_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC5_CNTL 0x0021
#define regDAGB0_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC6_CNTL 0x0022
#define regDAGB0_RD_VC6_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC7_CNTL 0x0023
#define regDAGB0_RD_VC7_CNTL_BASE_IDX 0
#define regDAGB0_RD_CNTL_MISC 0x0024
#define regDAGB0_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB0_RD_TLB_CREDIT 0x0025
#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB0_RD_RDRET_CREDIT_CNTL 0x0026
#define regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
#define regDAGB0_RD_RDRET_CREDIT_CNTL2 0x0027
#define regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB0_RDCLI_ASK_PENDING 0x0028
#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_GO_PENDING 0x0029
#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_GBLSEND_PENDING 0x002a
#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_TLB_PENDING 0x002b
#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_OARB_PENDING 0x002c
#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_OSD_PENDING 0x002d
#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI0 0x002e
#define regDAGB0_WRCLI0_BASE_IDX 0
#define regDAGB0_WRCLI1 0x002f
#define regDAGB0_WRCLI1_BASE_IDX 0
#define regDAGB0_WRCLI2 0x0030
#define regDAGB0_WRCLI2_BASE_IDX 0
#define regDAGB0_WRCLI3 0x0031
#define regDAGB0_WRCLI3_BASE_IDX 0
#define regDAGB0_WRCLI4 0x0032
#define regDAGB0_WRCLI4_BASE_IDX 0
#define regDAGB0_WRCLI5 0x0033
#define regDAGB0_WRCLI5_BASE_IDX 0
#define regDAGB0_WRCLI6 0x0034
#define regDAGB0_WRCLI6_BASE_IDX 0
#define regDAGB0_WRCLI7 0x0035
#define regDAGB0_WRCLI7_BASE_IDX 0
#define regDAGB0_WRCLI8 0x0036
#define regDAGB0_WRCLI8_BASE_IDX 0
#define regDAGB0_WRCLI9 0x0037
#define regDAGB0_WRCLI9_BASE_IDX 0
#define regDAGB0_WRCLI10 0x0038
#define regDAGB0_WRCLI10_BASE_IDX 0
#define regDAGB0_WRCLI11 0x0039
#define regDAGB0_WRCLI11_BASE_IDX 0
#define regDAGB0_WRCLI12 0x003a
#define regDAGB0_WRCLI12_BASE_IDX 0
#define regDAGB0_WRCLI13 0x003b
#define regDAGB0_WRCLI13_BASE_IDX 0
#define regDAGB0_WRCLI14 0x003c
#define regDAGB0_WRCLI14_BASE_IDX 0
#define regDAGB0_WRCLI15 0x003d
#define regDAGB0_WRCLI15_BASE_IDX 0
#define regDAGB0_WR_CNTL 0x003e
#define regDAGB0_WR_CNTL_BASE_IDX 0
#define regDAGB0_WR_GMI_CNTL 0x003f
#define regDAGB0_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB 0x0040
#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0041
#define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0042
#define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB0_WR_CGTT_CLK_CTRL 0x0043
#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0044
#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0045
#define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0046
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0047
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0048
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0049
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB 0x004a
#define regDAGB0_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x004b
#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004c
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004d
#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004e
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB0_WR_VC0_CNTL 0x004f
#define regDAGB0_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC1_CNTL 0x0050
#define regDAGB0_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC2_CNTL 0x0051
#define regDAGB0_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC3_CNTL 0x0052
#define regDAGB0_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC4_CNTL 0x0053
#define regDAGB0_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC5_CNTL 0x0054
#define regDAGB0_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC6_CNTL 0x0055
#define regDAGB0_WR_VC6_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC7_CNTL 0x0056
#define regDAGB0_WR_VC7_CNTL_BASE_IDX 0
#define regDAGB0_WR_CNTL_MISC 0x0057
#define regDAGB0_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB0_WR_TLB_CREDIT 0x0058
#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB0_WR_DATA_CREDIT 0x0059
#define regDAGB0_WR_DATA_CREDIT_BASE_IDX 0
#define regDAGB0_WR_MISC_CREDIT 0x005a
#define regDAGB0_WR_MISC_CREDIT_BASE_IDX 0
#define regDAGB0_WR_OSD_CREDIT_CNTL1 0x005b
#define regDAGB0_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB0_WR_OSD_CREDIT_CNTL2 0x005c
#define regDAGB0_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x005d
#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x005e
#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x005f
#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB0_WRCLI_ASK_PENDING 0x0060
#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_GO_PENDING 0x0061
#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0062
#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_TLB_PENDING 0x0063
#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_OARB_PENDING 0x0064
#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_OSD_PENDING 0x0065
#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x0066
#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x0067
#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB0_DAGB_DLY 0x0068
#define regDAGB0_DAGB_DLY_BASE_IDX 0
#define regDAGB0_CNTL_MISC 0x0069
#define regDAGB0_CNTL_MISC_BASE_IDX 0
#define regDAGB0_CNTL_MISC2 0x006a
#define regDAGB0_CNTL_MISC2_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_CNTL 0x006b
#define regDAGB0_FATAL_ERROR_CNTL_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_CLEAR 0x006c
#define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS0 0x006d
#define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS1 0x006e
#define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS2 0x006f
#define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS3 0x0070
#define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB0_FIFO_EMPTY 0x0071
#define regDAGB0_FIFO_EMPTY_BASE_IDX 0
#define regDAGB0_FIFO_FULL 0x0072
#define regDAGB0_FIFO_FULL_BASE_IDX 0
#define regDAGB0_WR_CREDITS_FULL 0x0073
#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB0_RD_CREDITS_FULL 0x0074
#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB0_PERFCOUNTER_LO 0x0075
#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB0_PERFCOUNTER_HI 0x0076
#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB0_PERFCOUNTER0_CFG 0x0077
#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB0_PERFCOUNTER1_CFG 0x0078
#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB0_PERFCOUNTER2_CFG 0x0079
#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x007a
#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB0_L1TLB_REG_RW 0x007b
#define regDAGB0_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB0_RESERVE1 0x007c
#define regDAGB0_RESERVE1_BASE_IDX 0
#define regDAGB0_RESERVE2 0x007d
#define regDAGB0_RESERVE2_BASE_IDX 0
#define regDAGB0_RESERVE3 0x007e
#define regDAGB0_RESERVE3_BASE_IDX 0
#define regDAGB0_RESERVE4 0x007f
#define regDAGB0_RESERVE4_BASE_IDX 0
// addressBlock: mmhub_dagb_dagbdec1
// base address: 0x68200
#define regDAGB1_RDCLI0 0x0080
#define regDAGB1_RDCLI0_BASE_IDX 0
#define regDAGB1_RDCLI1 0x0081
#define regDAGB1_RDCLI1_BASE_IDX 0
#define regDAGB1_RDCLI2 0x0082
#define regDAGB1_RDCLI2_BASE_IDX 0
#define regDAGB1_RDCLI3 0x0083
#define regDAGB1_RDCLI3_BASE_IDX 0
#define regDAGB1_RDCLI4 0x0084
#define regDAGB1_RDCLI4_BASE_IDX 0
#define regDAGB1_RDCLI5 0x0085
#define regDAGB1_RDCLI5_BASE_IDX 0
#define regDAGB1_RDCLI6 0x0086
#define regDAGB1_RDCLI6_BASE_IDX 0
#define regDAGB1_RDCLI7 0x0087
#define regDAGB1_RDCLI7_BASE_IDX 0
#define regDAGB1_RDCLI8 0x0088
#define regDAGB1_RDCLI8_BASE_IDX 0
#define regDAGB1_RDCLI9 0x0089
#define regDAGB1_RDCLI9_BASE_IDX 0
#define regDAGB1_RDCLI10 0x008a
#define regDAGB1_RDCLI10_BASE_IDX 0
#define regDAGB1_RDCLI11 0x008b
#define regDAGB1_RDCLI11_BASE_IDX 0
#define regDAGB1_RDCLI12 0x008c
#define regDAGB1_RDCLI12_BASE_IDX 0
#define regDAGB1_RDCLI13 0x008d
#define regDAGB1_RDCLI13_BASE_IDX 0
#define regDAGB1_RDCLI14 0x008e
#define regDAGB1_RDCLI14_BASE_IDX 0
#define regDAGB1_RDCLI15 0x008f
#define regDAGB1_RDCLI15_BASE_IDX 0
#define regDAGB1_RD_CNTL 0x0090
#define regDAGB1_RD_CNTL_BASE_IDX 0
#define regDAGB1_RD_GMI_CNTL 0x0091
#define regDAGB1_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB 0x0092
#define regDAGB1_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093
#define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094
#define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB1_RD_CGTT_CLK_CTRL 0x0095
#define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096
#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097
#define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB1_RD_VC0_CNTL 0x009c
#define regDAGB1_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC1_CNTL 0x009d
#define regDAGB1_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC2_CNTL 0x009e
#define regDAGB1_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC3_CNTL 0x009f
#define regDAGB1_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC4_CNTL 0x00a0
#define regDAGB1_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC5_CNTL 0x00a1
#define regDAGB1_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC6_CNTL 0x00a2
#define regDAGB1_RD_VC6_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC7_CNTL 0x00a3
#define regDAGB1_RD_VC7_CNTL_BASE_IDX 0
#define regDAGB1_RD_CNTL_MISC 0x00a4
#define regDAGB1_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB1_RD_TLB_CREDIT 0x00a5
#define regDAGB1_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB1_RD_RDRET_CREDIT_CNTL 0x00a6
#define regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
#define regDAGB1_RD_RDRET_CREDIT_CNTL2 0x00a7
#define regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB1_RDCLI_ASK_PENDING 0x00a8
#define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_GO_PENDING 0x00a9
#define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_GBLSEND_PENDING 0x00aa
#define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_TLB_PENDING 0x00ab
#define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_OARB_PENDING 0x00ac
#define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_OSD_PENDING 0x00ad
#define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI0 0x00ae
#define regDAGB1_WRCLI0_BASE_IDX 0
#define regDAGB1_WRCLI1 0x00af
#define regDAGB1_WRCLI1_BASE_IDX 0
#define regDAGB1_WRCLI2 0x00b0
#define regDAGB1_WRCLI2_BASE_IDX 0
#define regDAGB1_WRCLI3 0x00b1
#define regDAGB1_WRCLI3_BASE_IDX 0
#define regDAGB1_WRCLI4 0x00b2
#define regDAGB1_WRCLI4_BASE_IDX 0
#define regDAGB1_WRCLI5 0x00b3
#define regDAGB1_WRCLI5_BASE_IDX 0
#define regDAGB1_WRCLI6 0x00b4
#define regDAGB1_WRCLI6_BASE_IDX 0
#define regDAGB1_WRCLI7 0x00b5
#define regDAGB1_WRCLI7_BASE_IDX 0
#define regDAGB1_WRCLI8 0x00b6
#define regDAGB1_WRCLI8_BASE_IDX 0
#define regDAGB1_WRCLI9 0x00b7
#define regDAGB1_WRCLI9_BASE_IDX 0
#define regDAGB1_WRCLI10 0x00b8
#define regDAGB1_WRCLI10_BASE_IDX 0
#define regDAGB1_WRCLI11 0x00b9
#define regDAGB1_WRCLI11_BASE_IDX 0
#define regDAGB1_WRCLI12 0x00ba
#define regDAGB1_WRCLI12_BASE_IDX 0
#define regDAGB1_WRCLI13 0x00bb
#define regDAGB1_WRCLI13_BASE_IDX 0
#define regDAGB1_WRCLI14 0x00bc
#define regDAGB1_WRCLI14_BASE_IDX 0
#define regDAGB1_WRCLI15 0x00bd
#define regDAGB1_WRCLI15_BASE_IDX 0
#define regDAGB1_WR_CNTL 0x00be
#define regDAGB1_WR_CNTL_BASE_IDX 0
#define regDAGB1_WR_GMI_CNTL 0x00bf
#define regDAGB1_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB1_WR_ADDR_DAGB 0x00c0
#define regDAGB1_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00c1
#define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c2
#define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB1_WR_CGTT_CLK_CTRL 0x00c3
#define regDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c4
#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c5
#define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c6
#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c7
#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c8
#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c9
#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB1_WR_DATA_DAGB 0x00ca
#define regDAGB1_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00cb
#define regDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00cc
#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cd
#define regDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00ce
#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB1_WR_VC0_CNTL 0x00cf
#define regDAGB1_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC1_CNTL 0x00d0
#define regDAGB1_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC2_CNTL 0x00d1
#define regDAGB1_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC3_CNTL 0x00d2
#define regDAGB1_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC4_CNTL 0x00d3
#define regDAGB1_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC5_CNTL 0x00d4
#define regDAGB1_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC6_CNTL 0x00d5
#define regDAGB1_WR_VC6_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC7_CNTL 0x00d6
#define regDAGB1_WR_VC7_CNTL_BASE_IDX 0
#define regDAGB1_WR_CNTL_MISC 0x00d7
#define regDAGB1_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB1_WR_TLB_CREDIT 0x00d8
#define regDAGB1_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB1_WR_DATA_CREDIT 0x00d9
#define regDAGB1_WR_DATA_CREDIT_BASE_IDX 0
#define regDAGB1_WR_MISC_CREDIT 0x00da
#define regDAGB1_WR_MISC_CREDIT_BASE_IDX 0
#define regDAGB1_WR_OSD_CREDIT_CNTL1 0x00db
#define regDAGB1_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB1_WR_OSD_CREDIT_CNTL2 0x00dc
#define regDAGB1_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x00dd
#define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE 0x00de
#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x00df
#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB1_WRCLI_ASK_PENDING 0x00e0
#define regDAGB1_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_GO_PENDING 0x00e1
#define regDAGB1_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_GBLSEND_PENDING 0x00e2
#define regDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_TLB_PENDING 0x00e3
#define regDAGB1_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_OARB_PENDING 0x00e4
#define regDAGB1_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_OSD_PENDING 0x00e5
#define regDAGB1_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_DBUS_ASK_PENDING 0x00e6
#define regDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_DBUS_GO_PENDING 0x00e7
#define regDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB1_DAGB_DLY 0x00e8
#define regDAGB1_DAGB_DLY_BASE_IDX 0
#define regDAGB1_CNTL_MISC 0x00e9
#define regDAGB1_CNTL_MISC_BASE_IDX 0
#define regDAGB1_CNTL_MISC2 0x00ea
#define regDAGB1_CNTL_MISC2_BASE_IDX 0
#define regDAGB1_FATAL_ERROR_CNTL 0x00eb
#define regDAGB1_FATAL_ERROR_CNTL_BASE_IDX 0
#define regDAGB1_FATAL_ERROR_CLEAR 0x00ec
#define regDAGB1_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB1_FATAL_ERROR_STATUS0 0x00ed
#define regDAGB1_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB1_FATAL_ERROR_STATUS1 0x00ee
#define regDAGB1_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB1_FATAL_ERROR_STATUS2 0x00ef
#define regDAGB1_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB1_FATAL_ERROR_STATUS3 0x00f0
#define regDAGB1_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB1_FIFO_EMPTY 0x00f1
#define regDAGB1_FIFO_EMPTY_BASE_IDX 0
#define regDAGB1_FIFO_FULL 0x00f2
#define regDAGB1_FIFO_FULL_BASE_IDX 0
#define regDAGB1_WR_CREDITS_FULL 0x00f3
#define regDAGB1_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB1_RD_CREDITS_FULL 0x00f4
#define regDAGB1_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB1_PERFCOUNTER_LO 0x00f5
#define regDAGB1_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB1_PERFCOUNTER_HI 0x00f6
#define regDAGB1_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB1_PERFCOUNTER0_CFG 0x00f7
#define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB1_PERFCOUNTER1_CFG 0x00f8
#define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB1_PERFCOUNTER2_CFG 0x00f9
#define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB1_PERFCOUNTER_RSLT_CNTL 0x00fa
#define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB1_L1TLB_REG_RW 0x00fb
#define regDAGB1_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB1_RESERVE1 0x00fc
#define regDAGB1_RESERVE1_BASE_IDX 0
#define regDAGB1_RESERVE2 0x00fd
#define regDAGB1_RESERVE2_BASE_IDX 0
#define regDAGB1_RESERVE3 0x00fe
#define regDAGB1_RESERVE3_BASE_IDX 0
#define regDAGB1_RESERVE4 0x00ff
#define regDAGB1_RESERVE4_BASE_IDX 0
// addressBlock: mmhub_dagb_dagbdec2
// base address: 0x68400
#define regDAGB2_RDCLI0 0x0100
#define regDAGB2_RDCLI0_BASE_IDX 0
#define regDAGB2_RDCLI1 0x0101
#define regDAGB2_RDCLI1_BASE_IDX 0
#define regDAGB2_RDCLI2 0x0102
#define regDAGB2_RDCLI2_BASE_IDX 0
#define regDAGB2_RDCLI3 0x0103
#define regDAGB2_RDCLI3_BASE_IDX 0
#define regDAGB2_RDCLI4 0x0104
#define regDAGB2_RDCLI4_BASE_IDX 0
#define regDAGB2_RDCLI5 0x0105
#define regDAGB2_RDCLI5_BASE_IDX 0
#define regDAGB2_RDCLI6 0x0106
#define regDAGB2_RDCLI6_BASE_IDX 0
#define regDAGB2_RDCLI7 0x0107
#define regDAGB2_RDCLI7_BASE_IDX 0
#define regDAGB2_RDCLI8 0x0108
#define regDAGB2_RDCLI8_BASE_IDX 0
#define regDAGB2_RDCLI9 0x0109
#define regDAGB2_RDCLI9_BASE_IDX 0
#define regDAGB2_RDCLI10 0x010a
#define regDAGB2_RDCLI10_BASE_IDX 0
#define regDAGB2_RDCLI11 0x010b
#define regDAGB2_RDCLI11_BASE_IDX 0
#define regDAGB2_RDCLI12 0x010c
#define regDAGB2_RDCLI12_BASE_IDX 0
#define regDAGB2_RDCLI13 0x010d
#define regDAGB2_RDCLI13_BASE_IDX 0
#define regDAGB2_RDCLI14 0x010e
#define regDAGB2_RDCLI14_BASE_IDX 0
#define regDAGB2_RDCLI15 0x010f
#define regDAGB2_RDCLI15_BASE_IDX 0
#define regDAGB2_RD_CNTL 0x0110
#define regDAGB2_RD_CNTL_BASE_IDX 0
#define regDAGB2_RD_GMI_CNTL 0x0111
#define regDAGB2_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB2_RD_ADDR_DAGB 0x0112
#define regDAGB2_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0x0113
#define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0x0114
#define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB2_RD_CGTT_CLK_CTRL 0x0115
#define regDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0x0116
#define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0x0117
#define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB2_RD_ADDR_DAGB_MAX_BURST0 0x0118
#define regDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0x0119
#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB2_RD_ADDR_DAGB_MAX_BURST1 0x011a
#define regDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0x011b
#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB2_RD_VC0_CNTL 0x011c
#define regDAGB2_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC1_CNTL 0x011d
#define regDAGB2_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC2_CNTL 0x011e
#define regDAGB2_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC3_CNTL 0x011f
#define regDAGB2_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC4_CNTL 0x0120
#define regDAGB2_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC5_CNTL 0x0121
#define regDAGB2_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC6_CNTL 0x0122
#define regDAGB2_RD_VC6_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC7_CNTL 0x0123
#define regDAGB2_RD_VC7_CNTL_BASE_IDX 0
#define regDAGB2_RD_CNTL_MISC 0x0124
#define regDAGB2_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB2_RD_TLB_CREDIT 0x0125
#define regDAGB2_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB2_RD_RDRET_CREDIT_CNTL 0x0126
#define regDAGB2_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
#define regDAGB2_RD_RDRET_CREDIT_CNTL2 0x0127
#define regDAGB2_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB2_RDCLI_ASK_PENDING 0x0128
#define regDAGB2_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB2_RDCLI_GO_PENDING 0x0129
#define regDAGB2_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB2_RDCLI_GBLSEND_PENDING 0x012a
#define regDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB2_RDCLI_TLB_PENDING 0x012b
#define regDAGB2_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB2_RDCLI_OARB_PENDING 0x012c
#define regDAGB2_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB2_RDCLI_OSD_PENDING 0x012d
#define regDAGB2_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI0 0x012e
#define regDAGB2_WRCLI0_BASE_IDX 0
#define regDAGB2_WRCLI1 0x012f
#define regDAGB2_WRCLI1_BASE_IDX 0
#define regDAGB2_WRCLI2 0x0130
#define regDAGB2_WRCLI2_BASE_IDX 0
#define regDAGB2_WRCLI3 0x0131
#define regDAGB2_WRCLI3_BASE_IDX 0
#define regDAGB2_WRCLI4 0x0132
#define regDAGB2_WRCLI4_BASE_IDX 0
#define regDAGB2_WRCLI5 0x0133
#define regDAGB2_WRCLI5_BASE_IDX 0
#define regDAGB2_WRCLI6 0x0134
#define regDAGB2_WRCLI6_BASE_IDX 0
#define regDAGB2_WRCLI7 0x0135
#define regDAGB2_WRCLI7_BASE_IDX 0
#define regDAGB2_WRCLI8 0x0136
#define regDAGB2_WRCLI8_BASE_IDX 0
#define regDAGB2_WRCLI9 0x0137
#define regDAGB2_WRCLI9_BASE_IDX 0
#define regDAGB2_WRCLI10 0x0138
#define regDAGB2_WRCLI10_BASE_IDX 0
#define regDAGB2_WRCLI11 0x0139
#define regDAGB2_WRCLI11_BASE_IDX 0
#define regDAGB2_WRCLI12 0x013a
#define regDAGB2_WRCLI12_BASE_IDX 0
#define regDAGB2_WRCLI13 0x013b
#define regDAGB2_WRCLI13_BASE_IDX 0
#define regDAGB2_WRCLI14 0x013c
#define regDAGB2_WRCLI14_BASE_IDX 0
#define regDAGB2_WRCLI15 0x013d
#define regDAGB2_WRCLI15_BASE_IDX 0
#define regDAGB2_WR_CNTL 0x013e
#define regDAGB2_WR_CNTL_BASE_IDX 0
#define regDAGB2_WR_GMI_CNTL 0x013f
#define regDAGB2_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB2_WR_ADDR_DAGB 0x0140
#define regDAGB2_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0x0141
#define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0x0142
#define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB2_WR_CGTT_CLK_CTRL 0x0143
#define regDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0x0144
#define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0x0145
#define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB2_WR_ADDR_DAGB_MAX_BURST0 0x0146
#define regDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0x0147
#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB2_WR_ADDR_DAGB_MAX_BURST1 0x0148
#define regDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0x0149
#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB2_WR_DATA_DAGB 0x014a
#define regDAGB2_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB2_WR_DATA_DAGB_MAX_BURST0 0x014b
#define regDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0x014c
#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB2_WR_DATA_DAGB_MAX_BURST1 0x014d
#define regDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0x014e
#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB2_WR_VC0_CNTL 0x014f
#define regDAGB2_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC1_CNTL 0x0150
#define regDAGB2_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC2_CNTL 0x0151
#define regDAGB2_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC3_CNTL 0x0152
#define regDAGB2_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC4_CNTL 0x0153
#define regDAGB2_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC5_CNTL 0x0154
#define regDAGB2_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC6_CNTL 0x0155
#define regDAGB2_WR_VC6_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC7_CNTL 0x0156
#define regDAGB2_WR_VC7_CNTL_BASE_IDX 0
#define regDAGB2_WR_CNTL_MISC 0x0157
#define regDAGB2_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB2_WR_TLB_CREDIT 0x0158
#define regDAGB2_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB2_WR_DATA_CREDIT 0x0159
#define regDAGB2_WR_DATA_CREDIT_BASE_IDX 0
#define regDAGB2_WR_MISC_CREDIT 0x015a
#define regDAGB2_WR_MISC_CREDIT_BASE_IDX 0
#define regDAGB2_WR_OSD_CREDIT_CNTL1 0x015b
#define regDAGB2_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB2_WR_OSD_CREDIT_CNTL2 0x015c
#define regDAGB2_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x015d
#define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE 0x015e
#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x015f
#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB2_WRCLI_ASK_PENDING 0x0160
#define regDAGB2_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_GO_PENDING 0x0161
#define regDAGB2_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_GBLSEND_PENDING 0x0162
#define regDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_TLB_PENDING 0x0163
#define regDAGB2_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_OARB_PENDING 0x0164
#define regDAGB2_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_OSD_PENDING 0x0165
#define regDAGB2_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_DBUS_ASK_PENDING 0x0166
#define regDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_DBUS_GO_PENDING 0x0167
#define regDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB2_DAGB_DLY 0x0168
#define regDAGB2_DAGB_DLY_BASE_IDX 0
#define regDAGB2_CNTL_MISC 0x0169
#define regDAGB2_CNTL_MISC_BASE_IDX 0
#define regDAGB2_CNTL_MISC2 0x016a
#define regDAGB2_CNTL_MISC2_BASE_IDX 0
#define regDAGB2_FATAL_ERROR_CNTL 0x016b
#define regDAGB2_FATAL_ERROR_CNTL_BASE_IDX 0
#define regDAGB2_FATAL_ERROR_CLEAR 0x016c
#define regDAGB2_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB2_FATAL_ERROR_STATUS0 0x016d
#define regDAGB2_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB2_FATAL_ERROR_STATUS1 0x016e
#define regDAGB2_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB2_FATAL_ERROR_STATUS2 0x016f
#define regDAGB2_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB2_FATAL_ERROR_STATUS3 0x0170
#define regDAGB2_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB2_FIFO_EMPTY 0x0171
#define regDAGB2_FIFO_EMPTY_BASE_IDX 0
#define regDAGB2_FIFO_FULL 0x0172
#define regDAGB2_FIFO_FULL_BASE_IDX 0
#define regDAGB2_WR_CREDITS_FULL 0x0173
#define regDAGB2_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB2_RD_CREDITS_FULL 0x0174
#define regDAGB2_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB2_PERFCOUNTER_LO 0x0175
#define regDAGB2_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB2_PERFCOUNTER_HI 0x0176
#define regDAGB2_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB2_PERFCOUNTER0_CFG 0x0177
#define regDAGB2_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB2_PERFCOUNTER1_CFG 0x0178
#define regDAGB2_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB2_PERFCOUNTER2_CFG 0x0179
#define regDAGB2_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB2_PERFCOUNTER_RSLT_CNTL 0x017a
#define regDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB2_L1TLB_REG_RW 0x017b
#define regDAGB2_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB2_RESERVE1 0x017c
#define regDAGB2_RESERVE1_BASE_IDX 0
#define regDAGB2_RESERVE2 0x017d
#define regDAGB2_RESERVE2_BASE_IDX 0
#define regDAGB2_RESERVE3 0x017e
#define regDAGB2_RESERVE3_BASE_IDX 0
#define regDAGB2_RESERVE4 0x017f
#define regDAGB2_RESERVE4_BASE_IDX 0
// addressBlock: mmhub_dagb_dagbdec3
// base address: 0x68600
#define regDAGB3_RDCLI0 0x0180
#define regDAGB3_RDCLI0_BASE_IDX 0
#define regDAGB3_RDCLI1 0x0181
#define regDAGB3_RDCLI1_BASE_IDX 0
#define regDAGB3_RDCLI2 0x0182
#define regDAGB3_RDCLI2_BASE_IDX 0
#define regDAGB3_RDCLI3 0x0183
#define regDAGB3_RDCLI3_BASE_IDX 0
#define regDAGB3_RDCLI4 0x0184
#define regDAGB3_RDCLI4_BASE_IDX 0
#define regDAGB3_RDCLI5 0x0185
#define regDAGB3_RDCLI5_BASE_IDX 0
#define regDAGB3_RDCLI6 0x0186
#define regDAGB3_RDCLI6_BASE_IDX 0
#define regDAGB3_RDCLI7 0x0187
#define regDAGB3_RDCLI7_BASE_IDX 0
#define regDAGB3_RDCLI8 0x0188
#define regDAGB3_RDCLI8_BASE_IDX 0
#define regDAGB3_RDCLI9 0x0189
#define regDAGB3_RDCLI9_BASE_IDX 0
#define regDAGB3_RDCLI10 0x018a
#define regDAGB3_RDCLI10_BASE_IDX 0
#define regDAGB3_RDCLI11 0x018b
#define regDAGB3_RDCLI11_BASE_IDX 0
#define regDAGB3_RDCLI12 0x018c
#define regDAGB3_RDCLI12_BASE_IDX 0
#define regDAGB3_RDCLI13 0x018d
#define regDAGB3_RDCLI13_BASE_IDX 0
#define regDAGB3_RDCLI14 0x018e
#define regDAGB3_RDCLI14_BASE_IDX 0
#define regDAGB3_RDCLI15 0x018f
#define regDAGB3_RDCLI15_BASE_IDX 0
#define regDAGB3_RD_CNTL 0x0190
#define regDAGB3_RD_CNTL_BASE_IDX 0
#define regDAGB3_RD_GMI_CNTL 0x0191
#define regDAGB3_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB3_RD_ADDR_DAGB 0x0192
#define regDAGB3_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0x0193
#define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0x0194
#define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB3_RD_CGTT_CLK_CTRL 0x0195
#define regDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0x0196
#define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0x0197
#define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB3_RD_ADDR_DAGB_MAX_BURST0 0x0198
#define regDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0x0199
#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB3_RD_ADDR_DAGB_MAX_BURST1 0x019a
#define regDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0x019b
#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB3_RD_VC0_CNTL 0x019c
#define regDAGB3_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC1_CNTL 0x019d
#define regDAGB3_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC2_CNTL 0x019e
#define regDAGB3_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC3_CNTL 0x019f
#define regDAGB3_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC4_CNTL 0x01a0
#define regDAGB3_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC5_CNTL 0x01a1
#define regDAGB3_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC6_CNTL 0x01a2
#define regDAGB3_RD_VC6_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC7_CNTL 0x01a3
#define regDAGB3_RD_VC7_CNTL_BASE_IDX 0
#define regDAGB3_RD_CNTL_MISC 0x01a4
#define regDAGB3_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB3_RD_TLB_CREDIT 0x01a5
#define regDAGB3_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB3_RD_RDRET_CREDIT_CNTL 0x01a6
#define regDAGB3_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
#define regDAGB3_RD_RDRET_CREDIT_CNTL2 0x01a7
#define regDAGB3_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB3_RDCLI_ASK_PENDING 0x01a8
#define regDAGB3_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB3_RDCLI_GO_PENDING 0x01a9
#define regDAGB3_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB3_RDCLI_GBLSEND_PENDING 0x01aa
#define regDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB3_RDCLI_TLB_PENDING 0x01ab
#define regDAGB3_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB3_RDCLI_OARB_PENDING 0x01ac
#define regDAGB3_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB3_RDCLI_OSD_PENDING 0x01ad
#define regDAGB3_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI0 0x01ae
#define regDAGB3_WRCLI0_BASE_IDX 0
#define regDAGB3_WRCLI1 0x01af
#define regDAGB3_WRCLI1_BASE_IDX 0
#define regDAGB3_WRCLI2 0x01b0
#define regDAGB3_WRCLI2_BASE_IDX 0
#define regDAGB3_WRCLI3 0x01b1
#define regDAGB3_WRCLI3_BASE_IDX 0
#define regDAGB3_WRCLI4 0x01b2
#define regDAGB3_WRCLI4_BASE_IDX 0
#define regDAGB3_WRCLI5 0x01b3
#define regDAGB3_WRCLI5_BASE_IDX 0
#define regDAGB3_WRCLI6 0x01b4
#define regDAGB3_WRCLI6_BASE_IDX 0
#define regDAGB3_WRCLI7 0x01b5
#define regDAGB3_WRCLI7_BASE_IDX 0
#define regDAGB3_WRCLI8 0x01b6
#define regDAGB3_WRCLI8_BASE_IDX 0
#define regDAGB3_WRCLI9 0x01b7
#define regDAGB3_WRCLI9_BASE_IDX 0
#define regDAGB3_WRCLI10 0x01b8
#define regDAGB3_WRCLI10_BASE_IDX 0
#define regDAGB3_WRCLI11 0x01b9
#define regDAGB3_WRCLI11_BASE_IDX 0
#define regDAGB3_WRCLI12 0x01ba
#define regDAGB3_WRCLI12_BASE_IDX 0
#define regDAGB3_WRCLI13 0x01bb
#define regDAGB3_WRCLI13_BASE_IDX 0
#define regDAGB3_WRCLI14 0x01bc
#define regDAGB3_WRCLI14_BASE_IDX 0
#define regDAGB3_WRCLI15 0x01bd
#define regDAGB3_WRCLI15_BASE_IDX 0
#define regDAGB3_WR_CNTL 0x01be
#define regDAGB3_WR_CNTL_BASE_IDX 0
#define regDAGB3_WR_GMI_CNTL 0x01bf
#define regDAGB3_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB3_WR_ADDR_DAGB 0x01c0
#define regDAGB3_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0x01c1
#define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0x01c2
#define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB3_WR_CGTT_CLK_CTRL 0x01c3
#define regDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0x01c4
#define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0x01c5
#define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB3_WR_ADDR_DAGB_MAX_BURST0 0x01c6
#define regDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0x01c7
#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB3_WR_ADDR_DAGB_MAX_BURST1 0x01c8
#define regDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0x01c9
#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB3_WR_DATA_DAGB 0x01ca
#define regDAGB3_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB3_WR_DATA_DAGB_MAX_BURST0 0x01cb
#define regDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0x01cc
#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB3_WR_DATA_DAGB_MAX_BURST1 0x01cd
#define regDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0x01ce
#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB3_WR_VC0_CNTL 0x01cf
#define regDAGB3_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC1_CNTL 0x01d0
#define regDAGB3_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC2_CNTL 0x01d1
#define regDAGB3_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC3_CNTL 0x01d2
#define regDAGB3_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC4_CNTL 0x01d3
#define regDAGB3_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC5_CNTL 0x01d4
#define regDAGB3_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC6_CNTL 0x01d5
#define regDAGB3_WR_VC6_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC7_CNTL 0x01d6
#define regDAGB3_WR_VC7_CNTL_BASE_IDX 0
#define regDAGB3_WR_CNTL_MISC 0x01d7
#define regDAGB3_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB3_WR_TLB_CREDIT 0x01d8
#define regDAGB3_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB3_WR_DATA_CREDIT 0x01d9
#define regDAGB3_WR_DATA_CREDIT_BASE_IDX 0
#define regDAGB3_WR_MISC_CREDIT 0x01da
#define regDAGB3_WR_MISC_CREDIT_BASE_IDX 0
#define regDAGB3_WR_OSD_CREDIT_CNTL1 0x01db
#define regDAGB3_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB3_WR_OSD_CREDIT_CNTL2 0x01dc
#define regDAGB3_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x01dd
#define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE 0x01de
#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x01df
#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB3_WRCLI_ASK_PENDING 0x01e0
#define regDAGB3_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_GO_PENDING 0x01e1
#define regDAGB3_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_GBLSEND_PENDING 0x01e2
#define regDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_TLB_PENDING 0x01e3
#define regDAGB3_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_OARB_PENDING 0x01e4
#define regDAGB3_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_OSD_PENDING 0x01e5
#define regDAGB3_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_DBUS_ASK_PENDING 0x01e6
#define regDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_DBUS_GO_PENDING 0x01e7
#define regDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB3_DAGB_DLY 0x01e8
#define regDAGB3_DAGB_DLY_BASE_IDX 0
#define regDAGB3_CNTL_MISC 0x01e9
#define regDAGB3_CNTL_MISC_BASE_IDX 0
#define regDAGB3_CNTL_MISC2 0x01ea
#define regDAGB3_CNTL_MISC2_BASE_IDX 0
#define regDAGB3_FATAL_ERROR_CNTL 0x01eb
#define regDAGB3_FATAL_ERROR_CNTL_BASE_IDX 0
#define regDAGB3_FATAL_ERROR_CLEAR 0x01ec
#define regDAGB3_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB3_FATAL_ERROR_STATUS0 0x01ed
#define regDAGB3_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB3_FATAL_ERROR_STATUS1 0x01ee
#define regDAGB3_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB3_FATAL_ERROR_STATUS2 0x01ef
#define regDAGB3_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB3_FATAL_ERROR_STATUS3 0x01f0
#define regDAGB3_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB3_FIFO_EMPTY 0x01f1
#define regDAGB3_FIFO_EMPTY_BASE_IDX 0
#define regDAGB3_FIFO_FULL 0x01f2
#define regDAGB3_FIFO_FULL_BASE_IDX 0
#define regDAGB3_WR_CREDITS_FULL 0x01f3
#define regDAGB3_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB3_RD_CREDITS_FULL 0x01f4
#define regDAGB3_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB3_PERFCOUNTER_LO 0x01f5
#define regDAGB3_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB3_PERFCOUNTER_HI 0x01f6
#define regDAGB3_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB3_PERFCOUNTER0_CFG 0x01f7
#define regDAGB3_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB3_PERFCOUNTER1_CFG 0x01f8
#define regDAGB3_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB3_PERFCOUNTER2_CFG 0x01f9
#define regDAGB3_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB3_PERFCOUNTER_RSLT_CNTL 0x01fa
#define regDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB3_L1TLB_REG_RW 0x01fb
#define regDAGB3_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB3_RESERVE1 0x01fc
#define regDAGB3_RESERVE1_BASE_IDX 0
#define regDAGB3_RESERVE2 0x01fd
#define regDAGB3_RESERVE2_BASE_IDX 0
#define regDAGB3_RESERVE3 0x01fe
#define regDAGB3_RESERVE3_BASE_IDX 0
#define regDAGB3_RESERVE4 0x01ff
#define regDAGB3_RESERVE4_BASE_IDX 0
// addressBlock: mmhub_dagb_dagbdec4
// base address: 0x68800
#define regDAGB4_RDCLI0 0x0200
#define regDAGB4_RDCLI0_BASE_IDX 0
#define regDAGB4_RDCLI1 0x0201
#define regDAGB4_RDCLI1_BASE_IDX 0
#define regDAGB4_RDCLI2 0x0202
#define regDAGB4_RDCLI2_BASE_IDX 0
#define regDAGB4_RDCLI3 0x0203
#define regDAGB4_RDCLI3_BASE_IDX 0
#define regDAGB4_RDCLI4 0x0204
#define regDAGB4_RDCLI4_BASE_IDX 0
#define regDAGB4_RDCLI5 0x0205
#define regDAGB4_RDCLI5_BASE_IDX 0
#define regDAGB4_RDCLI6 0x0206
#define regDAGB4_RDCLI6_BASE_IDX 0
#define regDAGB4_RDCLI7 0x0207
#define regDAGB4_RDCLI7_BASE_IDX 0
#define regDAGB4_RDCLI8 0x0208
#define regDAGB4_RDCLI8_BASE_IDX 0
#define regDAGB4_RDCLI9 0x0209
#define regDAGB4_RDCLI9_BASE_IDX 0
#define regDAGB4_RDCLI10 0x020a
#define regDAGB4_RDCLI10_BASE_IDX 0
#define regDAGB4_RDCLI11 0x020b
#define regDAGB4_RDCLI11_BASE_IDX 0
#define regDAGB4_RDCLI12 0x020c
#define regDAGB4_RDCLI12_BASE_IDX 0
#define regDAGB4_RDCLI13 0x020d
#define regDAGB4_RDCLI13_BASE_IDX 0
#define regDAGB4_RDCLI14 0x020e
#define regDAGB4_RDCLI14_BASE_IDX 0
#define regDAGB4_RDCLI15 0x020f
#define regDAGB4_RDCLI15_BASE_IDX 0
#define regDAGB4_RD_CNTL 0x0210
#define regDAGB4_RD_CNTL_BASE_IDX 0
#define regDAGB4_RD_GMI_CNTL 0x0211
#define regDAGB4_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB4_RD_ADDR_DAGB 0x0212
#define regDAGB4_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0x0213
#define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0x0214
#define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB4_RD_CGTT_CLK_CTRL 0x0215
#define regDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0x0216
#define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0x0217
#define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB4_RD_ADDR_DAGB_MAX_BURST0 0x0218
#define regDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0x0219
#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB4_RD_ADDR_DAGB_MAX_BURST1 0x021a
#define regDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0x021b
#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB4_RD_VC0_CNTL 0x021c
#define regDAGB4_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC1_CNTL 0x021d
#define regDAGB4_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC2_CNTL 0x021e
#define regDAGB4_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC3_CNTL 0x021f
#define regDAGB4_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC4_CNTL 0x0220
#define regDAGB4_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC5_CNTL 0x0221
#define regDAGB4_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC6_CNTL 0x0222
#define regDAGB4_RD_VC6_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC7_CNTL 0x0223
#define regDAGB4_RD_VC7_CNTL_BASE_IDX 0
#define regDAGB4_RD_CNTL_MISC 0x0224
#define regDAGB4_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB4_RD_TLB_CREDIT 0x0225
#define regDAGB4_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB4_RD_RDRET_CREDIT_CNTL 0x0226
#define regDAGB4_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
#define regDAGB4_RD_RDRET_CREDIT_CNTL2 0x0227
#define regDAGB4_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB4_RDCLI_ASK_PENDING 0x0228
#define regDAGB4_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB4_RDCLI_GO_PENDING 0x0229
#define regDAGB4_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB4_RDCLI_GBLSEND_PENDING 0x022a
#define regDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB4_RDCLI_TLB_PENDING 0x022b
#define regDAGB4_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB4_RDCLI_OARB_PENDING 0x022c
#define regDAGB4_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB4_RDCLI_OSD_PENDING 0x022d
#define regDAGB4_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI0 0x022e
#define regDAGB4_WRCLI0_BASE_IDX 0
#define regDAGB4_WRCLI1 0x022f
#define regDAGB4_WRCLI1_BASE_IDX 0
#define regDAGB4_WRCLI2 0x0230
#define regDAGB4_WRCLI2_BASE_IDX 0
#define regDAGB4_WRCLI3 0x0231
#define regDAGB4_WRCLI3_BASE_IDX 0
#define regDAGB4_WRCLI4 0x0232
#define regDAGB4_WRCLI4_BASE_IDX 0
#define regDAGB4_WRCLI5 0x0233
#define regDAGB4_WRCLI5_BASE_IDX 0
#define regDAGB4_WRCLI6 0x0234
#define regDAGB4_WRCLI6_BASE_IDX 0
#define regDAGB4_WRCLI7 0x0235
#define regDAGB4_WRCLI7_BASE_IDX 0
#define regDAGB4_WRCLI8 0x0236
#define regDAGB4_WRCLI8_BASE_IDX 0
#define regDAGB4_WRCLI9 0x0237
#define regDAGB4_WRCLI9_BASE_IDX 0
#define regDAGB4_WRCLI10 0x0238
#define regDAGB4_WRCLI10_BASE_IDX 0
#define regDAGB4_WRCLI11 0x0239
#define regDAGB4_WRCLI11_BASE_IDX 0
#define regDAGB4_WRCLI12 0x023a
#define regDAGB4_WRCLI12_BASE_IDX 0
#define regDAGB4_WRCLI13 0x023b
#define regDAGB4_WRCLI13_BASE_IDX 0
#define regDAGB4_WRCLI14 0x023c
#define regDAGB4_WRCLI14_BASE_IDX 0
#define regDAGB4_WRCLI15 0x023d
#define regDAGB4_WRCLI15_BASE_IDX 0
#define regDAGB4_WR_CNTL 0x023e
#define regDAGB4_WR_CNTL_BASE_IDX 0
#define regDAGB4_WR_GMI_CNTL 0x023f
#define regDAGB4_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB4_WR_ADDR_DAGB 0x0240
#define regDAGB4_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0x0241
#define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0x0242
#define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB4_WR_CGTT_CLK_CTRL 0x0243
#define regDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0x0244
#define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0x0245
#define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB4_WR_ADDR_DAGB_MAX_BURST0 0x0246
#define regDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0x0247
#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB4_WR_ADDR_DAGB_MAX_BURST1 0x0248
#define regDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0x0249
#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB4_WR_DATA_DAGB 0x024a
#define regDAGB4_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB4_WR_DATA_DAGB_MAX_BURST0 0x024b
#define regDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0x024c
#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB4_WR_DATA_DAGB_MAX_BURST1 0x024d
#define regDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0x024e
#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB4_WR_VC0_CNTL 0x024f
#define regDAGB4_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC1_CNTL 0x0250
#define regDAGB4_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC2_CNTL 0x0251
#define regDAGB4_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC3_CNTL 0x0252
#define regDAGB4_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC4_CNTL 0x0253
#define regDAGB4_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC5_CNTL 0x0254
#define regDAGB4_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC6_CNTL 0x0255
#define regDAGB4_WR_VC6_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC7_CNTL 0x0256
#define regDAGB4_WR_VC7_CNTL_BASE_IDX 0
#define regDAGB4_WR_CNTL_MISC 0x0257
#define regDAGB4_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB4_WR_TLB_CREDIT 0x0258
#define regDAGB4_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB4_WR_DATA_CREDIT 0x0259
#define regDAGB4_WR_DATA_CREDIT_BASE_IDX 0
#define regDAGB4_WR_MISC_CREDIT 0x025a
#define regDAGB4_WR_MISC_CREDIT_BASE_IDX 0
#define regDAGB4_WR_OSD_CREDIT_CNTL1 0x025b
#define regDAGB4_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB4_WR_OSD_CREDIT_CNTL2 0x025c
#define regDAGB4_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x025d
#define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE 0x025e
#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x025f
#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB4_WRCLI_ASK_PENDING 0x0260
#define regDAGB4_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_GO_PENDING 0x0261
#define regDAGB4_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_GBLSEND_PENDING 0x0262
#define regDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_TLB_PENDING 0x0263
#define regDAGB4_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_OARB_PENDING 0x0264
#define regDAGB4_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_OSD_PENDING 0x0265
#define regDAGB4_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_DBUS_ASK_PENDING 0x0266
#define regDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_DBUS_GO_PENDING 0x0267
#define regDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB4_DAGB_DLY 0x0268
#define regDAGB4_DAGB_DLY_BASE_IDX 0
#define regDAGB4_CNTL_MISC 0x0269
#define regDAGB4_CNTL_MISC_BASE_IDX 0
#define regDAGB4_CNTL_MISC2 0x026a
#define regDAGB4_CNTL_MISC2_BASE_IDX 0
#define regDAGB4_FATAL_ERROR_CNTL 0x026b
#define regDAGB4_FATAL_ERROR_CNTL_BASE_IDX 0
#define regDAGB4_FATAL_ERROR_CLEAR 0x026c
#define regDAGB4_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB4_FATAL_ERROR_STATUS0 0x026d
#define regDAGB4_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB4_FATAL_ERROR_STATUS1 0x026e
#define regDAGB4_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB4_FATAL_ERROR_STATUS2 0x026f
#define regDAGB4_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB4_FATAL_ERROR_STATUS3 0x0270
#define regDAGB4_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB4_FIFO_EMPTY 0x0271
#define regDAGB4_FIFO_EMPTY_BASE_IDX 0
#define regDAGB4_FIFO_FULL 0x0272
#define regDAGB4_FIFO_FULL_BASE_IDX 0
#define regDAGB4_WR_CREDITS_FULL 0x0273
#define regDAGB4_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB4_RD_CREDITS_FULL 0x0274
#define regDAGB4_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB4_PERFCOUNTER_LO 0x0275
#define regDAGB4_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB4_PERFCOUNTER_HI 0x0276
#define regDAGB4_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB4_PERFCOUNTER0_CFG 0x0277
#define regDAGB4_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB4_PERFCOUNTER1_CFG 0x0278
#define regDAGB4_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB4_PERFCOUNTER2_CFG 0x0279
#define regDAGB4_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB4_PERFCOUNTER_RSLT_CNTL 0x027a
#define regDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB4_L1TLB_REG_RW 0x027b
#define regDAGB4_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB4_RESERVE1 0x027c
#define regDAGB4_RESERVE1_BASE_IDX 0
#define regDAGB4_RESERVE2 0x027d
#define regDAGB4_RESERVE2_BASE_IDX 0
#define regDAGB4_RESERVE3 0x027e
#define regDAGB4_RESERVE3_BASE_IDX 0
#define regDAGB4_RESERVE4 0x027f
#define regDAGB4_RESERVE4_BASE_IDX 0
// addressBlock: mmhub_dagb_dagbdec5
// base address: 0x68a00
#define regDAGB5_RDCLI0 0x0280
#define regDAGB5_RDCLI0_BASE_IDX 0
#define regDAGB5_RDCLI1 0x0281
#define regDAGB5_RDCLI1_BASE_IDX 0
#define regDAGB5_RDCLI2 0x0282
#define regDAGB5_RDCLI2_BASE_IDX 0
#define regDAGB5_RDCLI3 0x0283
#define regDAGB5_RDCLI3_BASE_IDX 0
#define regDAGB5_RDCLI4 0x0284
#define regDAGB5_RDCLI4_BASE_IDX 0
#define regDAGB5_RDCLI5 0x0285
#define regDAGB5_RDCLI5_BASE_IDX 0
#define regDAGB5_RDCLI6 0x0286
#define regDAGB5_RDCLI6_BASE_IDX 0
#define regDAGB5_RDCLI7 0x0287
#define regDAGB5_RDCLI7_BASE_IDX 0
#define regDAGB5_RDCLI8 0x0288
#define regDAGB5_RDCLI8_BASE_IDX 0
#define regDAGB5_RDCLI9 0x0289
#define regDAGB5_RDCLI9_BASE_IDX 0
#define regDAGB5_RDCLI10 0x028a
#define regDAGB5_RDCLI10_BASE_IDX 0
#define regDAGB5_RDCLI11 0x028b
#define regDAGB5_RDCLI11_BASE_IDX 0
#define regDAGB5_RDCLI12 0x028c
#define regDAGB5_RDCLI12_BASE_IDX 0
#define regDAGB5_RDCLI13 0x028d
#define regDAGB5_RDCLI13_BASE_IDX 0
#define regDAGB5_RDCLI14 0x028e
#define regDAGB5_RDCLI14_BASE_IDX 0
#define regDAGB5_RDCLI15 0x028f
#define regDAGB5_RDCLI15_BASE_IDX 0
#define regDAGB5_RD_CNTL 0x0290
#define regDAGB5_RD_CNTL_BASE_IDX 0
#define regDAGB5_RD_GMI_CNTL 0x0291
#define regDAGB5_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB5_RD_ADDR_DAGB 0x0292
#define regDAGB5_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB5_RD_OUTPUT_DAGB_MAX_BURST 0x0293
#define regDAGB5_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 0x0294
#define regDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB5_RD_CGTT_CLK_CTRL 0x0295
#define regDAGB5_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB5_L1TLB_RD_CGTT_CLK_CTRL 0x0296
#define regDAGB5_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB5_ATCVM_RD_CGTT_CLK_CTRL 0x0297
#define regDAGB5_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB5_RD_ADDR_DAGB_MAX_BURST0 0x0298
#define regDAGB5_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER0 0x0299
#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB5_RD_ADDR_DAGB_MAX_BURST1 0x029a
#define regDAGB5_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER1 0x029b
#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB5_RD_VC0_CNTL 0x029c
#define regDAGB5_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC1_CNTL 0x029d
#define regDAGB5_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC2_CNTL 0x029e
#define regDAGB5_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC3_CNTL 0x029f
#define regDAGB5_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC4_CNTL 0x02a0
#define regDAGB5_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC5_CNTL 0x02a1
#define regDAGB5_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC6_CNTL 0x02a2
#define regDAGB5_RD_VC6_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC7_CNTL 0x02a3
#define regDAGB5_RD_VC7_CNTL_BASE_IDX 0
#define regDAGB5_RD_CNTL_MISC 0x02a4
#define regDAGB5_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB5_RD_TLB_CREDIT 0x02a5
#define regDAGB5_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB5_RD_RDRET_CREDIT_CNTL 0x02a6
#define regDAGB5_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
#define regDAGB5_RD_RDRET_CREDIT_CNTL2 0x02a7
#define regDAGB5_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB5_RDCLI_ASK_PENDING 0x02a8
#define regDAGB5_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB5_RDCLI_GO_PENDING 0x02a9
#define regDAGB5_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB5_RDCLI_GBLSEND_PENDING 0x02aa
#define regDAGB5_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB5_RDCLI_TLB_PENDING 0x02ab
#define regDAGB5_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB5_RDCLI_OARB_PENDING 0x02ac
#define regDAGB5_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB5_RDCLI_OSD_PENDING 0x02ad
#define regDAGB5_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI0 0x02ae
#define regDAGB5_WRCLI0_BASE_IDX 0
#define regDAGB5_WRCLI1 0x02af
#define regDAGB5_WRCLI1_BASE_IDX 0
#define regDAGB5_WRCLI2 0x02b0
#define regDAGB5_WRCLI2_BASE_IDX 0
#define regDAGB5_WRCLI3 0x02b1
#define regDAGB5_WRCLI3_BASE_IDX 0
#define regDAGB5_WRCLI4 0x02b2
#define regDAGB5_WRCLI4_BASE_IDX 0
#define regDAGB5_WRCLI5 0x02b3
#define regDAGB5_WRCLI5_BASE_IDX 0
#define regDAGB5_WRCLI6 0x02b4
#define regDAGB5_WRCLI6_BASE_IDX 0
#define regDAGB5_WRCLI7 0x02b5
#define regDAGB5_WRCLI7_BASE_IDX 0
#define regDAGB5_WRCLI8 0x02b6
#define regDAGB5_WRCLI8_BASE_IDX 0
#define regDAGB5_WRCLI9 0x02b7
#define regDAGB5_WRCLI9_BASE_IDX 0
#define regDAGB5_WRCLI10 0x02b8
#define regDAGB5_WRCLI10_BASE_IDX 0
#define regDAGB5_WRCLI11 0x02b9
#define regDAGB5_WRCLI11_BASE_IDX 0
#define regDAGB5_WRCLI12 0x02ba
#define regDAGB5_WRCLI12_BASE_IDX 0
#define regDAGB5_WRCLI13 0x02bb
#define regDAGB5_WRCLI13_BASE_IDX 0
#define regDAGB5_WRCLI14 0x02bc
#define regDAGB5_WRCLI14_BASE_IDX 0
#define regDAGB5_WRCLI15 0x02bd
#define regDAGB5_WRCLI15_BASE_IDX 0
#define regDAGB5_WR_CNTL 0x02be
#define regDAGB5_WR_CNTL_BASE_IDX 0
#define regDAGB5_WR_GMI_CNTL 0x02bf
#define regDAGB5_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB5_WR_ADDR_DAGB 0x02c0
#define regDAGB5_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB5_WR_OUTPUT_DAGB_MAX_BURST 0x02c1
#define regDAGB5_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 0x02c2
#define regDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB5_WR_CGTT_CLK_CTRL 0x02c3
#define regDAGB5_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB5_L1TLB_WR_CGTT_CLK_CTRL 0x02c4
#define regDAGB5_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB5_ATCVM_WR_CGTT_CLK_CTRL 0x02c5
#define regDAGB5_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB5_WR_ADDR_DAGB_MAX_BURST0 0x02c6
#define regDAGB5_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER0 0x02c7
#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB5_WR_ADDR_DAGB_MAX_BURST1 0x02c8
#define regDAGB5_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER1 0x02c9
#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB5_WR_DATA_DAGB 0x02ca
#define regDAGB5_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB5_WR_DATA_DAGB_MAX_BURST0 0x02cb
#define regDAGB5_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER0 0x02cc
#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB5_WR_DATA_DAGB_MAX_BURST1 0x02cd
#define regDAGB5_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER1 0x02ce
#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB5_WR_VC0_CNTL 0x02cf
#define regDAGB5_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC1_CNTL 0x02d0
#define regDAGB5_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC2_CNTL 0x02d1
#define regDAGB5_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC3_CNTL 0x02d2
#define regDAGB5_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC4_CNTL 0x02d3
#define regDAGB5_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC5_CNTL 0x02d4
#define regDAGB5_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC6_CNTL 0x02d5
#define regDAGB5_WR_VC6_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC7_CNTL 0x02d6
#define regDAGB5_WR_VC7_CNTL_BASE_IDX 0
#define regDAGB5_WR_CNTL_MISC 0x02d7
#define regDAGB5_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB5_WR_TLB_CREDIT 0x02d8
#define regDAGB5_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB5_WR_DATA_CREDIT 0x02d9
#define regDAGB5_WR_DATA_CREDIT_BASE_IDX 0
#define regDAGB5_WR_MISC_CREDIT 0x02da
#define regDAGB5_WR_MISC_CREDIT_BASE_IDX 0
#define regDAGB5_WR_OSD_CREDIT_CNTL1 0x02db
#define regDAGB5_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB5_WR_OSD_CREDIT_CNTL2 0x02dc
#define regDAGB5_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x02dd
#define regDAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE 0x02de
#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x02df
#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB5_WRCLI_ASK_PENDING 0x02e0
#define regDAGB5_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_GO_PENDING 0x02e1
#define regDAGB5_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_GBLSEND_PENDING 0x02e2
#define regDAGB5_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_TLB_PENDING 0x02e3
#define regDAGB5_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_OARB_PENDING 0x02e4
#define regDAGB5_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_OSD_PENDING 0x02e5
#define regDAGB5_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_DBUS_ASK_PENDING 0x02e6
#define regDAGB5_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_DBUS_GO_PENDING 0x02e7
#define regDAGB5_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB5_DAGB_DLY 0x02e8
#define regDAGB5_DAGB_DLY_BASE_IDX 0
#define regDAGB5_CNTL_MISC 0x02e9
#define regDAGB5_CNTL_MISC_BASE_IDX 0
#define regDAGB5_CNTL_MISC2 0x02ea
#define regDAGB5_CNTL_MISC2_BASE_IDX 0
#define regDAGB5_FATAL_ERROR_CNTL 0x02eb
#define regDAGB5_FATAL_ERROR_CNTL_BASE_IDX 0
#define regDAGB5_FATAL_ERROR_CLEAR 0x02ec
#define regDAGB5_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB5_FATAL_ERROR_STATUS0 0x02ed
#define regDAGB5_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB5_FATAL_ERROR_STATUS1 0x02ee
#define regDAGB5_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB5_FATAL_ERROR_STATUS2 0x02ef
#define regDAGB5_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB5_FATAL_ERROR_STATUS3 0x02f0
#define regDAGB5_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB5_FIFO_EMPTY 0x02f1
#define regDAGB5_FIFO_EMPTY_BASE_IDX 0
#define regDAGB5_FIFO_FULL 0x02f2
#define regDAGB5_FIFO_FULL_BASE_IDX 0
#define regDAGB5_WR_CREDITS_FULL 0x02f3
#define regDAGB5_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB5_RD_CREDITS_FULL 0x02f4
#define regDAGB5_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB5_PERFCOUNTER_LO 0x02f5
#define regDAGB5_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB5_PERFCOUNTER_HI 0x02f6
#define regDAGB5_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB5_PERFCOUNTER0_CFG 0x02f7
#define regDAGB5_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB5_PERFCOUNTER1_CFG 0x02f8
#define regDAGB5_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB5_PERFCOUNTER2_CFG 0x02f9
#define regDAGB5_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB5_PERFCOUNTER_RSLT_CNTL 0x02fa
#define regDAGB5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB5_L1TLB_REG_RW 0x02fb
#define regDAGB5_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB5_RESERVE1 0x02fc
#define regDAGB5_RESERVE1_BASE_IDX 0
#define regDAGB5_RESERVE2 0x02fd
#define regDAGB5_RESERVE2_BASE_IDX 0
#define regDAGB5_RESERVE3 0x02fe
#define regDAGB5_RESERVE3_BASE_IDX 0
#define regDAGB5_RESERVE4 0x02ff
#define regDAGB5_RESERVE4_BASE_IDX 0
// addressBlock: mmhub_ea_mmeadec0
// base address: 0x68c00
#define regMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0300
#define regMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0301
#define regMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0302
#define regMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0303
#define regMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA0_DRAM_RD_GRP2VC_MAP 0x0304
#define regMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA0_DRAM_WR_GRP2VC_MAP 0x0305
#define regMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA0_DRAM_RD_LAZY 0x0306
#define regMMEA0_DRAM_RD_LAZY_BASE_IDX 0
#define regMMEA0_DRAM_WR_LAZY 0x0307
#define regMMEA0_DRAM_WR_LAZY_BASE_IDX 0
#define regMMEA0_DRAM_RD_CAM_CNTL 0x0308
#define regMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA0_DRAM_WR_CAM_CNTL 0x0309
#define regMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA0_DRAM_PAGE_BURST 0x030a
#define regMMEA0_DRAM_PAGE_BURST_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_AGE 0x030b
#define regMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_AGE 0x030c
#define regMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_QUEUING 0x030d
#define regMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_QUEUING 0x030e
#define regMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_FIXED 0x030f
#define regMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_FIXED 0x0310
#define regMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_URGENCY 0x0311
#define regMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_URGENCY 0x0312
#define regMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0313
#define regMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0314
#define regMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0315
#define regMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0316
#define regMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0317
#define regMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0318
#define regMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA0_GMI_RD_CLI2GRP_MAP0 0x0319
#define regMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA0_GMI_RD_CLI2GRP_MAP1 0x031a
#define regMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA0_GMI_WR_CLI2GRP_MAP0 0x031b
#define regMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA0_GMI_WR_CLI2GRP_MAP1 0x031c
#define regMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA0_GMI_RD_GRP2VC_MAP 0x031d
#define regMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA0_GMI_WR_GRP2VC_MAP 0x031e
#define regMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA0_GMI_RD_LAZY 0x031f
#define regMMEA0_GMI_RD_LAZY_BASE_IDX 0
#define regMMEA0_GMI_WR_LAZY 0x0320
#define regMMEA0_GMI_WR_LAZY_BASE_IDX 0
#define regMMEA0_GMI_RD_CAM_CNTL 0x0321
#define regMMEA0_GMI_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA0_GMI_WR_CAM_CNTL 0x0322
#define regMMEA0_GMI_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA0_GMI_PAGE_BURST 0x0323
#define regMMEA0_GMI_PAGE_BURST_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_AGE 0x0324
#define regMMEA0_GMI_RD_PRI_AGE_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_AGE 0x0325
#define regMMEA0_GMI_WR_PRI_AGE_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_QUEUING 0x0326
#define regMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_QUEUING 0x0327
#define regMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_FIXED 0x0328
#define regMMEA0_GMI_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_FIXED 0x0329
#define regMMEA0_GMI_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_URGENCY 0x032a
#define regMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_URGENCY 0x032b
#define regMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_URGENCY_MASKING 0x032c
#define regMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_URGENCY_MASKING 0x032d
#define regMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_QUANT_PRI1 0x032e
#define regMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_QUANT_PRI2 0x032f
#define regMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_QUANT_PRI3 0x0330
#define regMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_QUANT_PRI1 0x0331
#define regMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_QUANT_PRI2 0x0332
#define regMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_QUANT_PRI3 0x0333
#define regMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA0_ADDRNORM_BASE_ADDR0 0x0334
#define regMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0
#define regMMEA0_ADDRNORM_LIMIT_ADDR0 0x0335
#define regMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
#define regMMEA0_ADDRNORM_BASE_ADDR1 0x0336
#define regMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0
#define regMMEA0_ADDRNORM_LIMIT_ADDR1 0x0337
#define regMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
#define regMMEA0_ADDRNORM_OFFSET_ADDR1 0x0338
#define regMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
#define regMMEA0_ADDRNORM_BASE_ADDR2 0x0339
#define regMMEA0_ADDRNORM_BASE_ADDR2_BASE_IDX 0
#define regMMEA0_ADDRNORM_LIMIT_ADDR2 0x033a
#define regMMEA0_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
#define regMMEA0_ADDRNORM_BASE_ADDR3 0x033b
#define regMMEA0_ADDRNORM_BASE_ADDR3_BASE_IDX 0
#define regMMEA0_ADDRNORM_LIMIT_ADDR3 0x033c
#define regMMEA0_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
#define regMMEA0_ADDRNORM_OFFSET_ADDR3 0x033d
#define regMMEA0_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
#define regMMEA0_ADDRNORM_MEGABASE_ADDR0 0x033e
#define regMMEA0_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR0 0x033f
#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
#define regMMEA0_ADDRNORM_MEGABASE_ADDR1 0x0340
#define regMMEA0_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR1 0x0341
#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
#define regMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0343
#define regMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
#define regMMEA0_ADDRNORMGMI_HOLE_CNTL 0x0344
#define regMMEA0_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
#define regMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0345
#define regMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0346
#define regMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA0_ADDRDEC_BANK_CFG 0x0347
#define regMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0
#define regMMEA0_ADDRDEC_MISC_CFG 0x0348
#define regMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0
#define regMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0353
#define regMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA0_ADDRDECGMI_HARVEST_ENABLE 0x035e
#define regMMEA0_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x035f
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0360
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x0361
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x0362
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x0363
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x0364
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x0365
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x0366
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x0367
#define regMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0368
#define regMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0369
#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x036a
#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x036b
#define regMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x036c
#define regMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x036d
#define regMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x036e
#define regMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0x036f
#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0x0370
#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0371
#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0372
#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x0373
#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x0374
#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_RM_SEL_CS01 0x0375
#define regMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_RM_SEL_CS23 0x0376
#define regMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x0377
#define regMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x0378
#define regMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0379
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x037a
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x037b
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x037c
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x037d
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x037e
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x037f
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0380
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0381
#define regMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0382
#define regMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0383
#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0384
#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0385
#define regMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x0386
#define regMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x0387
#define regMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0388
#define regMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0x0389
#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0x038a
#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x038b
#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x038c
#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x038d
#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x038e
#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_RM_SEL_CS01 0x038f
#define regMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_RM_SEL_CS23 0x0390
#define regMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0391
#define regMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0392
#define regMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS0 0x0393
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS1 0x0394
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS2 0x0395
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS3 0x0396
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 0x0397
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 0x0398
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 0x0399
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 0x039a
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_MASK_CS01 0x039b
#define regMMEA0_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_MASK_CS23 0x039c
#define regMMEA0_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 0x039d
#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 0x039e
#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_CFG_CS01 0x039f
#define regMMEA0_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_CFG_CS23 0x03a0
#define regMMEA0_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_SEL_CS01 0x03a1
#define regMMEA0_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_SEL_CS23 0x03a2
#define regMMEA0_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS01 0x03a3
#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS23 0x03a4
#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS01 0x03a5
#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS23 0x03a6
#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS01 0x03a7
#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS23 0x03a8
#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_RM_SEL_CS01 0x03a9
#define regMMEA0_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_RM_SEL_CS23 0x03aa
#define regMMEA0_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_RM_SEL_SECCS01 0x03ab
#define regMMEA0_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_RM_SEL_SECCS23 0x03ac
#define regMMEA0_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0x03ad
#define regMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA0_ADDRNORMGMI_GLOBAL_CNTL 0x03ae
#define regMMEA0_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR0 0x03d1
#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR1 0x03d2
#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
#define regMMEA0_ADDRNORMDRAM_MASKING 0x03d3
#define regMMEA0_ADDRNORMDRAM_MASKING_BASE_IDX 0
#define regMMEA0_ADDRNORMGMI_MASKING 0x03d4
#define regMMEA0_ADDRNORMGMI_MASKING_BASE_IDX 0
#define regMMEA0_IO_RD_CLI2GRP_MAP0 0x03d5
#define regMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA0_IO_RD_CLI2GRP_MAP1 0x03d6
#define regMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA0_IO_WR_CLI2GRP_MAP0 0x03d7
#define regMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA0_IO_WR_CLI2GRP_MAP1 0x03d8
#define regMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA0_IO_RD_COMBINE_FLUSH 0x03d9
#define regMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA0_IO_WR_COMBINE_FLUSH 0x03da
#define regMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA0_IO_GROUP_BURST 0x03db
#define regMMEA0_IO_GROUP_BURST_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_AGE 0x03dc
#define regMMEA0_IO_RD_PRI_AGE_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_AGE 0x03dd
#define regMMEA0_IO_WR_PRI_AGE_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_QUEUING 0x03de
#define regMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_QUEUING 0x03df
#define regMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_FIXED 0x03e0
#define regMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_FIXED 0x03e1
#define regMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_URGENCY 0x03e2
#define regMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_URGENCY 0x03e3
#define regMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_URGENCY_MASKING 0x03e4
#define regMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_URGENCY_MASKING 0x03e5
#define regMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_QUANT_PRI1 0x03e6
#define regMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_QUANT_PRI2 0x03e7
#define regMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_QUANT_PRI3 0x03e8
#define regMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_QUANT_PRI1 0x03e9
#define regMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_QUANT_PRI2 0x03ea
#define regMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_QUANT_PRI3 0x03eb
#define regMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA0_SDP_ARB_DRAM 0x03ec
#define regMMEA0_SDP_ARB_DRAM_BASE_IDX 0
#define regMMEA0_SDP_ARB_GMI 0x03ed
#define regMMEA0_SDP_ARB_GMI_BASE_IDX 0
#define regMMEA0_SDP_ARB_FINAL 0x03ee
#define regMMEA0_SDP_ARB_FINAL_BASE_IDX 0
#define regMMEA0_SDP_DRAM_PRIORITY 0x03ef
#define regMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0
#define regMMEA0_SDP_GMI_PRIORITY 0x03f0
#define regMMEA0_SDP_GMI_PRIORITY_BASE_IDX 0
#define regMMEA0_SDP_IO_PRIORITY 0x03f1
#define regMMEA0_SDP_IO_PRIORITY_BASE_IDX 0
#define regMMEA0_SDP_CREDITS 0x03f2
#define regMMEA0_SDP_CREDITS_BASE_IDX 0
#define regMMEA0_SDP_TAG_RESERVE0 0x03f3
#define regMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0
#define regMMEA0_SDP_TAG_RESERVE1 0x03f4
#define regMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0
#define regMMEA0_SDP_VCC_RESERVE0 0x03f5
#define regMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0
#define regMMEA0_SDP_VCC_RESERVE1 0x03f6
#define regMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0
#define regMMEA0_SDP_VCD_RESERVE0 0x03f7
#define regMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0
#define regMMEA0_SDP_VCD_RESERVE1 0x03f8
#define regMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0
#define regMMEA0_SDP_REQ_CNTL 0x03f9
#define regMMEA0_SDP_REQ_CNTL_BASE_IDX 0
#define regMMEA0_MISC 0x03fa
#define regMMEA0_MISC_BASE_IDX 0
#define regMMEA0_LATENCY_SAMPLING 0x03fb
#define regMMEA0_LATENCY_SAMPLING_BASE_IDX 0
#define regMMEA0_PERFCOUNTER_LO 0x03fc
#define regMMEA0_PERFCOUNTER_LO_BASE_IDX 0
#define regMMEA0_PERFCOUNTER_HI 0x03fd
#define regMMEA0_PERFCOUNTER_HI_BASE_IDX 0
#define regMMEA0_PERFCOUNTER0_CFG 0x03fe
#define regMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0
#define regMMEA0_PERFCOUNTER1_CFG 0x03ff
#define regMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0
#define regMMEA0_PERFCOUNTER_RSLT_CNTL 0x0400
#define regMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regMMEA0_EDC_CNT 0x0406
#define regMMEA0_EDC_CNT_BASE_IDX 0
#define regMMEA0_EDC_CNT2 0x0407
#define regMMEA0_EDC_CNT2_BASE_IDX 0
#define regMMEA0_DSM_CNTL 0x0408
#define regMMEA0_DSM_CNTL_BASE_IDX 0
#define regMMEA0_DSM_CNTLA 0x0409
#define regMMEA0_DSM_CNTLA_BASE_IDX 0
#define regMMEA0_DSM_CNTLB 0x040a
#define regMMEA0_DSM_CNTLB_BASE_IDX 0
#define regMMEA0_DSM_CNTL2 0x040b
#define regMMEA0_DSM_CNTL2_BASE_IDX 0
#define regMMEA0_DSM_CNTL2A 0x040c
#define regMMEA0_DSM_CNTL2A_BASE_IDX 0
#define regMMEA0_DSM_CNTL2B 0x040d
#define regMMEA0_DSM_CNTL2B_BASE_IDX 0
#define regMMEA0_CGTT_CLK_CTRL 0x040f
#define regMMEA0_CGTT_CLK_CTRL_BASE_IDX 0
#define regMMEA0_EDC_MODE 0x0410
#define regMMEA0_EDC_MODE_BASE_IDX 0
#define regMMEA0_ERR_STATUS 0x0411
#define regMMEA0_ERR_STATUS_BASE_IDX 0
#define regMMEA0_MISC2 0x0412
#define regMMEA0_MISC2_BASE_IDX 0
#define regMMEA0_ADDRDEC_SELECT 0x0413
#define regMMEA0_ADDRDEC_SELECT_BASE_IDX 0
#define regMMEA0_EDC_CNT3 0x0414
#define regMMEA0_EDC_CNT3_BASE_IDX 0
#define regMMEA0_MISC_AON 0x0415
#define regMMEA0_MISC_AON_BASE_IDX 0
// addressBlock: mmhub_ea_mmeadec1
// base address: 0x69100
#define regMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0440
#define regMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0441
#define regMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0442
#define regMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0443
#define regMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA1_DRAM_RD_GRP2VC_MAP 0x0444
#define regMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA1_DRAM_WR_GRP2VC_MAP 0x0445
#define regMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA1_DRAM_RD_LAZY 0x0446
#define regMMEA1_DRAM_RD_LAZY_BASE_IDX 0
#define regMMEA1_DRAM_WR_LAZY 0x0447
#define regMMEA1_DRAM_WR_LAZY_BASE_IDX 0
#define regMMEA1_DRAM_RD_CAM_CNTL 0x0448
#define regMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA1_DRAM_WR_CAM_CNTL 0x0449
#define regMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA1_DRAM_PAGE_BURST 0x044a
#define regMMEA1_DRAM_PAGE_BURST_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_AGE 0x044b
#define regMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_AGE 0x044c
#define regMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_QUEUING 0x044d
#define regMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_QUEUING 0x044e
#define regMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_FIXED 0x044f
#define regMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_FIXED 0x0450
#define regMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_URGENCY 0x0451
#define regMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_URGENCY 0x0452
#define regMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0453
#define regMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0454
#define regMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0455
#define regMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0456
#define regMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0457
#define regMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0458
#define regMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA1_GMI_RD_CLI2GRP_MAP0 0x0459
#define regMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA1_GMI_RD_CLI2GRP_MAP1 0x045a
#define regMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA1_GMI_WR_CLI2GRP_MAP0 0x045b
#define regMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA1_GMI_WR_CLI2GRP_MAP1 0x045c
#define regMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA1_GMI_RD_GRP2VC_MAP 0x045d
#define regMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA1_GMI_WR_GRP2VC_MAP 0x045e
#define regMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA1_GMI_RD_LAZY 0x045f
#define regMMEA1_GMI_RD_LAZY_BASE_IDX 0
#define regMMEA1_GMI_WR_LAZY 0x0460
#define regMMEA1_GMI_WR_LAZY_BASE_IDX 0
#define regMMEA1_GMI_RD_CAM_CNTL 0x0461
#define regMMEA1_GMI_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA1_GMI_WR_CAM_CNTL 0x0462
#define regMMEA1_GMI_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA1_GMI_PAGE_BURST 0x0463
#define regMMEA1_GMI_PAGE_BURST_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_AGE 0x0464
#define regMMEA1_GMI_RD_PRI_AGE_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_AGE 0x0465
#define regMMEA1_GMI_WR_PRI_AGE_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_QUEUING 0x0466
#define regMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_QUEUING 0x0467
#define regMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_FIXED 0x0468
#define regMMEA1_GMI_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_FIXED 0x0469
#define regMMEA1_GMI_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_URGENCY 0x046a
#define regMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_URGENCY 0x046b
#define regMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_URGENCY_MASKING 0x046c
#define regMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_URGENCY_MASKING 0x046d
#define regMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_QUANT_PRI1 0x046e
#define regMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_QUANT_PRI2 0x046f
#define regMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_QUANT_PRI3 0x0470
#define regMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_QUANT_PRI1 0x0471
#define regMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_QUANT_PRI2 0x0472
#define regMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_QUANT_PRI3 0x0473
#define regMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA1_ADDRNORM_BASE_ADDR0 0x0474
#define regMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 0
#define regMMEA1_ADDRNORM_LIMIT_ADDR0 0x0475
#define regMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
#define regMMEA1_ADDRNORM_BASE_ADDR1 0x0476
#define regMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 0
#define regMMEA1_ADDRNORM_LIMIT_ADDR1 0x0477
#define regMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
#define regMMEA1_ADDRNORM_OFFSET_ADDR1 0x0478
#define regMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
#define regMMEA1_ADDRNORM_BASE_ADDR2 0x0479
#define regMMEA1_ADDRNORM_BASE_ADDR2_BASE_IDX 0
#define regMMEA1_ADDRNORM_LIMIT_ADDR2 0x047a
#define regMMEA1_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
#define regMMEA1_ADDRNORM_BASE_ADDR3 0x047b
#define regMMEA1_ADDRNORM_BASE_ADDR3_BASE_IDX 0
#define regMMEA1_ADDRNORM_LIMIT_ADDR3 0x047c
#define regMMEA1_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
#define regMMEA1_ADDRNORM_OFFSET_ADDR3 0x047d
#define regMMEA1_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
#define regMMEA1_ADDRNORM_MEGABASE_ADDR0 0x047e
#define regMMEA1_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR0 0x047f
#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
#define regMMEA1_ADDRNORM_MEGABASE_ADDR1 0x0480
#define regMMEA1_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR1 0x0481
#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
#define regMMEA1_ADDRNORMDRAM_HOLE_CNTL 0x0483
#define regMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
#define regMMEA1_ADDRNORMGMI_HOLE_CNTL 0x0484
#define regMMEA1_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
#define regMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0485
#define regMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0486
#define regMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA1_ADDRDEC_BANK_CFG 0x0487
#define regMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 0
#define regMMEA1_ADDRDEC_MISC_CFG 0x0488
#define regMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 0
#define regMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x0493
#define regMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA1_ADDRDECGMI_HARVEST_ENABLE 0x049e
#define regMMEA1_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x049f
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x04a0
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x04a1
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x04a2
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x04a3
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x04a4
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x04a5
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x04a6
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x04a7
#define regMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x04a8
#define regMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x04a9
#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x04aa
#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x04ab
#define regMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x04ac
#define regMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x04ad
#define regMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x04ae
#define regMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS01 0x04af
#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS23 0x04b0
#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x04b1
#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x04b2
#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x04b3
#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x04b4
#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_RM_SEL_CS01 0x04b5
#define regMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_RM_SEL_CS23 0x04b6
#define regMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x04b7
#define regMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x04b8
#define regMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x04b9
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x04ba
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x04bb
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x04bc
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x04bd
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x04be
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x04bf
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x04c0
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x04c1
#define regMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x04c2
#define regMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x04c3
#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x04c4
#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x04c5
#define regMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x04c6
#define regMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x04c7
#define regMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x04c8
#define regMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS01 0x04c9
#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS23 0x04ca
#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x04cb
#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x04cc
#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x04cd
#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x04ce
#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_RM_SEL_CS01 0x04cf
#define regMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_RM_SEL_CS23 0x04d0
#define regMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x04d1
#define regMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x04d2
#define regMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS0 0x04d3
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS1 0x04d4
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS2 0x04d5
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS3 0x04d6
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 0x04d7
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 0x04d8
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 0x04d9
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 0x04da
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_MASK_CS01 0x04db
#define regMMEA1_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_MASK_CS23 0x04dc
#define regMMEA1_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 0x04dd
#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 0x04de
#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_CFG_CS01 0x04df
#define regMMEA1_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_CFG_CS23 0x04e0
#define regMMEA1_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_SEL_CS01 0x04e1
#define regMMEA1_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_SEL_CS23 0x04e2
#define regMMEA1_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS01 0x04e3
#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS23 0x04e4
#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS01 0x04e5
#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS23 0x04e6
#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS01 0x04e7
#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS23 0x04e8
#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_RM_SEL_CS01 0x04e9
#define regMMEA1_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_RM_SEL_CS23 0x04ea
#define regMMEA1_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_RM_SEL_SECCS01 0x04eb
#define regMMEA1_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_RM_SEL_SECCS23 0x04ec
#define regMMEA1_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA1_ADDRNORMDRAM_GLOBAL_CNTL 0x04ed
#define regMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA1_ADDRNORMGMI_GLOBAL_CNTL 0x04ee
#define regMMEA1_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR0 0x0511
#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR1 0x0512
#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
#define regMMEA1_ADDRNORMDRAM_MASKING 0x0513
#define regMMEA1_ADDRNORMDRAM_MASKING_BASE_IDX 0
#define regMMEA1_ADDRNORMGMI_MASKING 0x0514
#define regMMEA1_ADDRNORMGMI_MASKING_BASE_IDX 0
#define regMMEA1_IO_RD_CLI2GRP_MAP0 0x0515
#define regMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA1_IO_RD_CLI2GRP_MAP1 0x0516
#define regMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA1_IO_WR_CLI2GRP_MAP0 0x0517
#define regMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA1_IO_WR_CLI2GRP_MAP1 0x0518
#define regMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA1_IO_RD_COMBINE_FLUSH 0x0519
#define regMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA1_IO_WR_COMBINE_FLUSH 0x051a
#define regMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA1_IO_GROUP_BURST 0x051b
#define regMMEA1_IO_GROUP_BURST_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_AGE 0x051c
#define regMMEA1_IO_RD_PRI_AGE_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_AGE 0x051d
#define regMMEA1_IO_WR_PRI_AGE_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_QUEUING 0x051e
#define regMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_QUEUING 0x051f
#define regMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_FIXED 0x0520
#define regMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_FIXED 0x0521
#define regMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_URGENCY 0x0522
#define regMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_URGENCY 0x0523
#define regMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_URGENCY_MASKING 0x0524
#define regMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_URGENCY_MASKING 0x0525
#define regMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_QUANT_PRI1 0x0526
#define regMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_QUANT_PRI2 0x0527
#define regMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_QUANT_PRI3 0x0528
#define regMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_QUANT_PRI1 0x0529
#define regMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_QUANT_PRI2 0x052a
#define regMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_QUANT_PRI3 0x052b
#define regMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA1_SDP_ARB_DRAM 0x052c
#define regMMEA1_SDP_ARB_DRAM_BASE_IDX 0
#define regMMEA1_SDP_ARB_GMI 0x052d
#define regMMEA1_SDP_ARB_GMI_BASE_IDX 0
#define regMMEA1_SDP_ARB_FINAL 0x052e
#define regMMEA1_SDP_ARB_FINAL_BASE_IDX 0
#define regMMEA1_SDP_DRAM_PRIORITY 0x052f
#define regMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0
#define regMMEA1_SDP_GMI_PRIORITY 0x0530
#define regMMEA1_SDP_GMI_PRIORITY_BASE_IDX 0
#define regMMEA1_SDP_IO_PRIORITY 0x0531
#define regMMEA1_SDP_IO_PRIORITY_BASE_IDX 0
#define regMMEA1_SDP_CREDITS 0x0532
#define regMMEA1_SDP_CREDITS_BASE_IDX 0
#define regMMEA1_SDP_TAG_RESERVE0 0x0533
#define regMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0
#define regMMEA1_SDP_TAG_RESERVE1 0x0534
#define regMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0
#define regMMEA1_SDP_VCC_RESERVE0 0x0535
#define regMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0
#define regMMEA1_SDP_VCC_RESERVE1 0x0536
#define regMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0
#define regMMEA1_SDP_VCD_RESERVE0 0x0537
#define regMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0
#define regMMEA1_SDP_VCD_RESERVE1 0x0538
#define regMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0
#define regMMEA1_SDP_REQ_CNTL 0x0539
#define regMMEA1_SDP_REQ_CNTL_BASE_IDX 0
#define regMMEA1_MISC 0x053a
#define regMMEA1_MISC_BASE_IDX 0
#define regMMEA1_LATENCY_SAMPLING 0x053b
#define regMMEA1_LATENCY_SAMPLING_BASE_IDX 0
#define regMMEA1_PERFCOUNTER_LO 0x053c
#define regMMEA1_PERFCOUNTER_LO_BASE_IDX 0
#define regMMEA1_PERFCOUNTER_HI 0x053d
#define regMMEA1_PERFCOUNTER_HI_BASE_IDX 0
#define regMMEA1_PERFCOUNTER0_CFG 0x053e
#define regMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0
#define regMMEA1_PERFCOUNTER1_CFG 0x053f
#define regMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0
#define regMMEA1_PERFCOUNTER_RSLT_CNTL 0x0540
#define regMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regMMEA1_EDC_CNT 0x0546
#define regMMEA1_EDC_CNT_BASE_IDX 0
#define regMMEA1_EDC_CNT2 0x0547
#define regMMEA1_EDC_CNT2_BASE_IDX 0
#define regMMEA1_DSM_CNTL 0x0548
#define regMMEA1_DSM_CNTL_BASE_IDX 0
#define regMMEA1_DSM_CNTLA 0x0549
#define regMMEA1_DSM_CNTLA_BASE_IDX 0
#define regMMEA1_DSM_CNTLB 0x054a
#define regMMEA1_DSM_CNTLB_BASE_IDX 0
#define regMMEA1_DSM_CNTL2 0x054b
#define regMMEA1_DSM_CNTL2_BASE_IDX 0
#define regMMEA1_DSM_CNTL2A 0x054c
#define regMMEA1_DSM_CNTL2A_BASE_IDX 0
#define regMMEA1_DSM_CNTL2B 0x054d
#define regMMEA1_DSM_CNTL2B_BASE_IDX 0
#define regMMEA1_CGTT_CLK_CTRL 0x054f
#define regMMEA1_CGTT_CLK_CTRL_BASE_IDX 0
#define regMMEA1_EDC_MODE 0x0550
#define regMMEA1_EDC_MODE_BASE_IDX 0
#define regMMEA1_ERR_STATUS 0x0551
#define regMMEA1_ERR_STATUS_BASE_IDX 0
#define regMMEA1_MISC2 0x0552
#define regMMEA1_MISC2_BASE_IDX 0
#define regMMEA1_ADDRDEC_SELECT 0x0553
#define regMMEA1_ADDRDEC_SELECT_BASE_IDX 0
#define regMMEA1_EDC_CNT3 0x0554
#define regMMEA1_EDC_CNT3_BASE_IDX 0
#define regMMEA1_MISC_AON 0x0555
#define regMMEA1_MISC_AON_BASE_IDX 0
// addressBlock: mmhub_ea_mmeadec2
// base address: 0x69600
#define regMMEA2_DRAM_RD_CLI2GRP_MAP0 0x0580
#define regMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA2_DRAM_RD_CLI2GRP_MAP1 0x0581
#define regMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA2_DRAM_WR_CLI2GRP_MAP0 0x0582
#define regMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA2_DRAM_WR_CLI2GRP_MAP1 0x0583
#define regMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA2_DRAM_RD_GRP2VC_MAP 0x0584
#define regMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA2_DRAM_WR_GRP2VC_MAP 0x0585
#define regMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA2_DRAM_RD_LAZY 0x0586
#define regMMEA2_DRAM_RD_LAZY_BASE_IDX 0
#define regMMEA2_DRAM_WR_LAZY 0x0587
#define regMMEA2_DRAM_WR_LAZY_BASE_IDX 0
#define regMMEA2_DRAM_RD_CAM_CNTL 0x0588
#define regMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA2_DRAM_WR_CAM_CNTL 0x0589
#define regMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA2_DRAM_PAGE_BURST 0x058a
#define regMMEA2_DRAM_PAGE_BURST_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_AGE 0x058b
#define regMMEA2_DRAM_RD_PRI_AGE_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_AGE 0x058c
#define regMMEA2_DRAM_WR_PRI_AGE_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_QUEUING 0x058d
#define regMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_QUEUING 0x058e
#define regMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_FIXED 0x058f
#define regMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_FIXED 0x0590
#define regMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_URGENCY 0x0591
#define regMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_URGENCY 0x0592
#define regMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_QUANT_PRI1 0x0593
#define regMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_QUANT_PRI2 0x0594
#define regMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_QUANT_PRI3 0x0595
#define regMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_QUANT_PRI1 0x0596
#define regMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_QUANT_PRI2 0x0597
#define regMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_QUANT_PRI3 0x0598
#define regMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA2_GMI_RD_CLI2GRP_MAP0 0x0599
#define regMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA2_GMI_RD_CLI2GRP_MAP1 0x059a
#define regMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA2_GMI_WR_CLI2GRP_MAP0 0x059b
#define regMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA2_GMI_WR_CLI2GRP_MAP1 0x059c
#define regMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA2_GMI_RD_GRP2VC_MAP 0x059d
#define regMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA2_GMI_WR_GRP2VC_MAP 0x059e
#define regMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA2_GMI_RD_LAZY 0x059f
#define regMMEA2_GMI_RD_LAZY_BASE_IDX 0
#define regMMEA2_GMI_WR_LAZY 0x05a0
#define regMMEA2_GMI_WR_LAZY_BASE_IDX 0
#define regMMEA2_GMI_RD_CAM_CNTL 0x05a1
#define regMMEA2_GMI_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA2_GMI_WR_CAM_CNTL 0x05a2
#define regMMEA2_GMI_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA2_GMI_PAGE_BURST 0x05a3
#define regMMEA2_GMI_PAGE_BURST_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_AGE 0x05a4
#define regMMEA2_GMI_RD_PRI_AGE_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_AGE 0x05a5
#define regMMEA2_GMI_WR_PRI_AGE_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_QUEUING 0x05a6
#define regMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_QUEUING 0x05a7
#define regMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_FIXED 0x05a8
#define regMMEA2_GMI_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_FIXED 0x05a9
#define regMMEA2_GMI_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_URGENCY 0x05aa
#define regMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_URGENCY 0x05ab
#define regMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_URGENCY_MASKING 0x05ac
#define regMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_URGENCY_MASKING 0x05ad
#define regMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_QUANT_PRI1 0x05ae
#define regMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_QUANT_PRI2 0x05af
#define regMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_QUANT_PRI3 0x05b0
#define regMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_QUANT_PRI1 0x05b1
#define regMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_QUANT_PRI2 0x05b2
#define regMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_QUANT_PRI3 0x05b3
#define regMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA2_ADDRNORM_BASE_ADDR0 0x05b4
#define regMMEA2_ADDRNORM_BASE_ADDR0_BASE_IDX 0
#define regMMEA2_ADDRNORM_LIMIT_ADDR0 0x05b5
#define regMMEA2_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
#define regMMEA2_ADDRNORM_BASE_ADDR1 0x05b6
#define regMMEA2_ADDRNORM_BASE_ADDR1_BASE_IDX 0
#define regMMEA2_ADDRNORM_LIMIT_ADDR1