blob: c1185f36c0808282e365e5c355c0b55cdfe9f768 [file] [log] [blame]
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _mmhub_1_7_SH_MASK_HEADER
#define _mmhub_1_7_SH_MASK_HEADER
// addressBlock: mmhub_dagb_dagbdec0
//DAGB0_RDCLI0
#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI1
#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI2
#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI3
#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI4
#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI5
#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI6
#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI7
#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI8
#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI9
#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI10
#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI11
#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI12
#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI13
#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI14
#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L
//DAGB0_RDCLI15
#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0
#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4
#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8
#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd
#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16
#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a
#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L
#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L
#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L
#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L
#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L
//DAGB0_RD_CNTL
#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0
#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11
#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
#define DAGB0_RD_CNTL__FIX_JUMP__SHIFT 0x1a
#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
#define DAGB0_RD_CNTL__FIX_JUMP_MASK 0x04000000L
//DAGB0_RD_GMI_CNTL
#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6
#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
//DAGB0_RD_ADDR_DAGB
#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
//DAGB0_RD_OUTPUT_DAGB_MAX_BURST
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
//DAGB0_RD_CGTT_CLK_CTRL
#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB0_ATCVM_RD_CGTT_CLK_CTRL
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB0_RD_ADDR_DAGB_MAX_BURST0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
//DAGB0_RD_ADDR_DAGB_MAX_BURST1
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
//DAGB0_RD_VC0_CNTL
#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC1_CNTL
#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC2_CNTL
#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC3_CNTL
#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC4_CNTL
#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC5_CNTL
#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC6_CNTL
#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_VC7_CNTL
#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_RD_CNTL_MISC
#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
#define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
#define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
//DAGB0_RD_TLB_CREDIT
#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0
#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5
#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa
#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf
#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14
#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19
#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
//DAGB0_RD_RDRET_CREDIT_CNTL
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e
#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L
#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L
#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L
//DAGB0_RD_RDRET_CREDIT_CNTL2
#define DAGB0_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0
#define DAGB0_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6
#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc
#define DAGB0_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL
#define DAGB0_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L
#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L
//DAGB0_RDCLI_ASK_PENDING
#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_RDCLI_GO_PENDING
#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_RDCLI_GBLSEND_PENDING
#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_RDCLI_TLB_PENDING
#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_RDCLI_OARB_PENDING
#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_RDCLI_OSD_PENDING
#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI0
#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI1
#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI2
#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI3
#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI4
#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI5
#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI6
#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI7
#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI8
#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI9
#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI10
#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI11
#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI12
#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI13
#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI14
#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L
//DAGB0_WRCLI15
#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0
#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4
#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8
#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd
#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16
#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a
#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L
#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L
#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L
#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L
#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L
#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L
//DAGB0_WR_CNTL
#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0
#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11
#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
#define DAGB0_WR_CNTL__FIX_JUMP__SHIFT 0x1a
#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
#define DAGB0_WR_CNTL__FIX_JUMP_MASK 0x04000000L
//DAGB0_WR_GMI_CNTL
#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6
#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
//DAGB0_WR_ADDR_DAGB
#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
//DAGB0_WR_OUTPUT_DAGB_MAX_BURST
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
//DAGB0_WR_CGTT_CLK_CTRL
#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB0_ATCVM_WR_CGTT_CLK_CTRL
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB0_WR_ADDR_DAGB_MAX_BURST0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
//DAGB0_WR_ADDR_DAGB_MAX_BURST1
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
//DAGB0_WR_DATA_DAGB
#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
//DAGB0_WR_DATA_DAGB_MAX_BURST0
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
//DAGB0_WR_DATA_DAGB_MAX_BURST1
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
//DAGB0_WR_VC0_CNTL
#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC1_CNTL
#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC2_CNTL
#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC3_CNTL
#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC4_CNTL
#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC5_CNTL
#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC6_CNTL
#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_VC7_CNTL
#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB0_WR_CNTL_MISC
#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
#define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
#define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
//DAGB0_WR_TLB_CREDIT
#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0
#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5
#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa
#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf
#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14
#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19
#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
//DAGB0_WR_DATA_CREDIT
#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
//DAGB0_WR_MISC_CREDIT
#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
//DAGB0_WR_OSD_CREDIT_CNTL1
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc
#define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10
#define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14
#define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L
#define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L
#define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L
#define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L
#define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L
//DAGB0_WR_OSD_CREDIT_CNTL2
#define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0
#define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4
#define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL
#define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L
//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L
//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_ASK_PENDING
#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_GO_PENDING
#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_GBLSEND_PENDING
#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_TLB_PENDING
#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_OARB_PENDING
#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_OSD_PENDING
#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_DBUS_ASK_PENDING
#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_WRCLI_DBUS_GO_PENDING
#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB0_DAGB_DLY
#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0
#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8
#define DAGB0_DAGB_DLY__POS__SHIFT 0x10
#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL
#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L
#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L
//DAGB0_CNTL_MISC
#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
//DAGB0_CNTL_MISC2
#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb
#define DAGB0_CNTL_MISC2__HDP_CID__SHIFT 0xc
#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11
#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L
#define DAGB0_CNTL_MISC2__HDP_CID_MASK 0x0001F000L
#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L
//DAGB0_FATAL_ERROR_CNTL
#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0
#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL
//DAGB0_FATAL_ERROR_CLEAR
#define DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0
#define DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L
//DAGB0_FATAL_ERROR_STATUS0
#define DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0
#define DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT 0x1
#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6
#define DAGB0_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L
#define DAGB0_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL
#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L
//DAGB0_FATAL_ERROR_STATUS1
#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0
#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL
//DAGB0_FATAL_ERROR_STATUS2
#define DAGB0_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0
#define DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10
#define DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT 0x14
#define DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15
#define DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT 0x16
#define DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17
#define DAGB0_FATAL_ERROR_STATUS2__FED__SHIFT 0x19
#define DAGB0_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL
#define DAGB0_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L
#define DAGB0_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L
#define DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L
#define DAGB0_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L
#define DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L
#define DAGB0_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L
//DAGB0_FATAL_ERROR_STATUS3
#define DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT 0x6
#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10
#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11
#define DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12
#define DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13
#define DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14
#define DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT 0x16
#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17
#define DAGB0_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18
#define DAGB0_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L
#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L
#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L
#define DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L
#define DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L
#define DAGB0_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L
#define DAGB0_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L
#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L
#define DAGB0_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L
//DAGB0_FIFO_EMPTY
#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0
#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
//DAGB0_FIFO_FULL
#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0
#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL
//DAGB0_WR_CREDITS_FULL
#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0
#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL
//DAGB0_RD_CREDITS_FULL
#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0
#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
//DAGB0_PERFCOUNTER_LO
#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
//DAGB0_PERFCOUNTER_HI
#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
//DAGB0_PERFCOUNTER0_CFG
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
//DAGB0_PERFCOUNTER1_CFG
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
//DAGB0_PERFCOUNTER2_CFG
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
//DAGB0_PERFCOUNTER_RSLT_CNTL
#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
//DAGB0_L1TLB_REG_RW
#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0
#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1
#define DAGB0_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2
#define DAGB0_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4
#define DAGB0_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5
#define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x6
#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L
#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L
#define DAGB0_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L
#define DAGB0_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L
#define DAGB0_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L
#define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L
//DAGB0_RESERVE1
#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE2
#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE3
#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
//DAGB0_RESERVE4
#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0
#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
// addressBlock: mmhub_dagb_dagbdec1
//DAGB1_RDCLI0
#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI1
#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI2
#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI3
#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI4
#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI5
#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI6
#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI7
#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI8
#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI9
#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI10
#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI11
#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI12
#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI13
#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI14
#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L
//DAGB1_RDCLI15
#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0
#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4
#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8
#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd
#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16
#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a
#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L
#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L
#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L
#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L
#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L
//DAGB1_RD_CNTL
#define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0
#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
#define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11
#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
#define DAGB1_RD_CNTL__FIX_JUMP__SHIFT 0x1a
#define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
#define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
#define DAGB1_RD_CNTL__FIX_JUMP_MASK 0x04000000L
//DAGB1_RD_GMI_CNTL
#define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
#define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6
#define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
#define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
#define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
#define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
#define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
#define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
//DAGB1_RD_ADDR_DAGB
#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
#define DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd
#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
#define DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L
//DAGB1_RD_OUTPUT_DAGB_MAX_BURST
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
//DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
//DAGB1_RD_CGTT_CLK_CTRL
#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB1_L1TLB_RD_CGTT_CLK_CTRL
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB1_ATCVM_RD_CGTT_CLK_CTRL
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
//DAGB1_RD_ADDR_DAGB_MAX_BURST0
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
//DAGB1_RD_ADDR_DAGB_MAX_BURST1
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
//DAGB1_RD_VC0_CNTL
#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB1_RD_VC1_CNTL
#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB1_RD_VC2_CNTL
#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB1_RD_VC3_CNTL
#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB1_RD_VC4_CNTL
#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB1_RD_VC5_CNTL
#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB1_RD_VC6_CNTL
#define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB1_RD_VC7_CNTL
#define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
#define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
#define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
#define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
#define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
#define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
#define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
#define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
#define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
#define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
//DAGB1_RD_CNTL_MISC
#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
#define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
#define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a
#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
#define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
#define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L
//DAGB1_RD_TLB_CREDIT
#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0
#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5
#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa
#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf
#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14
#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19
#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
//DAGB1_RD_RDRET_CREDIT_CNTL
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e
#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L
#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L
#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L
//DAGB1_RD_RDRET_CREDIT_CNTL2
#define DAGB1_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0
#define DAGB1_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6
#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc
#define DAGB1_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL
#define DAGB1_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L
#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L
//DAGB1_RDCLI_ASK_PENDING
#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB1_RDCLI_GO_PENDING
#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB1_RDCLI_GBLSEND_PENDING
#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB1_RDCLI_TLB_PENDING
#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB1_RDCLI_OARB_PENDING
#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB1_RDCLI_OSD_PENDING
#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
//DAGB1_WRCLI0
#define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0
#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
#define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4
#define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8
#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
#define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd
#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
#define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16
#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
#define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a
#define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L
#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
#define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L
#define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L
#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
#define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L
#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
#define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L
#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
#define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L
//DAGB1_WRCLI1