| /* |
| * Copyright (C) 2020 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included |
| * in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef _mmhub_2_3_0_OFFSET_HEADER |
| #define _mmhub_2_3_0_OFFSET_HEADER |
| |
| |
| |
| // addressBlock: mmhub_dagbdec |
| // base address: 0x68000 |
| #define mmDAGB0_RDCLI0 0x0000 |
| #define mmDAGB0_RDCLI0_BASE_IDX 1 |
| #define mmDAGB0_RDCLI1 0x0001 |
| #define mmDAGB0_RDCLI1_BASE_IDX 1 |
| #define mmDAGB0_RDCLI2 0x0002 |
| #define mmDAGB0_RDCLI2_BASE_IDX 1 |
| #define mmDAGB0_RDCLI3 0x0003 |
| #define mmDAGB0_RDCLI3_BASE_IDX 1 |
| #define mmDAGB0_RDCLI4 0x0004 |
| #define mmDAGB0_RDCLI4_BASE_IDX 1 |
| #define mmDAGB0_RDCLI5 0x0005 |
| #define mmDAGB0_RDCLI5_BASE_IDX 1 |
| #define mmDAGB0_RDCLI6 0x0006 |
| #define mmDAGB0_RDCLI6_BASE_IDX 1 |
| #define mmDAGB0_RDCLI7 0x0007 |
| #define mmDAGB0_RDCLI7_BASE_IDX 1 |
| #define mmDAGB0_RDCLI8 0x0008 |
| #define mmDAGB0_RDCLI8_BASE_IDX 1 |
| #define mmDAGB0_RDCLI9 0x0009 |
| #define mmDAGB0_RDCLI9_BASE_IDX 1 |
| #define mmDAGB0_RDCLI10 0x000a |
| #define mmDAGB0_RDCLI10_BASE_IDX 1 |
| #define mmDAGB0_RDCLI11 0x000b |
| #define mmDAGB0_RDCLI11_BASE_IDX 1 |
| #define mmDAGB0_RDCLI12 0x000c |
| #define mmDAGB0_RDCLI12_BASE_IDX 1 |
| #define mmDAGB0_RDCLI13 0x000d |
| #define mmDAGB0_RDCLI13_BASE_IDX 1 |
| #define mmDAGB0_RDCLI14 0x000e |
| #define mmDAGB0_RDCLI14_BASE_IDX 1 |
| #define mmDAGB0_RDCLI15 0x000f |
| #define mmDAGB0_RDCLI15_BASE_IDX 1 |
| #define mmDAGB0_RDCLI16 0x0010 |
| #define mmDAGB0_RDCLI16_BASE_IDX 1 |
| #define mmDAGB0_RDCLI17 0x0011 |
| #define mmDAGB0_RDCLI17_BASE_IDX 1 |
| #define mmDAGB0_RDCLI18 0x0012 |
| #define mmDAGB0_RDCLI18_BASE_IDX 1 |
| #define mmDAGB0_RDCLI19 0x0013 |
| #define mmDAGB0_RDCLI19_BASE_IDX 1 |
| #define mmDAGB0_RDCLI20 0x0014 |
| #define mmDAGB0_RDCLI20_BASE_IDX 1 |
| #define mmDAGB0_RDCLI21 0x0015 |
| #define mmDAGB0_RDCLI21_BASE_IDX 1 |
| #define mmDAGB0_RDCLI22 0x0016 |
| #define mmDAGB0_RDCLI22_BASE_IDX 1 |
| #define mmDAGB0_RDCLI23 0x0017 |
| #define mmDAGB0_RDCLI23_BASE_IDX 1 |
| #define mmDAGB0_RDCLI24 0x0018 |
| #define mmDAGB0_RDCLI24_BASE_IDX 1 |
| #define mmDAGB0_RDCLI25 0x0019 |
| #define mmDAGB0_RDCLI25_BASE_IDX 1 |
| #define mmDAGB0_RDCLI26 0x001a |
| #define mmDAGB0_RDCLI26_BASE_IDX 1 |
| #define mmDAGB0_RDCLI27 0x001b |
| #define mmDAGB0_RDCLI27_BASE_IDX 1 |
| #define mmDAGB0_RDCLI28 0x001c |
| #define mmDAGB0_RDCLI28_BASE_IDX 1 |
| #define mmDAGB0_RDCLI29 0x001d |
| #define mmDAGB0_RDCLI29_BASE_IDX 1 |
| #define mmDAGB0_RDCLI30 0x001e |
| #define mmDAGB0_RDCLI30_BASE_IDX 1 |
| #define mmDAGB0_RD_CNTL 0x001f |
| #define mmDAGB0_RD_CNTL_BASE_IDX 1 |
| #define mmDAGB0_RD_GMI_CNTL 0x0020 |
| #define mmDAGB0_RD_GMI_CNTL_BASE_IDX 1 |
| #define mmDAGB0_RD_ADDR_DAGB 0x0021 |
| #define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 1 |
| #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0022 |
| #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
| #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0023 |
| #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
| #define mmDAGB0_RD_CGTT_CLK_CTRL 0x0024 |
| #define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
| #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0025 |
| #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
| #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0026 |
| #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 |
| #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0027 |
| #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
| #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0028 |
| #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
| #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0029 |
| #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
| #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x002a |
| #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
| #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x002b |
| #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 |
| #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x002c |
| #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 |
| #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3 0x002d |
| #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3_BASE_IDX 1 |
| #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3 0x002e |
| #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1 |
| #define mmDAGB0_RD_VC0_CNTL 0x002f |
| #define mmDAGB0_RD_VC0_CNTL_BASE_IDX 1 |
| #define mmDAGB0_RD_VC1_CNTL 0x0030 |
| #define mmDAGB0_RD_VC1_CNTL_BASE_IDX 1 |
| #define mmDAGB0_RD_VC2_CNTL 0x0031 |
| #define mmDAGB0_RD_VC2_CNTL_BASE_IDX 1 |
| #define mmDAGB0_RD_VC3_CNTL 0x0032 |
| #define mmDAGB0_RD_VC3_CNTL_BASE_IDX 1 |
| #define mmDAGB0_RD_VC4_CNTL 0x0033 |
| #define mmDAGB0_RD_VC4_CNTL_BASE_IDX 1 |
| #define mmDAGB0_RD_VC5_CNTL 0x0034 |
| #define mmDAGB0_RD_VC5_CNTL_BASE_IDX 1 |
| #define mmDAGB0_RD_VC6_CNTL 0x0035 |
| #define mmDAGB0_RD_VC6_CNTL_BASE_IDX 1 |
| #define mmDAGB0_RD_VC7_CNTL 0x0036 |
| #define mmDAGB0_RD_VC7_CNTL_BASE_IDX 1 |
| #define mmDAGB0_RD_CNTL_MISC 0x0037 |
| #define mmDAGB0_RD_CNTL_MISC_BASE_IDX 1 |
| #define mmDAGB0_RD_TLB_CREDIT 0x0038 |
| #define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 1 |
| #define mmDAGB0_RD_RDRET_CREDIT_CNTL 0x0039 |
| #define mmDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX 1 |
| #define mmDAGB0_RD_RDRET_CREDIT_CNTL2 0x003a |
| #define mmDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX 1 |
| #define mmDAGB0_RDCLI_ASK_PENDING 0x003b |
| #define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1 |
| #define mmDAGB0_RDCLI_GO_PENDING 0x003c |
| #define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 1 |
| #define mmDAGB0_RDCLI_GBLSEND_PENDING 0x003d |
| #define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1 |
| #define mmDAGB0_RDCLI_TLB_PENDING 0x003e |
| #define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1 |
| #define mmDAGB0_RDCLI_OARB_PENDING 0x003f |
| #define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1 |
| #define mmDAGB0_RDCLI_OSD_PENDING 0x0040 |
| #define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1 |
| #define mmDAGB0_WRCLI0 0x0041 |
| #define mmDAGB0_WRCLI0_BASE_IDX 1 |
| #define mmDAGB0_WRCLI1 0x0042 |
| #define mmDAGB0_WRCLI1_BASE_IDX 1 |
| #define mmDAGB0_WRCLI2 0x0043 |
| #define mmDAGB0_WRCLI2_BASE_IDX 1 |
| #define mmDAGB0_WRCLI3 0x0044 |
| #define mmDAGB0_WRCLI3_BASE_IDX 1 |
| #define mmDAGB0_WRCLI4 0x0045 |
| #define mmDAGB0_WRCLI4_BASE_IDX 1 |
| #define mmDAGB0_WRCLI5 0x0046 |
| #define mmDAGB0_WRCLI5_BASE_IDX 1 |
| #define mmDAGB0_WRCLI6 0x0047 |
| #define mmDAGB0_WRCLI6_BASE_IDX 1 |
| #define mmDAGB0_WRCLI7 0x0048 |
| #define mmDAGB0_WRCLI7_BASE_IDX 1 |
| #define mmDAGB0_WRCLI8 0x0049 |
| #define mmDAGB0_WRCLI8_BASE_IDX 1 |
| #define mmDAGB0_WRCLI9 0x004a |
| #define mmDAGB0_WRCLI9_BASE_IDX 1 |
| #define mmDAGB0_WRCLI10 0x004b |
| #define mmDAGB0_WRCLI10_BASE_IDX 1 |
| #define mmDAGB0_WRCLI11 0x004c |
| #define mmDAGB0_WRCLI11_BASE_IDX 1 |
| #define mmDAGB0_WRCLI12 0x004d |
| #define mmDAGB0_WRCLI12_BASE_IDX 1 |
| #define mmDAGB0_WRCLI13 0x004e |
| #define mmDAGB0_WRCLI13_BASE_IDX 1 |
| #define mmDAGB0_WRCLI14 0x004f |
| #define mmDAGB0_WRCLI14_BASE_IDX 1 |
| #define mmDAGB0_WRCLI15 0x0050 |
| #define mmDAGB0_WRCLI15_BASE_IDX 1 |
| #define mmDAGB0_WRCLI16 0x0051 |
| #define mmDAGB0_WRCLI16_BASE_IDX 1 |
| #define mmDAGB0_WRCLI17 0x0052 |
| #define mmDAGB0_WRCLI17_BASE_IDX 1 |
| #define mmDAGB0_WRCLI18 0x0053 |
| #define mmDAGB0_WRCLI18_BASE_IDX 1 |
| #define mmDAGB0_WRCLI19 0x0054 |
| #define mmDAGB0_WRCLI19_BASE_IDX 1 |
| #define mmDAGB0_WRCLI20 0x0055 |
| #define mmDAGB0_WRCLI20_BASE_IDX 1 |
| #define mmDAGB0_WRCLI21 0x0056 |
| #define mmDAGB0_WRCLI21_BASE_IDX 1 |
| #define mmDAGB0_WRCLI22 0x0057 |
| #define mmDAGB0_WRCLI22_BASE_IDX 1 |
| #define mmDAGB0_WRCLI23 0x0058 |
| #define mmDAGB0_WRCLI23_BASE_IDX 1 |
| #define mmDAGB0_WRCLI24 0x0059 |
| #define mmDAGB0_WRCLI24_BASE_IDX 1 |
| #define mmDAGB0_WRCLI25 0x005a |
| #define mmDAGB0_WRCLI25_BASE_IDX 1 |
| #define mmDAGB0_WRCLI26 0x005b |
| #define mmDAGB0_WRCLI26_BASE_IDX 1 |
| #define mmDAGB0_WRCLI27 0x005c |
| #define mmDAGB0_WRCLI27_BASE_IDX 1 |
| #define mmDAGB0_WRCLI28 0x005d |
| #define mmDAGB0_WRCLI28_BASE_IDX 1 |
| #define mmDAGB0_WRCLI29 0x005e |
| #define mmDAGB0_WRCLI29_BASE_IDX 1 |
| #define mmDAGB0_WRCLI30 0x005f |
| #define mmDAGB0_WRCLI30_BASE_IDX 1 |
| #define mmDAGB0_WR_CNTL 0x0060 |
| #define mmDAGB0_WR_CNTL_BASE_IDX 1 |
| #define mmDAGB0_WR_GMI_CNTL 0x0061 |
| #define mmDAGB0_WR_GMI_CNTL_BASE_IDX 1 |
| #define mmDAGB0_WR_ADDR_DAGB 0x0062 |
| #define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 1 |
| #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0063 |
| #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 |
| #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0064 |
| #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 |
| #define mmDAGB0_WR_CGTT_CLK_CTRL 0x0065 |
| #define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
| #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0066 |
| #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
| #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0067 |
| #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 |
| #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0068 |
| #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 |
| #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0069 |
| #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 |
| #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x006a |
| #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 |
| #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x006b |
| #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 |
| #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x006c |
| #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 |
| #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x006d |
| #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 |
| #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3 0x006e |
| #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3_BASE_IDX 1 |
| #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3 0x006f |
| #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1 |
| #define mmDAGB0_WR_DATA_DAGB 0x0070 |
| #define mmDAGB0_WR_DATA_DAGB_BASE_IDX 1 |
| #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0071 |
| #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 |
| #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x0072 |
| #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 |
| #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0073 |
| #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 |
| #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0074 |
| #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 |
| #define mmDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0075 |
| #define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 1 |
| #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0076 |
| #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 1 |
| #define mmDAGB0_WR_DATA_DAGB_MAX_BURST3 0x0077 |
| #define mmDAGB0_WR_DATA_DAGB_MAX_BURST3_BASE_IDX 1 |
| #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3 0x0078 |
| #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3_BASE_IDX 1 |
| #define mmDAGB0_WR_VC0_CNTL 0x0079 |
| #define mmDAGB0_WR_VC0_CNTL_BASE_IDX 1 |
| #define mmDAGB0_WR_VC1_CNTL 0x007a |
| #define mmDAGB0_WR_VC1_CNTL_BASE_IDX 1 |
| #define mmDAGB0_WR_VC2_CNTL 0x007b |
| #define mmDAGB0_WR_VC2_CNTL_BASE_IDX 1 |
| #define mmDAGB0_WR_VC3_CNTL 0x007c |
| #define mmDAGB0_WR_VC3_CNTL_BASE_IDX 1 |
| #define mmDAGB0_WR_VC4_CNTL 0x007d |
| #define mmDAGB0_WR_VC4_CNTL_BASE_IDX 1 |
| #define mmDAGB0_WR_VC5_CNTL 0x007e |
| #define mmDAGB0_WR_VC5_CNTL_BASE_IDX 1 |
| #define mmDAGB0_WR_VC6_CNTL 0x007f |
| #define mmDAGB0_WR_VC6_CNTL_BASE_IDX 1 |
| #define mmDAGB0_WR_VC7_CNTL 0x0080 |
| #define mmDAGB0_WR_VC7_CNTL_BASE_IDX 1 |
| #define mmDAGB0_WR_CNTL_MISC 0x0081 |
| #define mmDAGB0_WR_CNTL_MISC_BASE_IDX 1 |
| #define mmDAGB0_WR_TLB_CREDIT 0x0082 |
| #define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 1 |
| #define mmDAGB0_WR_DATA_CREDIT 0x0083 |
| #define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 1 |
| #define mmDAGB0_WR_MISC_CREDIT 0x0084 |
| #define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 1 |
| #define mmDAGB0_WR_OSD_CREDIT_CNTL1 0x0085 |
| #define mmDAGB0_WR_OSD_CREDIT_CNTL1_BASE_IDX 1 |
| #define mmDAGB0_WR_OSD_CREDIT_CNTL2 0x0086 |
| #define mmDAGB0_WR_OSD_CREDIT_CNTL2_BASE_IDX 1 |
| #define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x0087 |
| #define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 1 |
| #define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL2 0x0088 |
| #define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL2_BASE_IDX 1 |
| #define mmDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x0089 |
| #define mmDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 1 |
| #define mmDAGB0_WRCLI_ASK_PENDING 0x008a |
| #define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1 |
| #define mmDAGB0_WRCLI_GO_PENDING 0x008b |
| #define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 1 |
| #define mmDAGB0_WRCLI_GBLSEND_PENDING 0x008c |
| #define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1 |
| #define mmDAGB0_WRCLI_TLB_PENDING 0x008d |
| #define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1 |
| #define mmDAGB0_WRCLI_OARB_PENDING 0x008e |
| #define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1 |
| #define mmDAGB0_WRCLI_OSD_PENDING 0x008f |
| #define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1 |
| #define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x0090 |
| #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 |
| #define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0091 |
| #define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 |
| #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x0092 |
| #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1 |
| #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x0093 |
| #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1 |
| #define mmDAGB0_DAGB_DLY 0x0094 |
| #define mmDAGB0_DAGB_DLY_BASE_IDX 1 |
| #define mmDAGB0_CNTL_MISC 0x0095 |
| #define mmDAGB0_CNTL_MISC_BASE_IDX 1 |
| #define mmDAGB0_CNTL_MISC2 0x0096 |
| #define mmDAGB0_CNTL_MISC2_BASE_IDX 1 |
| #define mmDAGB0_FIFO_EMPTY 0x0097 |
| #define mmDAGB0_FIFO_EMPTY_BASE_IDX 1 |
| #define mmDAGB0_FIFO_FULL 0x0098 |
| #define mmDAGB0_FIFO_FULL_BASE_IDX 1 |
| #define mmDAGB0_WR_CREDITS_FULL 0x0099 |
| #define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 1 |
| #define mmDAGB0_RD_CREDITS_FULL 0x009a |
| #define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 1 |
| #define mmDAGB0_PERFCOUNTER_LO 0x009b |
| #define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 1 |
| #define mmDAGB0_PERFCOUNTER_HI 0x009c |
| #define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 1 |
| #define mmDAGB0_PERFCOUNTER0_CFG 0x009d |
| #define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1 |
| #define mmDAGB0_PERFCOUNTER1_CFG 0x009e |
| #define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1 |
| #define mmDAGB0_PERFCOUNTER2_CFG 0x009f |
| #define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1 |
| #define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x00a0 |
| #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
| #define mmDAGB0_RESERVE0 0x00a1 |
| #define mmDAGB0_RESERVE0_BASE_IDX 1 |
| #define mmDAGB0_RESERVE1 0x00a2 |
| #define mmDAGB0_RESERVE1_BASE_IDX 1 |
| #define mmDAGB0_RESERVE2 0x00a3 |
| #define mmDAGB0_RESERVE2_BASE_IDX 1 |
| #define mmDAGB0_RESERVE3 0x00a4 |
| #define mmDAGB0_RESERVE3_BASE_IDX 1 |
| #define mmDAGB0_RESERVE4 0x00a5 |
| #define mmDAGB0_RESERVE4_BASE_IDX 1 |
| #define mmDAGB0_RESERVE5 0x00a6 |
| #define mmDAGB0_RESERVE5_BASE_IDX 1 |
| #define mmDAGB0_RESERVE6 0x00a7 |
| #define mmDAGB0_RESERVE6_BASE_IDX 1 |
| #define mmDAGB0_RESERVE7 0x00a8 |
| #define mmDAGB0_RESERVE7_BASE_IDX 1 |
| #define mmDAGB0_RESERVE8 0x00a9 |
| #define mmDAGB0_RESERVE8_BASE_IDX 1 |
| #define mmDAGB0_RESERVE9 0x00aa |
| #define mmDAGB0_RESERVE9_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmea_mmeadec0 |
| // base address: 0x68400 |
| #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100 |
| #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 |
| #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101 |
| #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 |
| #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102 |
| #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 |
| #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103 |
| #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 |
| #define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104 |
| #define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 |
| #define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105 |
| #define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 |
| #define mmMMEA0_DRAM_RD_LAZY 0x0106 |
| #define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 1 |
| #define mmMMEA0_DRAM_WR_LAZY 0x0107 |
| #define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 1 |
| #define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108 |
| #define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 1 |
| #define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109 |
| #define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 1 |
| #define mmMMEA0_DRAM_PAGE_BURST 0x010a |
| #define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 1 |
| #define mmMMEA0_DRAM_RD_PRI_AGE 0x010b |
| #define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 1 |
| #define mmMMEA0_DRAM_WR_PRI_AGE 0x010c |
| #define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 1 |
| #define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d |
| #define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 1 |
| #define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e |
| #define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 1 |
| #define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f |
| #define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 1 |
| #define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110 |
| #define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 1 |
| #define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111 |
| #define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 1 |
| #define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112 |
| #define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 1 |
| #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113 |
| #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
| #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114 |
| #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
| #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115 |
| #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
| #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116 |
| #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
| #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117 |
| #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
| #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118 |
| #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
| #define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0134 |
| #define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 1 |
| #define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0135 |
| #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 |
| #define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0136 |
| #define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 1 |
| #define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0137 |
| #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 |
| #define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0138 |
| #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 |
| #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0143 |
| #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 |
| #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0145 |
| #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC_BANK_CFG 0x0147 |
| #define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC_MISC_CFG 0x0148 |
| #define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0149 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x014a |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x014b |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x014c |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x014d |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 0x014e |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x014f |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x0150 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x0151 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x0152 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0153 |
| #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0 0x0154 |
| #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0 0x0155 |
| #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1 0x0156 |
| #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1 0x0157 |
| #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x0167 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0168 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x0169 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x016a |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x016b |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x016c |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x016d |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x016e |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x016f |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0170 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0171 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0172 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0173 |
| #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x0174 |
| #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x0175 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x0176 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0x0177 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0x0178 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0179 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x017a |
| #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x017b |
| #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x017c |
| #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x017d |
| #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x017e |
| #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_CS1 0x017f |
| #define mmMMEA0_ADDRDEC0_RM_SEL_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_CS3 0x0180 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0181 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x0182 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x0183 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0184 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0185 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x0186 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x0187 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0188 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0189 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x018a |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x018b |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x018c |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x018d |
| #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x018e |
| #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x018f |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0190 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0x0191 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0x0192 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x0193 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x0194 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x0195 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0196 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0197 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0198 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_CS1 0x0199 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_CS3 0x019a |
| #define mmMMEA0_ADDRDEC1_RM_SEL_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0x01b5 |
| #define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ0 0x01b7 |
| #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ0_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ1 0x01b8 |
| #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ2 0x01b9 |
| #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ2_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ3 0x01ba |
| #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ4 0x01bb |
| #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ4_BASE_IDX 1 |
| #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ5 0x01bc |
| #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ5_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS1 0x01c3 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS3 0x01c4 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS1 0x01c5 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS3 0x01c6 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS1 0x01c7 |
| #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS3 0x01c8 |
| #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS1 0x01c9 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS3 0x01ca |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS1 0x01cb |
| #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS3 0x01cc |
| #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS1 0x01cd |
| #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS3 0x01ce |
| #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS1 0x01cf |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS3 0x01d0 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS1 0x01d1 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS3 0x01d2 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS1 0x01d3 |
| #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS3 0x01d4 |
| #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS1 0x01d5 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS3 0x01d6 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS1 0x01d7 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS3 0x01d8 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS1 0x01d9 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS1_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS3 0x01da |
| #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS3_BASE_IDX 1 |
| #define mmMMEA0_ADDRNORMDRAM_MASKING 0x01db |
| #define mmMMEA0_ADDRNORMDRAM_MASKING_BASE_IDX 1 |
| #define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01dd |
| #define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 |
| #define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01de |
| #define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 |
| #define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01df |
| #define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 |
| #define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01e0 |
| #define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 |
| #define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01e1 |
| #define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 1 |
| #define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01e2 |
| #define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 1 |
| #define mmMMEA0_IO_GROUP_BURST 0x01e3 |
| #define mmMMEA0_IO_GROUP_BURST_BASE_IDX 1 |
| #define mmMMEA0_IO_RD_PRI_AGE 0x01e4 |
| #define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 1 |
| #define mmMMEA0_IO_WR_PRI_AGE 0x01e5 |
| #define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 1 |
| #define mmMMEA0_IO_RD_PRI_QUEUING 0x01e6 |
| #define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 1 |
| #define mmMMEA0_IO_WR_PRI_QUEUING 0x01e7 |
| #define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 1 |
| #define mmMMEA0_IO_RD_PRI_FIXED 0x01e8 |
| #define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 1 |
| #define mmMMEA0_IO_WR_PRI_FIXED 0x01e9 |
| #define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 1 |
| #define mmMMEA0_IO_RD_PRI_URGENCY 0x01ea |
| #define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 1 |
| #define mmMMEA0_IO_WR_PRI_URGENCY 0x01eb |
| #define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 1 |
| #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0x01ec |
| #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 |
| #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0x01ed |
| #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 |
| #define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01ee |
| #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 |
| #define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01ef |
| #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 |
| #define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01f0 |
| #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 |
| #define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01f1 |
| #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 |
| #define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01f2 |
| #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 |
| #define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01f3 |
| #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 |
| #define mmMMEA0_SDP_ARB_DRAM 0x01f4 |
| #define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 1 |
| #define mmMMEA0_SDP_ARB_FINAL 0x01f6 |
| #define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 1 |
| #define mmMMEA0_SDP_DRAM_PRIORITY 0x01f7 |
| #define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 1 |
| #define mmMMEA0_SDP_IO_PRIORITY 0x01f9 |
| #define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 1 |
| #define mmMMEA0_SDP_CREDITS 0x01fa |
| #define mmMMEA0_SDP_CREDITS_BASE_IDX 1 |
| #define mmMMEA0_SDP_TAG_RESERVE0 0x01fb |
| #define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 1 |
| #define mmMMEA0_SDP_TAG_RESERVE1 0x01fc |
| #define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 1 |
| #define mmMMEA0_SDP_VCC_RESERVE0 0x01fd |
| #define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 1 |
| #define mmMMEA0_SDP_VCC_RESERVE1 0x01fe |
| #define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 1 |
| #define mmMMEA0_SDP_VCD_RESERVE0 0x01ff |
| #define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 1 |
| #define mmMMEA0_SDP_VCD_RESERVE1 0x0200 |
| #define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 1 |
| #define mmMMEA0_SDP_REQ_CNTL 0x0201 |
| #define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 1 |
| #define mmMMEA0_MISC 0x0202 |
| #define mmMMEA0_MISC_BASE_IDX 1 |
| #define mmMMEA0_LATENCY_SAMPLING 0x0203 |
| #define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 1 |
| #define mmMMEA0_PERFCOUNTER_LO 0x0204 |
| #define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 1 |
| #define mmMMEA0_PERFCOUNTER_HI 0x0205 |
| #define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 1 |
| #define mmMMEA0_PERFCOUNTER0_CFG 0x0206 |
| #define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 1 |
| #define mmMMEA0_PERFCOUNTER1_CFG 0x0207 |
| #define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 1 |
| #define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0208 |
| #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
| #define mmMMEA0_EDC_CNT 0x020f |
| #define mmMMEA0_EDC_CNT_BASE_IDX 1 |
| #define mmMMEA0_EDC_CNT2 0x0210 |
| #define mmMMEA0_EDC_CNT2_BASE_IDX 1 |
| #define mmMMEA0_DSM_CNTL 0x0211 |
| #define mmMMEA0_DSM_CNTL_BASE_IDX 1 |
| #define mmMMEA0_DSM_CNTLA 0x0212 |
| #define mmMMEA0_DSM_CNTLA_BASE_IDX 1 |
| #define mmMMEA0_DSM_CNTLB 0x0213 |
| #define mmMMEA0_DSM_CNTLB_BASE_IDX 1 |
| #define mmMMEA0_DSM_CNTL2 0x0214 |
| #define mmMMEA0_DSM_CNTL2_BASE_IDX 1 |
| #define mmMMEA0_DSM_CNTL2A 0x0215 |
| #define mmMMEA0_DSM_CNTL2A_BASE_IDX 1 |
| #define mmMMEA0_DSM_CNTL2B 0x0216 |
| #define mmMMEA0_DSM_CNTL2B_BASE_IDX 1 |
| #define mmMMEA0_CGTT_CLK_CTRL 0x0218 |
| #define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 1 |
| #define mmMMEA0_EDC_MODE 0x0219 |
| #define mmMMEA0_EDC_MODE_BASE_IDX 1 |
| #define mmMMEA0_ERR_STATUS 0x021a |
| #define mmMMEA0_ERR_STATUS_BASE_IDX 1 |
| #define mmMMEA0_MISC2 0x021b |
| #define mmMMEA0_MISC2_BASE_IDX 1 |
| #define mmMMEA0_ADDRDEC_SELECT 0x021c |
| #define mmMMEA0_ADDRDEC_SELECT_BASE_IDX 1 |
| #define mmMMEA0_EDC_CNT3 0x021d |
| #define mmMMEA0_EDC_CNT3_BASE_IDX 1 |
| #define mmMMEA0_SDP_PRIORITY_OVERRIDE 0x021e |
| #define mmMMEA0_SDP_PRIORITY_OVERRIDE_BASE_IDX 1 |
| #define mmMMEA0_MISC_AON 0x021f |
| #define mmMMEA0_MISC_AON_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_pctldec |
| // base address: 0x68e00 |
| #define mmPCTL_CTRL 0x0380 |
| #define mmPCTL_CTRL_BASE_IDX 1 |
| #define mmPCTL_MMHUB_DEEPSLEEP_IB 0x0381 |
| #define mmPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 |
| #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 |
| #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 |
| #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0383 |
| #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 |
| #define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0384 |
| #define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 |
| #define mmPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0385 |
| #define mmPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 |
| #define mmPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0386 |
| #define mmPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 1 |
| #define mmPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0387 |
| #define mmPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 1 |
| #define mmPCTL_SLICE0_CFG_DS_ALLOW 0x0388 |
| #define mmPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 |
| #define mmPCTL_SLICE0_CFG_DS_ALLOW_IB 0x0389 |
| #define mmPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 |
| #define mmPCTL_SLICE1_CFG_DAGB_WRBUSY 0x038a |
| #define mmPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 1 |
| #define mmPCTL_SLICE1_CFG_DAGB_RDBUSY 0x038b |
| #define mmPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 1 |
| #define mmPCTL_SLICE1_CFG_DS_ALLOW 0x038c |
| #define mmPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 |
| #define mmPCTL_SLICE1_CFG_DS_ALLOW_IB 0x038d |
| #define mmPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 |
| #define mmPCTL_UTCL2_MISC 0x038e |
| #define mmPCTL_UTCL2_MISC_BASE_IDX 1 |
| #define mmPCTL_SLICE0_MISC 0x038f |
| #define mmPCTL_SLICE0_MISC_BASE_IDX 1 |
| #define mmPCTL_SLICE1_MISC 0x0390 |
| #define mmPCTL_SLICE1_MISC_BASE_IDX 1 |
| #define mmPCTL_RENG_CTRL 0x0391 |
| #define mmPCTL_RENG_CTRL_BASE_IDX 1 |
| #define mmPCTL_UTCL2_RENG_EXECUTE 0x0392 |
| #define mmPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 1 |
| #define mmPCTL_SLICE0_RENG_EXECUTE 0x0393 |
| #define mmPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 1 |
| #define mmPCTL_SLICE1_RENG_EXECUTE 0x0394 |
| #define mmPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 1 |
| #define mmPCTL_UTCL2_RENG_RAM_INDEX 0x0395 |
| #define mmPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 |
| #define mmPCTL_UTCL2_RENG_RAM_DATA 0x0396 |
| #define mmPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 1 |
| #define mmPCTL_SLICE0_RENG_RAM_INDEX 0x0397 |
| #define mmPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 |
| #define mmPCTL_SLICE0_RENG_RAM_DATA 0x0398 |
| #define mmPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 1 |
| #define mmPCTL_SLICE1_RENG_RAM_INDEX 0x0399 |
| #define mmPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 |
| #define mmPCTL_SLICE1_RENG_RAM_DATA 0x039a |
| #define mmPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 1 |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x039e |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x039f |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a0 |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a1 |
| #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x03a2 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x03a3 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x03a4 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x03a5 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x03a6 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a7 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a8 |
| #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x03a9 |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x03aa |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x03ab |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x03ac |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x03ad |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03ae |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03af |
| #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 |
| #define mmPCTL_STATUS 0x03b0 |
| #define mmPCTL_STATUS_BASE_IDX 1 |
| #define mmPCTL_PERFCOUNTER_LO 0x03b1 |
| #define mmPCTL_PERFCOUNTER_LO_BASE_IDX 1 |
| #define mmPCTL_PERFCOUNTER_HI 0x03b2 |
| #define mmPCTL_PERFCOUNTER_HI_BASE_IDX 1 |
| #define mmPCTL_PERFCOUNTER0_CFG 0x03b3 |
| #define mmPCTL_PERFCOUNTER0_CFG_BASE_IDX 1 |
| #define mmPCTL_PERFCOUNTER1_CFG 0x03b4 |
| #define mmPCTL_PERFCOUNTER1_CFG_BASE_IDX 1 |
| #define mmPCTL_PERFCOUNTER_RSLT_CNTL 0x03b5 |
| #define mmPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
| #define mmPCTL_RESERVED_0 0x03b6 |
| #define mmPCTL_RESERVED_0_BASE_IDX 1 |
| #define mmPCTL_RESERVED_1 0x03b7 |
| #define mmPCTL_RESERVED_1_BASE_IDX 1 |
| #define mmPCTL_RESERVED_2 0x03b8 |
| #define mmPCTL_RESERVED_2_BASE_IDX 1 |
| #define mmPCTL_RESERVED_3 0x03b9 |
| #define mmPCTL_RESERVED_3_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_l1tlb_mmutcl1pfdec |
| // base address: 0x69600 |
| #define mmMMMC_VM_MX_L1_TLB0_STATUS 0x0588 |
| #define mmMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLB1_STATUS 0x0589 |
| #define mmMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLB2_STATUS 0x058a |
| #define mmMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLB3_STATUS 0x058b |
| #define mmMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLB4_STATUS 0x058c |
| #define mmMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLB5_STATUS 0x058d |
| #define mmMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLB6_STATUS 0x058e |
| #define mmMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLB7_STATUS 0x058f |
| #define mmMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_l1tlb_mmutcl1pldec |
| // base address: 0x69670 |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x059c |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x059d |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x059e |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x059f |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x05a0 |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_l1tlb_mmutcl1prdec |
| // base address: 0x69690 |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER_LO 0x05a4 |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER_HI 0x05a5 |
| #define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_l1tlb_mmvmtlspfdec |
| // base address: 0x696c0 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL 0x05b0 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL0 0x05b1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL0_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL1 0x05b2 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL1_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL2 0x05b3 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL2_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL3 0x05b4 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL3_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL4 0x05b5 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL4_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL5 0x05b6 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL5_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL6 0x05b7 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL6_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL7 0x05b8 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL7_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL8 0x05b9 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL8_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL9 0x05ba |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL9_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL10 0x05bb |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL10_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL11 0x05bc |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL11_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL12 0x05bd |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL12_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL13 0x05be |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL13_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL14 0x05bf |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL14_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL15 0x05c0 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL15_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL16 0x05c1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL16_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL17 0x05c2 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL17_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL18 0x05c3 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL18_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL19 0x05c4 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL19_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL20 0x05c5 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL20_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL21 0x05c6 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL21_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL22 0x05c7 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL22_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL23 0x05c8 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL23_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL24 0x05c9 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL24_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL25 0x05ca |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL25_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL26 0x05cb |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL26_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL27 0x05cc |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL27_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL28 0x05cd |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL28_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL29 0x05ce |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL29_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL30 0x05cf |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL30_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL31 0x05d0 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL31_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL32 0x05d1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL33 0x05d2 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL33_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL34 0x05d3 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL34_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL35 0x05d4 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL35_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL36 0x05d5 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL36_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL37 0x05d6 |
| #define mmMMMC_VM_MX_L1_TLS0_CNTL37_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 0x05d7 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 0x05d8 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 0x05d9 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 0x05da |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 0x05db |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 0x05dc |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 0x05dd |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 0x05de |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 0x05df |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 0x05e0 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 0x05e1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 0x05e2 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 0x05e3 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 0x05e4 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 0x05e5 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 0x05e6 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 0x05e7 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 0x05e8 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 0x05e9 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 0x05ea |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 0x05eb |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 0x05ec |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 0x05ed |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 0x05ee |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 0x05ef |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 0x05f0 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 0x05f1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 0x05f2 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 0x05f3 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 0x05f4 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 0x05f5 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 0x05f6 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 0x05f7 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 0x05f8 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 0x05f9 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 0x05fa |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 0x05fb |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 0x05fc |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 0x05fd |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 0x05fe |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 0x05ff |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 0x0600 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 0x0601 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 0x0602 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 0x0603 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 0x0604 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 0x0605 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 0x0606 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 0x0607 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 0x0608 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 0x0609 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 0x060a |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 0x060b |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 0x060c |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 0x060d |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 0x060e |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 0x060f |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 0x0610 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 0x0611 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 0x0612 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 0x0613 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 0x0614 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 0x0615 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 0x0616 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 0x0617 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 0x0618 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 0x0619 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 0x061a |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 0x061b |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 0x061c |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 0x061d |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 0x061e |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 0x061f |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 0x0620 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 0x0621 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 0x0622 |
| #define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 0x0623 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 0x0624 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 0x0625 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 0x0626 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 0x0627 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 0x0628 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 0x0629 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 0x062a |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 0x062b |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 0x062c |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 0x062d |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 0x062e |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 0x062f |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 0x0630 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 0x0631 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 0x0632 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 0x0633 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 0x0634 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 0x0635 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 0x0636 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 0x0637 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 0x0638 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 0x0639 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 0x063a |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 0x063b |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 0x063c |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 0x063d |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 0x063e |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 0x063f |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 0x0640 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 0x0641 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 0x0642 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 0x0643 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 0x0644 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 0x0645 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 0x0646 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 0x0647 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 0x0648 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 0x0649 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 0x064a |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 0x064b |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 0x064c |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 0x064d |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 0x064e |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 0x064f |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 0x0650 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 0x0651 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 0x0652 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 0x0653 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 0x0654 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 0x0655 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 0x0656 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 0x0657 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 0x0658 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 0x0659 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 0x065a |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 0x065b |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 0x065c |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 0x065d |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 0x065e |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 0x065f |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 0x0660 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 0x0661 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 0x0662 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 0x0663 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 0x0664 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 0x0665 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 0x0666 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 0x0667 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 0x0668 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 0x0669 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 0x066a |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 0x066b |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 0x066c |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 0x066d |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 0x066e |
| #define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 0x066f |
| #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 0x0670 |
| #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 0x0671 |
| #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 0x0672 |
| #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS 0x0673 |
| #define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 0x0674 |
| #define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 0x0675 |
| #define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CNTL 0x0676 |
| #define mmMMVM_L2_SAW_CNTL_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CNTL2 0x0677 |
| #define mmMMVM_L2_SAW_CNTL2_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CNTL3 0x0678 |
| #define mmMMVM_L2_SAW_CNTL3_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CNTL4 0x0679 |
| #define mmMMVM_L2_SAW_CNTL4_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CONTEXT0_CNTL 0x067a |
| #define mmMMVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CONTEXT0_CNTL2 0x067b |
| #define mmMMVM_L2_SAW_CONTEXT0_CNTL2_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x067c |
| #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x067d |
| #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x067e |
| #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x067f |
| #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0680 |
| #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0681 |
| #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_CONTEXTS_DISABLE 0x0682 |
| #define mmMMVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_PIPES_BUSY_LO32 0x0683 |
| #define mmMMVM_L2_SAW_PIPES_BUSY_LO32_BASE_IDX 1 |
| #define mmMMVM_L2_SAW_PIPES_BUSY_HI32 0x0684 |
| #define mmMMVM_L2_SAW_PIPES_BUSY_HI32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS 0x0685 |
| #define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 0x0686 |
| #define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 0x0687 |
| #define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mmatcl2dec |
| // base address: 0x69b00 |
| #define mmMM_ATC_L2_CNTL 0x06c0 |
| #define mmMM_ATC_L2_CNTL_BASE_IDX 1 |
| #define mmMM_ATC_L2_CNTL2 0x06c1 |
| #define mmMM_ATC_L2_CNTL2_BASE_IDX 1 |
| #define mmMM_ATC_L2_CACHE_DATA0 0x06c4 |
| #define mmMM_ATC_L2_CACHE_DATA0_BASE_IDX 1 |
| #define mmMM_ATC_L2_CACHE_DATA1 0x06c5 |
| #define mmMM_ATC_L2_CACHE_DATA1_BASE_IDX 1 |
| #define mmMM_ATC_L2_CACHE_DATA2 0x06c6 |
| #define mmMM_ATC_L2_CACHE_DATA2_BASE_IDX 1 |
| #define mmMM_ATC_L2_CNTL3 0x06c7 |
| #define mmMM_ATC_L2_CNTL3_BASE_IDX 1 |
| #define mmMM_ATC_L2_CNTL4 0x06c8 |
| #define mmMM_ATC_L2_CNTL4_BASE_IDX 1 |
| #define mmMM_ATC_L2_CNTL5 0x06c9 |
| #define mmMM_ATC_L2_CNTL5_BASE_IDX 1 |
| #define mmMM_ATC_L2_MM_GROUP_RT_CLASSES 0x06ca |
| #define mmMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 |
| #define mmMM_ATC_L2_STATUS 0x06cb |
| #define mmMM_ATC_L2_STATUS_BASE_IDX 1 |
| #define mmMM_ATC_L2_STATUS2 0x06cc |
| #define mmMM_ATC_L2_STATUS2_BASE_IDX 1 |
| #define mmMM_ATC_L2_MISC_CG 0x06cd |
| #define mmMM_ATC_L2_MISC_CG_BASE_IDX 1 |
| #define mmMM_ATC_L2_MEM_POWER_LS 0x06ce |
| #define mmMM_ATC_L2_MEM_POWER_LS_BASE_IDX 1 |
| #define mmMM_ATC_L2_CGTT_CLK_CTRL 0x06cf |
| #define mmMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 |
| #define mmMM_ATC_L2_SDPPORT_CTRL 0x06d2 |
| #define mmMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mmvml2pfdec |
| // base address: 0x69c00 |
| #define mmMMVM_L2_CNTL 0x0700 |
| #define mmMMVM_L2_CNTL_BASE_IDX 1 |
| #define mmMMVM_L2_CNTL2 0x0701 |
| #define mmMMVM_L2_CNTL2_BASE_IDX 1 |
| #define mmMMVM_L2_CNTL3 0x0702 |
| #define mmMMVM_L2_CNTL3_BASE_IDX 1 |
| #define mmMMVM_L2_STATUS 0x0703 |
| #define mmMMVM_L2_STATUS_BASE_IDX 1 |
| #define mmMMVM_DUMMY_PAGE_FAULT_CNTL 0x0704 |
| #define mmMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 |
| #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0705 |
| #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0706 |
| #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_CNTL 0x0707 |
| #define mmMMVM_INVALIDATE_CNTL_BASE_IDX 1 |
| #define mmMMVM_L2_PROTECTION_FAULT_CNTL 0x0708 |
| #define mmMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1 |
| #define mmMMVM_L2_PROTECTION_FAULT_CNTL2 0x0709 |
| #define mmMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 |
| #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x070a |
| #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1 |
| #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x070b |
| #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1 |
| #define mmMMVM_L2_PROTECTION_FAULT_STATUS 0x070c |
| #define mmMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1 |
| #define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x070d |
| #define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x070e |
| #define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x070f |
| #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0710 |
| #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0712 |
| #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0713 |
| #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0714 |
| #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0715 |
| #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0716 |
| #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0717 |
| #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 |
| #define mmMMVM_L2_CNTL4 0x0718 |
| #define mmMMVM_L2_CNTL4_BASE_IDX 1 |
| #define mmMMVM_L2_MM_GROUP_RT_CLASSES 0x0719 |
| #define mmMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 |
| #define mmMMVM_L2_BANK_SELECT_RESERVED_CID 0x071a |
| #define mmMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 |
| #define mmMMVM_L2_BANK_SELECT_RESERVED_CID2 0x071b |
| #define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 |
| #define mmMMVM_L2_CACHE_PARITY_CNTL 0x071c |
| #define mmMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 |
| #define mmMMVM_L2_IH_LOG_CNTL 0x071d |
| #define mmMMVM_L2_IH_LOG_CNTL_BASE_IDX 1 |
| #define mmMMVM_L2_IH_LOG_BUSY 0x071e |
| #define mmMMVM_L2_IH_LOG_BUSY_BASE_IDX 1 |
| #define mmMMVM_L2_CGTT_CLK_CTRL 0x071f |
| #define mmMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 1 |
| #define mmMMVM_L2_CNTL5 0x0720 |
| #define mmMMVM_L2_CNTL5_BASE_IDX 1 |
| #define mmMMVM_L2_GCR_CNTL 0x0721 |
| #define mmMMVM_L2_GCR_CNTL_BASE_IDX 1 |
| #define mmMMVM_L2_CGTT_BUSY_CTRL 0x0722 |
| #define mmMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 1 |
| #define mmMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0723 |
| #define mmMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 1 |
| #define mmMMVM_L2_PTE_CACHE_DUMP_READ 0x0724 |
| #define mmMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mmvml2vcdec |
| // base address: 0x69d00 |
| #define mmMMVM_CONTEXT0_CNTL 0x0740 |
| #define mmMMVM_CONTEXT0_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT1_CNTL 0x0741 |
| #define mmMMVM_CONTEXT1_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT2_CNTL 0x0742 |
| #define mmMMVM_CONTEXT2_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT3_CNTL 0x0743 |
| #define mmMMVM_CONTEXT3_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT4_CNTL 0x0744 |
| #define mmMMVM_CONTEXT4_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT5_CNTL 0x0745 |
| #define mmMMVM_CONTEXT5_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT6_CNTL 0x0746 |
| #define mmMMVM_CONTEXT6_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT7_CNTL 0x0747 |
| #define mmMMVM_CONTEXT7_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT8_CNTL 0x0748 |
| #define mmMMVM_CONTEXT8_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT9_CNTL 0x0749 |
| #define mmMMVM_CONTEXT9_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT10_CNTL 0x074a |
| #define mmMMVM_CONTEXT10_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT11_CNTL 0x074b |
| #define mmMMVM_CONTEXT11_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT12_CNTL 0x074c |
| #define mmMMVM_CONTEXT12_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT13_CNTL 0x074d |
| #define mmMMVM_CONTEXT13_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT14_CNTL 0x074e |
| #define mmMMVM_CONTEXT14_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXT15_CNTL 0x074f |
| #define mmMMVM_CONTEXT15_CNTL_BASE_IDX 1 |
| #define mmMMVM_CONTEXTS_DISABLE 0x0750 |
| #define mmMMVM_CONTEXTS_DISABLE_BASE_IDX 1 |
| #define mmMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0751 |
| #define mmMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0752 |
| #define mmMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0753 |
| #define mmMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0754 |
| #define mmMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0755 |
| #define mmMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0756 |
| #define mmMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0757 |
| #define mmMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0758 |
| #define mmMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0759 |
| #define mmMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x075a |
| #define mmMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x075b |
| #define mmMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x075c |
| #define mmMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x075d |
| #define mmMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x075e |
| #define mmMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x075f |
| #define mmMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0760 |
| #define mmMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| #define mmMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0761 |
| #define mmMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mmvml2pldec |
| // base address: 0x6a090 |
| #define mmMMMC_VM_L2_PERFCOUNTER0_CFG 0x0824 |
| #define mmMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 |
| #define mmMMMC_VM_L2_PERFCOUNTER1_CFG 0x0825 |
| #define mmMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 |
| #define mmMMMC_VM_L2_PERFCOUNTER2_CFG 0x0826 |
| #define mmMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 |
| #define mmMMMC_VM_L2_PERFCOUNTER3_CFG 0x0827 |
| #define mmMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 |
| #define mmMMMC_VM_L2_PERFCOUNTER4_CFG 0x0828 |
| #define mmMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 |
| #define mmMMMC_VM_L2_PERFCOUNTER5_CFG 0x0829 |
| #define mmMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 |
| #define mmMMMC_VM_L2_PERFCOUNTER6_CFG 0x082a |
| #define mmMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 |
| #define mmMMMC_VM_L2_PERFCOUNTER7_CFG 0x082b |
| #define mmMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 |
| #define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x082c |
| #define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
| #define mmMMUTCL2_PERFCOUNTER0_CFG 0x082d |
| #define mmMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 |
| #define mmMMUTCL2_PERFCOUNTER1_CFG 0x082e |
| #define mmMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 |
| #define mmMMUTCL2_PERFCOUNTER2_CFG 0x082f |
| #define mmMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 |
| #define mmMMUTCL2_PERFCOUNTER3_CFG 0x0830 |
| #define mmMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 |
| #define mmMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x0831 |
| #define mmMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mmvml2prdec |
| // base address: 0x6a0e0 |
| #define mmMMMC_VM_L2_PERFCOUNTER_LO 0x0838 |
| #define mmMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 |
| #define mmMMMC_VM_L2_PERFCOUNTER_HI 0x0839 |
| #define mmMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 |
| #define mmMMUTCL2_PERFCOUNTER_LO 0x083a |
| #define mmMMUTCL2_PERFCOUNTER_LO_BASE_IDX 1 |
| #define mmMMUTCL2_PERFCOUNTER_HI 0x083b |
| #define mmMMUTCL2_PERFCOUNTER_HI_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec |
| // base address: 0x6a130 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF0 0x084c |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF1 0x084d |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF2 0x084e |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF3 0x084f |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF4 0x0850 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF5 0x0851 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF6 0x0852 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF7 0x0853 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF8 0x0854 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF9 0x0855 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF10 0x0856 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF11 0x0857 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF12 0x0858 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF13 0x0859 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF14 0x085a |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF15 0x085b |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF16 0x085c |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF17 0x085d |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF18 0x085e |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF19 0x085f |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF20 0x0860 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF21 0x0861 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF22 0x0862 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF23 0x0863 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF24 0x0864 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF25 0x0865 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF26 0x0866 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF27 0x0867 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF28 0x0868 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF29 0x0869 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF30 0x086a |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX 1 |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF31 0x086b |
| #define mmMMMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX 1 |
| #define mmMMVM_IOMMU_MMIO_CNTRL_1 0x086c |
| #define mmMMVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_BASE_LO_0 0x086d |
| #define mmMMMC_VM_MARC_BASE_LO_0_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_BASE_LO_1 0x086e |
| #define mmMMMC_VM_MARC_BASE_LO_1_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_BASE_LO_2 0x086f |
| #define mmMMMC_VM_MARC_BASE_LO_2_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_BASE_LO_3 0x0870 |
| #define mmMMMC_VM_MARC_BASE_LO_3_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_BASE_HI_0 0x0871 |
| #define mmMMMC_VM_MARC_BASE_HI_0_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_BASE_HI_1 0x0872 |
| #define mmMMMC_VM_MARC_BASE_HI_1_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_BASE_HI_2 0x0873 |
| #define mmMMMC_VM_MARC_BASE_HI_2_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_BASE_HI_3 0x0874 |
| #define mmMMMC_VM_MARC_BASE_HI_3_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_RELOC_LO_0 0x0875 |
| #define mmMMMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_RELOC_LO_1 0x0876 |
| #define mmMMMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_RELOC_LO_2 0x0877 |
| #define mmMMMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_RELOC_LO_3 0x0878 |
| #define mmMMMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_RELOC_HI_0 0x0879 |
| #define mmMMMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_RELOC_HI_1 0x087a |
| #define mmMMMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_RELOC_HI_2 0x087b |
| #define mmMMMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_RELOC_HI_3 0x087c |
| #define mmMMMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_LEN_LO_0 0x087d |
| #define mmMMMC_VM_MARC_LEN_LO_0_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_LEN_LO_1 0x087e |
| #define mmMMMC_VM_MARC_LEN_LO_1_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_LEN_LO_2 0x087f |
| #define mmMMMC_VM_MARC_LEN_LO_2_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_LEN_LO_3 0x0880 |
| #define mmMMMC_VM_MARC_LEN_LO_3_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_LEN_HI_0 0x0881 |
| #define mmMMMC_VM_MARC_LEN_HI_0_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_LEN_HI_1 0x0882 |
| #define mmMMMC_VM_MARC_LEN_HI_1_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_LEN_HI_2 0x0883 |
| #define mmMMMC_VM_MARC_LEN_HI_2_BASE_IDX 1 |
| #define mmMMMC_VM_MARC_LEN_HI_3 0x0884 |
| #define mmMMMC_VM_MARC_LEN_HI_3_BASE_IDX 1 |
| #define mmMMVM_IOMMU_CONTROL_REGISTER 0x0885 |
| #define mmMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 |
| #define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0886 |
| #define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL 0x0887 |
| #define mmMMVM_PCIE_ATS_CNTL_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_0 0x0888 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_1 0x0889 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_2 0x088a |
| #define mmMMVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_3 0x088b |
| #define mmMMVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_4 0x088c |
| #define mmMMVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_5 0x088d |
| #define mmMMVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_6 0x088e |
| #define mmMMVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_7 0x088f |
| #define mmMMVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_8 0x0890 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_9 0x0891 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_10 0x0892 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_11 0x0893 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_12 0x0894 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_13 0x0895 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_14 0x0896 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_15 0x0897 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_16 0x0898 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_16_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_17 0x0899 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_17_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_18 0x089a |
| #define mmMMVM_PCIE_ATS_CNTL_VF_18_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_19 0x089b |
| #define mmMMVM_PCIE_ATS_CNTL_VF_19_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_20 0x089c |
| #define mmMMVM_PCIE_ATS_CNTL_VF_20_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_21 0x089d |
| #define mmMMVM_PCIE_ATS_CNTL_VF_21_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_22 0x089e |
| #define mmMMVM_PCIE_ATS_CNTL_VF_22_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_23 0x089f |
| #define mmMMVM_PCIE_ATS_CNTL_VF_23_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_24 0x08a0 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_24_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_25 0x08a1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_25_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_26 0x08a2 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_26_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_27 0x08a3 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_27_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_28 0x08a4 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_28_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_29 0x08a5 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_29_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_30 0x08a6 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_30_BASE_IDX 1 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_31 0x08a7 |
| #define mmMMVM_PCIE_ATS_CNTL_VF_31_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec |
| // base address: 0x6a340 |
| #define mmMMMC_VM_NB_MMIOBASE 0x08d0 |
| #define mmMMMC_VM_NB_MMIOBASE_BASE_IDX 1 |
| #define mmMMMC_VM_NB_MMIOLIMIT 0x08d1 |
| #define mmMMMC_VM_NB_MMIOLIMIT_BASE_IDX 1 |
| #define mmMMMC_VM_NB_PCI_CTRL 0x08d2 |
| #define mmMMMC_VM_NB_PCI_CTRL_BASE_IDX 1 |
| #define mmMMMC_VM_NB_PCI_ARB 0x08d3 |
| #define mmMMMC_VM_NB_PCI_ARB_BASE_IDX 1 |
| #define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x08d4 |
| #define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 |
| #define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x08d5 |
| #define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 |
| #define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x08d6 |
| #define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 |
| #define mmMMMC_VM_FB_OFFSET 0x08d7 |
| #define mmMMMC_VM_FB_OFFSET_BASE_IDX 1 |
| #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x08d8 |
| #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 |
| #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x08d9 |
| #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 |
| #define mmMMMC_VM_STEERING 0x08da |
| #define mmMMMC_VM_STEERING_BASE_IDX 1 |
| #define mmMMMC_SHARED_VIRT_RESET_REQ 0x08db |
| #define mmMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 |
| #define mmMMMC_MEM_POWER_LS 0x08dc |
| #define mmMMMC_MEM_POWER_LS_BASE_IDX 1 |
| #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x08dd |
| #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 |
| #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x08de |
| #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 |
| #define mmMMMC_VM_APT_CNTL 0x08df |
| #define mmMMMC_VM_APT_CNTL_BASE_IDX 1 |
| #define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x08e0 |
| #define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 1 |
| #define mmMMMC_VM_LOCAL_HBM_ADDRESS_START 0x08e1 |
| #define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 1 |
| #define mmMMMC_VM_LOCAL_HBM_ADDRESS_END 0x08e2 |
| #define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 1 |
| #define mmMMUTCL2_CGTT_CLK_CTRL 0x08e3 |
| #define mmMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 1 |
| #define mmMMMC_SHARED_ACTIVE_FCN_ID 0x08e4 |
| #define mmMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 |
| #define mmMMMC_SHARED_VIRT_RESET_REQ2 0x08e5 |
| #define mmMMMC_SHARED_VIRT_RESET_REQ2_BASE_IDX 1 |
| #define mmMMUTCL2_CGTT_BUSY_CTRL 0x08e6 |
| #define mmMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 1 |
| #define mmMMUTCL2_HARVEST_BYPASS_GROUPS 0x08e7 |
| #define mmMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec |
| // base address: 0x6a3b0 |
| #define mmMMMC_VM_FB_LOCATION_BASE 0x08ec |
| #define mmMMMC_VM_FB_LOCATION_BASE_BASE_IDX 1 |
| #define mmMMMC_VM_FB_LOCATION_TOP 0x08ed |
| #define mmMMMC_VM_FB_LOCATION_TOP_BASE_IDX 1 |
| #define mmMMMC_VM_AGP_TOP 0x08ee |
| #define mmMMMC_VM_AGP_TOP_BASE_IDX 1 |
| #define mmMMMC_VM_AGP_BOT 0x08ef |
| #define mmMMMC_VM_AGP_BOT_BASE_IDX 1 |
| #define mmMMMC_VM_AGP_BASE 0x08f0 |
| #define mmMMMC_VM_AGP_BASE_BASE_IDX 1 |
| #define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x08f1 |
| #define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 |
| #define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08f2 |
| #define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 |
| #define mmMMMC_VM_MX_L1_TLB_CNTL 0x08f3 |
| #define mmMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec |
| // base address: 0x6a400 |
| #define mmMM_ATC_L2_PERFCOUNTER_LO 0x0900 |
| #define mmMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 |
| #define mmMM_ATC_L2_PERFCOUNTER_HI 0x0901 |
| #define mmMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec |
| // base address: 0x6a420 |
| #define mmMM_ATC_L2_PERFCOUNTER0_CFG 0x0908 |
| #define mmMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 |
| #define mmMM_ATC_L2_PERFCOUNTER1_CFG 0x0909 |
| #define mmMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 |
| #define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x090a |
| #define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mmvml2ptdec |
| // base address: 0x6a500 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0940 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0941 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0942 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0943 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0944 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0945 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE0 0x0946 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE1 0x0947 |
| #define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0948 |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0949 |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x094a |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x094b |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x094c |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x094d |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE0 0x094e |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE1 0x094f |
| #define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0950 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0951 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x0952 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0953 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0954 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0955 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE0 0x0956 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE1 0x0957 |
| #define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0958 |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0959 |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x095a |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x095b |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x095c |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x095d |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE0 0x095e |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE1 0x095f |
| #define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0960 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0961 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0962 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0963 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0964 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0965 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE0 0x0966 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE1 0x0967 |
| #define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0968 |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0969 |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x096a |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x096b |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x096c |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x096d |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE0 0x096e |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE1 0x096f |
| #define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0970 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0971 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0972 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0973 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0974 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0975 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE0 0x0976 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE1 0x0977 |
| #define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0978 |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x0979 |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x097a |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x097b |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x097c |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x097d |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE0 0x097e |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE1 0x097f |
| #define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0980 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0981 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0982 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0983 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0984 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0985 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE0 0x0986 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE1 0x0987 |
| #define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x0988 |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0989 |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x098a |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x098b |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x098c |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x098d |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE0 0x098e |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE1 0x098f |
| #define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x0990 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0991 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0992 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0993 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0994 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0995 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE0 0x0996 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE1 0x0997 |
| #define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0998 |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0999 |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x099a |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x099b |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x099c |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x099d |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE0 0x099e |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE1 0x099f |
| #define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x09a0 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x09a1 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x09a2 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x09a3 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x09a4 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x09a5 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE0 0x09a6 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE1 0x09a7 |
| #define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x09a8 |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x09a9 |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x09aa |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x09ab |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x09ac |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x09ad |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE0 0x09ae |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE1 0x09af |
| #define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x09b0 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x09b1 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x09b2 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x09b3 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x09b4 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x09b5 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE0 0x09b6 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE1 0x09b7 |
| #define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x09b8 |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x09b9 |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x09ba |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x09bb |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x09bc |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x09bd |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE0 0x09be |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE1 0x09bf |
| #define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE1_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mmvml2indec |
| // base address: 0x6a800 |
| #define mmMMVM_INVALIDATE_ENG0_SEM 0x0a00 |
| #define mmMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG0_REQ 0x0a01 |
| #define mmMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG0_ACK 0x0a02 |
| #define mmMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0a03 |
| #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0a04 |
| #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG0_RESERVE0 0x0a05 |
| #define mmMMVM_INVALIDATE_ENG0_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG0_RESERVE1 0x0a06 |
| #define mmMMVM_INVALIDATE_ENG0_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG0_RESERVE2 0x0a07 |
| #define mmMMVM_INVALIDATE_ENG0_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG1_SEM 0x0a08 |
| #define mmMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG1_REQ 0x0a09 |
| #define mmMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG1_ACK 0x0a0a |
| #define mmMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0a0b |
| #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x0a0c |
| #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG1_RESERVE0 0x0a0d |
| #define mmMMVM_INVALIDATE_ENG1_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG1_RESERVE1 0x0a0e |
| #define mmMMVM_INVALIDATE_ENG1_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG1_RESERVE2 0x0a0f |
| #define mmMMVM_INVALIDATE_ENG1_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG2_SEM 0x0a10 |
| #define mmMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG2_REQ 0x0a11 |
| #define mmMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG2_ACK 0x0a12 |
| #define mmMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x0a13 |
| #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x0a14 |
| #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG2_RESERVE0 0x0a15 |
| #define mmMMVM_INVALIDATE_ENG2_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG2_RESERVE1 0x0a16 |
| #define mmMMVM_INVALIDATE_ENG2_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG2_RESERVE2 0x0a17 |
| #define mmMMVM_INVALIDATE_ENG2_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG3_SEM 0x0a18 |
| #define mmMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG3_REQ 0x0a19 |
| #define mmMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG3_ACK 0x0a1a |
| #define mmMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x0a1b |
| #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x0a1c |
| #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG3_RESERVE0 0x0a1d |
| #define mmMMVM_INVALIDATE_ENG3_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG3_RESERVE1 0x0a1e |
| #define mmMMVM_INVALIDATE_ENG3_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG3_RESERVE2 0x0a1f |
| #define mmMMVM_INVALIDATE_ENG3_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG4_SEM 0x0a20 |
| #define mmMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG4_REQ 0x0a21 |
| #define mmMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG4_ACK 0x0a22 |
| #define mmMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x0a23 |
| #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0a24 |
| #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG4_RESERVE0 0x0a25 |
| #define mmMMVM_INVALIDATE_ENG4_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG4_RESERVE1 0x0a26 |
| #define mmMMVM_INVALIDATE_ENG4_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG4_RESERVE2 0x0a27 |
| #define mmMMVM_INVALIDATE_ENG4_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG5_SEM 0x0a28 |
| #define mmMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG5_REQ 0x0a29 |
| #define mmMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG5_ACK 0x0a2a |
| #define mmMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0a2b |
| #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0a2c |
| #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG5_RESERVE0 0x0a2d |
| #define mmMMVM_INVALIDATE_ENG5_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG5_RESERVE1 0x0a2e |
| #define mmMMVM_INVALIDATE_ENG5_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG5_RESERVE2 0x0a2f |
| #define mmMMVM_INVALIDATE_ENG5_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG6_SEM 0x0a30 |
| #define mmMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG6_REQ 0x0a31 |
| #define mmMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG6_ACK 0x0a32 |
| #define mmMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0a33 |
| #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0a34 |
| #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG6_RESERVE0 0x0a35 |
| #define mmMMVM_INVALIDATE_ENG6_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG6_RESERVE1 0x0a36 |
| #define mmMMVM_INVALIDATE_ENG6_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG6_RESERVE2 0x0a37 |
| #define mmMMVM_INVALIDATE_ENG6_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG7_SEM 0x0a38 |
| #define mmMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG7_REQ 0x0a39 |
| #define mmMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG7_ACK 0x0a3a |
| #define mmMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0a3b |
| #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0a3c |
| #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG7_RESERVE0 0x0a3d |
| #define mmMMVM_INVALIDATE_ENG7_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG7_RESERVE1 0x0a3e |
| #define mmMMVM_INVALIDATE_ENG7_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG7_RESERVE2 0x0a3f |
| #define mmMMVM_INVALIDATE_ENG7_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG8_SEM 0x0a40 |
| #define mmMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG8_REQ 0x0a41 |
| #define mmMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG8_ACK 0x0a42 |
| #define mmMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0a43 |
| #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0a44 |
| #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG8_RESERVE0 0x0a45 |
| #define mmMMVM_INVALIDATE_ENG8_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG8_RESERVE1 0x0a46 |
| #define mmMMVM_INVALIDATE_ENG8_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG8_RESERVE2 0x0a47 |
| #define mmMMVM_INVALIDATE_ENG8_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG9_SEM 0x0a48 |
| #define mmMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG9_REQ 0x0a49 |
| #define mmMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG9_ACK 0x0a4a |
| #define mmMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0a4b |
| #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x0a4c |
| #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG9_RESERVE0 0x0a4d |
| #define mmMMVM_INVALIDATE_ENG9_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG9_RESERVE1 0x0a4e |
| #define mmMMVM_INVALIDATE_ENG9_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG9_RESERVE2 0x0a4f |
| #define mmMMVM_INVALIDATE_ENG9_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG10_SEM 0x0a50 |
| #define mmMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG10_REQ 0x0a51 |
| #define mmMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG10_ACK 0x0a52 |
| #define mmMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x0a53 |
| #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x0a54 |
| #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG10_RESERVE0 0x0a55 |
| #define mmMMVM_INVALIDATE_ENG10_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG10_RESERVE1 0x0a56 |
| #define mmMMVM_INVALIDATE_ENG10_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG10_RESERVE2 0x0a57 |
| #define mmMMVM_INVALIDATE_ENG10_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG11_SEM 0x0a58 |
| #define mmMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG11_REQ 0x0a59 |
| #define mmMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG11_ACK 0x0a5a |
| #define mmMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x0a5b |
| #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x0a5c |
| #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG11_RESERVE0 0x0a5d |
| #define mmMMVM_INVALIDATE_ENG11_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG11_RESERVE1 0x0a5e |
| #define mmMMVM_INVALIDATE_ENG11_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG11_RESERVE2 0x0a5f |
| #define mmMMVM_INVALIDATE_ENG11_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG12_SEM 0x0a60 |
| #define mmMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG12_REQ 0x0a61 |
| #define mmMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG12_ACK 0x0a62 |
| #define mmMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x0a63 |
| #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0a64 |
| #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG12_RESERVE0 0x0a65 |
| #define mmMMVM_INVALIDATE_ENG12_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG12_RESERVE1 0x0a66 |
| #define mmMMVM_INVALIDATE_ENG12_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG12_RESERVE2 0x0a67 |
| #define mmMMVM_INVALIDATE_ENG12_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG13_SEM 0x0a68 |
| #define mmMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG13_REQ 0x0a69 |
| #define mmMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG13_ACK 0x0a6a |
| #define mmMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0a6b |
| #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0a6c |
| #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG13_RESERVE0 0x0a6d |
| #define mmMMVM_INVALIDATE_ENG13_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG13_RESERVE1 0x0a6e |
| #define mmMMVM_INVALIDATE_ENG13_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG13_RESERVE2 0x0a6f |
| #define mmMMVM_INVALIDATE_ENG13_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG14_SEM 0x0a70 |
| #define mmMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG14_REQ 0x0a71 |
| #define mmMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG14_ACK 0x0a72 |
| #define mmMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0a73 |
| #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0a74 |
| #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG14_RESERVE0 0x0a75 |
| #define mmMMVM_INVALIDATE_ENG14_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG14_RESERVE1 0x0a76 |
| #define mmMMVM_INVALIDATE_ENG14_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG14_RESERVE2 0x0a77 |
| #define mmMMVM_INVALIDATE_ENG14_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG15_SEM 0x0a78 |
| #define mmMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG15_REQ 0x0a79 |
| #define mmMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG15_ACK 0x0a7a |
| #define mmMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0a7b |
| #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0a7c |
| #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG15_RESERVE0 0x0a7d |
| #define mmMMVM_INVALIDATE_ENG15_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG15_RESERVE1 0x0a7e |
| #define mmMMVM_INVALIDATE_ENG15_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG15_RESERVE2 0x0a7f |
| #define mmMMVM_INVALIDATE_ENG15_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG16_SEM 0x0a80 |
| #define mmMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG16_REQ 0x0a81 |
| #define mmMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG16_ACK 0x0a82 |
| #define mmMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0a83 |
| #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0a84 |
| #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG16_RESERVE0 0x0a85 |
| #define mmMMVM_INVALIDATE_ENG16_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG16_RESERVE1 0x0a86 |
| #define mmMMVM_INVALIDATE_ENG16_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG16_RESERVE2 0x0a87 |
| #define mmMMVM_INVALIDATE_ENG16_RESERVE2_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG17_SEM 0x0a88 |
| #define mmMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG17_REQ 0x0a89 |
| #define mmMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG17_ACK 0x0a8a |
| #define mmMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0a8b |
| #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x0a8c |
| #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG17_RESERVE0 0x0a8d |
| #define mmMMVM_INVALIDATE_ENG17_RESERVE0_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG17_RESERVE1 0x0a8e |
| #define mmMMVM_INVALIDATE_ENG17_RESERVE1_BASE_IDX 1 |
| #define mmMMVM_INVALIDATE_ENG17_RESERVE2 0x0a8f |
| #define mmMMVM_INVALIDATE_ENG17_RESERVE2_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mml2tlbpfdec |
| // base address: 0x6aa90 |
| #define mmMML2TLB_TLB0_STATUS 0x0aa5 |
| #define mmMML2TLB_TLB0_STATUS_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mml2tlbpldec |
| // base address: 0x6ab00 |
| #define mmMML2TLB_PERFCOUNTER0_CFG 0x0ac0 |
| #define mmMML2TLB_PERFCOUNTER0_CFG_BASE_IDX 1 |
| #define mmMML2TLB_PERFCOUNTER1_CFG 0x0ac1 |
| #define mmMML2TLB_PERFCOUNTER1_CFG_BASE_IDX 1 |
| #define mmMML2TLB_PERFCOUNTER2_CFG 0x0ac2 |
| #define mmMML2TLB_PERFCOUNTER2_CFG_BASE_IDX 1 |
| #define mmMML2TLB_PERFCOUNTER3_CFG 0x0ac3 |
| #define mmMML2TLB_PERFCOUNTER3_CFG_BASE_IDX 1 |
| #define mmMML2TLB_PERFCOUNTER_RSLT_CNTL 0x0ac4 |
| #define mmMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
| |
| |
| // addressBlock: mmhub_mmutcl2_mml2tlbprdec |
| // base address: 0x6ab20 |
| #define mmMML2TLB_PERFCOUNTER_LO 0x0ac8 |
| #define mmMML2TLB_PERFCOUNTER_LO_BASE_IDX 1 |
| #define mmMML2TLB_PERFCOUNTER_HI 0x0ac9 |
| #define mmMML2TLB_PERFCOUNTER_HI_BASE_IDX 1 |
| |
| #endif |
