blob: d8632ccf349442be1d809a41c02a5362ab7a9d17 [file] [log] [blame]
/*
* Copyright (C) 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _mmhub_9_4_1_OFFSET_HEADER
#define _mmhub_9_4_1_OFFSET_HEADER
// addressBlock: mmhub_dagb_dagbdec0
// base address: 0x68000
#define mmDAGB0_RDCLI0 0x0000
#define mmDAGB0_RDCLI0_BASE_IDX 1
#define mmDAGB0_RDCLI1 0x0001
#define mmDAGB0_RDCLI1_BASE_IDX 1
#define mmDAGB0_RDCLI2 0x0002
#define mmDAGB0_RDCLI2_BASE_IDX 1
#define mmDAGB0_RDCLI3 0x0003
#define mmDAGB0_RDCLI3_BASE_IDX 1
#define mmDAGB0_RDCLI4 0x0004
#define mmDAGB0_RDCLI4_BASE_IDX 1
#define mmDAGB0_RDCLI5 0x0005
#define mmDAGB0_RDCLI5_BASE_IDX 1
#define mmDAGB0_RDCLI6 0x0006
#define mmDAGB0_RDCLI6_BASE_IDX 1
#define mmDAGB0_RDCLI7 0x0007
#define mmDAGB0_RDCLI7_BASE_IDX 1
#define mmDAGB0_RDCLI8 0x0008
#define mmDAGB0_RDCLI8_BASE_IDX 1
#define mmDAGB0_RDCLI9 0x0009
#define mmDAGB0_RDCLI9_BASE_IDX 1
#define mmDAGB0_RDCLI10 0x000a
#define mmDAGB0_RDCLI10_BASE_IDX 1
#define mmDAGB0_RDCLI11 0x000b
#define mmDAGB0_RDCLI11_BASE_IDX 1
#define mmDAGB0_RDCLI12 0x000c
#define mmDAGB0_RDCLI12_BASE_IDX 1
#define mmDAGB0_RDCLI13 0x000d
#define mmDAGB0_RDCLI13_BASE_IDX 1
#define mmDAGB0_RDCLI14 0x000e
#define mmDAGB0_RDCLI14_BASE_IDX 1
#define mmDAGB0_RDCLI15 0x000f
#define mmDAGB0_RDCLI15_BASE_IDX 1
#define mmDAGB0_RD_CNTL 0x0010
#define mmDAGB0_RD_CNTL_BASE_IDX 1
#define mmDAGB0_RD_GMI_CNTL 0x0011
#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 1
#define mmDAGB0_RD_ADDR_DAGB 0x0012
#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 1
#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013
#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014
#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0015
#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016
#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017
#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB0_RD_VC0_CNTL 0x001c
#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 1
#define mmDAGB0_RD_VC1_CNTL 0x001d
#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 1
#define mmDAGB0_RD_VC2_CNTL 0x001e
#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 1
#define mmDAGB0_RD_VC3_CNTL 0x001f
#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 1
#define mmDAGB0_RD_VC4_CNTL 0x0020
#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 1
#define mmDAGB0_RD_VC5_CNTL 0x0021
#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 1
#define mmDAGB0_RD_VC6_CNTL 0x0022
#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 1
#define mmDAGB0_RD_VC7_CNTL 0x0023
#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 1
#define mmDAGB0_RD_CNTL_MISC 0x0024
#define mmDAGB0_RD_CNTL_MISC_BASE_IDX 1
#define mmDAGB0_RD_TLB_CREDIT 0x0025
#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 1
#define mmDAGB0_RDCLI_ASK_PENDING 0x0026
#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1
#define mmDAGB0_RDCLI_GO_PENDING 0x0027
#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 1
#define mmDAGB0_RDCLI_GBLSEND_PENDING 0x0028
#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1
#define mmDAGB0_RDCLI_TLB_PENDING 0x0029
#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1
#define mmDAGB0_RDCLI_OARB_PENDING 0x002a
#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1
#define mmDAGB0_RDCLI_OSD_PENDING 0x002b
#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1
#define mmDAGB0_WRCLI0 0x002c
#define mmDAGB0_WRCLI0_BASE_IDX 1
#define mmDAGB0_WRCLI1 0x002d
#define mmDAGB0_WRCLI1_BASE_IDX 1
#define mmDAGB0_WRCLI2 0x002e
#define mmDAGB0_WRCLI2_BASE_IDX 1
#define mmDAGB0_WRCLI3 0x002f
#define mmDAGB0_WRCLI3_BASE_IDX 1
#define mmDAGB0_WRCLI4 0x0030
#define mmDAGB0_WRCLI4_BASE_IDX 1
#define mmDAGB0_WRCLI5 0x0031
#define mmDAGB0_WRCLI5_BASE_IDX 1
#define mmDAGB0_WRCLI6 0x0032
#define mmDAGB0_WRCLI6_BASE_IDX 1
#define mmDAGB0_WRCLI7 0x0033
#define mmDAGB0_WRCLI7_BASE_IDX 1
#define mmDAGB0_WRCLI8 0x0034
#define mmDAGB0_WRCLI8_BASE_IDX 1
#define mmDAGB0_WRCLI9 0x0035
#define mmDAGB0_WRCLI9_BASE_IDX 1
#define mmDAGB0_WRCLI10 0x0036
#define mmDAGB0_WRCLI10_BASE_IDX 1
#define mmDAGB0_WRCLI11 0x0037
#define mmDAGB0_WRCLI11_BASE_IDX 1
#define mmDAGB0_WRCLI12 0x0038
#define mmDAGB0_WRCLI12_BASE_IDX 1
#define mmDAGB0_WRCLI13 0x0039
#define mmDAGB0_WRCLI13_BASE_IDX 1
#define mmDAGB0_WRCLI14 0x003a
#define mmDAGB0_WRCLI14_BASE_IDX 1
#define mmDAGB0_WRCLI15 0x003b
#define mmDAGB0_WRCLI15_BASE_IDX 1
#define mmDAGB0_WR_CNTL 0x003c
#define mmDAGB0_WR_CNTL_BASE_IDX 1
#define mmDAGB0_WR_GMI_CNTL 0x003d
#define mmDAGB0_WR_GMI_CNTL_BASE_IDX 1
#define mmDAGB0_WR_ADDR_DAGB 0x003e
#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 1
#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x003f
#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0040
#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
#define mmDAGB0_WR_CGTT_CLK_CTRL 0x0041
#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0042
#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0043
#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0044
#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0045
#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0046
#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0047
#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB0_WR_DATA_DAGB 0x0048
#define mmDAGB0_WR_DATA_DAGB_BASE_IDX 1
#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0049
#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004a
#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004b
#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004c
#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB0_WR_VC0_CNTL 0x004d
#define mmDAGB0_WR_VC0_CNTL_BASE_IDX 1
#define mmDAGB0_WR_VC1_CNTL 0x004e
#define mmDAGB0_WR_VC1_CNTL_BASE_IDX 1
#define mmDAGB0_WR_VC2_CNTL 0x004f
#define mmDAGB0_WR_VC2_CNTL_BASE_IDX 1
#define mmDAGB0_WR_VC3_CNTL 0x0050
#define mmDAGB0_WR_VC3_CNTL_BASE_IDX 1
#define mmDAGB0_WR_VC4_CNTL 0x0051
#define mmDAGB0_WR_VC4_CNTL_BASE_IDX 1
#define mmDAGB0_WR_VC5_CNTL 0x0052
#define mmDAGB0_WR_VC5_CNTL_BASE_IDX 1
#define mmDAGB0_WR_VC6_CNTL 0x0053
#define mmDAGB0_WR_VC6_CNTL_BASE_IDX 1
#define mmDAGB0_WR_VC7_CNTL 0x0054
#define mmDAGB0_WR_VC7_CNTL_BASE_IDX 1
#define mmDAGB0_WR_CNTL_MISC 0x0055
#define mmDAGB0_WR_CNTL_MISC_BASE_IDX 1
#define mmDAGB0_WR_TLB_CREDIT 0x0056
#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 1
#define mmDAGB0_WR_DATA_CREDIT 0x0057
#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 1
#define mmDAGB0_WR_MISC_CREDIT 0x0058
#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 1
#define mmDAGB0_WRCLI_ASK_PENDING 0x005d
#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1
#define mmDAGB0_WRCLI_GO_PENDING 0x005e
#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 1
#define mmDAGB0_WRCLI_GBLSEND_PENDING 0x005f
#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1
#define mmDAGB0_WRCLI_TLB_PENDING 0x0060
#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1
#define mmDAGB0_WRCLI_OARB_PENDING 0x0061
#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1
#define mmDAGB0_WRCLI_OSD_PENDING 0x0062
#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1
#define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x0063
#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
#define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0064
#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
#define mmDAGB0_DAGB_DLY 0x0065
#define mmDAGB0_DAGB_DLY_BASE_IDX 1
#define mmDAGB0_CNTL_MISC 0x0066
#define mmDAGB0_CNTL_MISC_BASE_IDX 1
#define mmDAGB0_CNTL_MISC2 0x0067
#define mmDAGB0_CNTL_MISC2_BASE_IDX 1
#define mmDAGB0_FIFO_EMPTY 0x0068
#define mmDAGB0_FIFO_EMPTY_BASE_IDX 1
#define mmDAGB0_FIFO_FULL 0x0069
#define mmDAGB0_FIFO_FULL_BASE_IDX 1
#define mmDAGB0_WR_CREDITS_FULL 0x006a
#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 1
#define mmDAGB0_RD_CREDITS_FULL 0x006b
#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 1
#define mmDAGB0_PERFCOUNTER_LO 0x006c
#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 1
#define mmDAGB0_PERFCOUNTER_HI 0x006d
#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 1
#define mmDAGB0_PERFCOUNTER0_CFG 0x006e
#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1
#define mmDAGB0_PERFCOUNTER1_CFG 0x006f
#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1
#define mmDAGB0_PERFCOUNTER2_CFG 0x0070
#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1
#define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x0071
#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
#define mmDAGB0_RESERVE0 0x0072
#define mmDAGB0_RESERVE0_BASE_IDX 1
#define mmDAGB0_RESERVE1 0x0073
#define mmDAGB0_RESERVE1_BASE_IDX 1
#define mmDAGB0_RESERVE2 0x0074
#define mmDAGB0_RESERVE2_BASE_IDX 1
#define mmDAGB0_RESERVE3 0x0075
#define mmDAGB0_RESERVE3_BASE_IDX 1
#define mmDAGB0_RESERVE4 0x0076
#define mmDAGB0_RESERVE4_BASE_IDX 1
#define mmDAGB0_RESERVE5 0x0077
#define mmDAGB0_RESERVE5_BASE_IDX 1
#define mmDAGB0_RESERVE6 0x0078
#define mmDAGB0_RESERVE6_BASE_IDX 1
#define mmDAGB0_RESERVE7 0x0079
#define mmDAGB0_RESERVE7_BASE_IDX 1
#define mmDAGB0_RESERVE8 0x007a
#define mmDAGB0_RESERVE8_BASE_IDX 1
#define mmDAGB0_RESERVE9 0x007b
#define mmDAGB0_RESERVE9_BASE_IDX 1
#define mmDAGB0_RESERVE10 0x007c
#define mmDAGB0_RESERVE10_BASE_IDX 1
#define mmDAGB0_RESERVE11 0x007d
#define mmDAGB0_RESERVE11_BASE_IDX 1
#define mmDAGB0_RESERVE12 0x007e
#define mmDAGB0_RESERVE12_BASE_IDX 1
#define mmDAGB0_RESERVE13 0x007f
#define mmDAGB0_RESERVE13_BASE_IDX 1
// addressBlock: mmhub_dagb_dagbdec1
// base address: 0x68200
#define mmDAGB1_RDCLI0 0x0080
#define mmDAGB1_RDCLI0_BASE_IDX 1
#define mmDAGB1_RDCLI1 0x0081
#define mmDAGB1_RDCLI1_BASE_IDX 1
#define mmDAGB1_RDCLI2 0x0082
#define mmDAGB1_RDCLI2_BASE_IDX 1
#define mmDAGB1_RDCLI3 0x0083
#define mmDAGB1_RDCLI3_BASE_IDX 1
#define mmDAGB1_RDCLI4 0x0084
#define mmDAGB1_RDCLI4_BASE_IDX 1
#define mmDAGB1_RDCLI5 0x0085
#define mmDAGB1_RDCLI5_BASE_IDX 1
#define mmDAGB1_RDCLI6 0x0086
#define mmDAGB1_RDCLI6_BASE_IDX 1
#define mmDAGB1_RDCLI7 0x0087
#define mmDAGB1_RDCLI7_BASE_IDX 1
#define mmDAGB1_RDCLI8 0x0088
#define mmDAGB1_RDCLI8_BASE_IDX 1
#define mmDAGB1_RDCLI9 0x0089
#define mmDAGB1_RDCLI9_BASE_IDX 1
#define mmDAGB1_RDCLI10 0x008a
#define mmDAGB1_RDCLI10_BASE_IDX 1
#define mmDAGB1_RDCLI11 0x008b
#define mmDAGB1_RDCLI11_BASE_IDX 1
#define mmDAGB1_RDCLI12 0x008c
#define mmDAGB1_RDCLI12_BASE_IDX 1
#define mmDAGB1_RDCLI13 0x008d
#define mmDAGB1_RDCLI13_BASE_IDX 1
#define mmDAGB1_RDCLI14 0x008e
#define mmDAGB1_RDCLI14_BASE_IDX 1
#define mmDAGB1_RDCLI15 0x008f
#define mmDAGB1_RDCLI15_BASE_IDX 1
#define mmDAGB1_RD_CNTL 0x0090
#define mmDAGB1_RD_CNTL_BASE_IDX 1
#define mmDAGB1_RD_GMI_CNTL 0x0091
#define mmDAGB1_RD_GMI_CNTL_BASE_IDX 1
#define mmDAGB1_RD_ADDR_DAGB 0x0092
#define mmDAGB1_RD_ADDR_DAGB_BASE_IDX 1
#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093
#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094
#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
#define mmDAGB1_RD_CGTT_CLK_CTRL 0x0095
#define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096
#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097
#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098
#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099
#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a
#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b
#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB1_RD_VC0_CNTL 0x009c
#define mmDAGB1_RD_VC0_CNTL_BASE_IDX 1
#define mmDAGB1_RD_VC1_CNTL 0x009d
#define mmDAGB1_RD_VC1_CNTL_BASE_IDX 1
#define mmDAGB1_RD_VC2_CNTL 0x009e
#define mmDAGB1_RD_VC2_CNTL_BASE_IDX 1
#define mmDAGB1_RD_VC3_CNTL 0x009f
#define mmDAGB1_RD_VC3_CNTL_BASE_IDX 1
#define mmDAGB1_RD_VC4_CNTL 0x00a0
#define mmDAGB1_RD_VC4_CNTL_BASE_IDX 1
#define mmDAGB1_RD_VC5_CNTL 0x00a1
#define mmDAGB1_RD_VC5_CNTL_BASE_IDX 1
#define mmDAGB1_RD_VC6_CNTL 0x00a2
#define mmDAGB1_RD_VC6_CNTL_BASE_IDX 1
#define mmDAGB1_RD_VC7_CNTL 0x00a3
#define mmDAGB1_RD_VC7_CNTL_BASE_IDX 1
#define mmDAGB1_RD_CNTL_MISC 0x00a4
#define mmDAGB1_RD_CNTL_MISC_BASE_IDX 1
#define mmDAGB1_RD_TLB_CREDIT 0x00a5
#define mmDAGB1_RD_TLB_CREDIT_BASE_IDX 1
#define mmDAGB1_RDCLI_ASK_PENDING 0x00a6
#define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX 1
#define mmDAGB1_RDCLI_GO_PENDING 0x00a7
#define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX 1
#define mmDAGB1_RDCLI_GBLSEND_PENDING 0x00a8
#define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 1
#define mmDAGB1_RDCLI_TLB_PENDING 0x00a9
#define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX 1
#define mmDAGB1_RDCLI_OARB_PENDING 0x00aa
#define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX 1
#define mmDAGB1_RDCLI_OSD_PENDING 0x00ab
#define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX 1
#define mmDAGB1_WRCLI0 0x00ac
#define mmDAGB1_WRCLI0_BASE_IDX 1
#define mmDAGB1_WRCLI1 0x00ad
#define mmDAGB1_WRCLI1_BASE_IDX 1
#define mmDAGB1_WRCLI2 0x00ae
#define mmDAGB1_WRCLI2_BASE_IDX 1
#define mmDAGB1_WRCLI3 0x00af
#define mmDAGB1_WRCLI3_BASE_IDX 1
#define mmDAGB1_WRCLI4 0x00b0
#define mmDAGB1_WRCLI4_BASE_IDX 1
#define mmDAGB1_WRCLI5 0x00b1
#define mmDAGB1_WRCLI5_BASE_IDX 1
#define mmDAGB1_WRCLI6 0x00b2
#define mmDAGB1_WRCLI6_BASE_IDX 1
#define mmDAGB1_WRCLI7 0x00b3
#define mmDAGB1_WRCLI7_BASE_IDX 1
#define mmDAGB1_WRCLI8 0x00b4
#define mmDAGB1_WRCLI8_BASE_IDX 1
#define mmDAGB1_WRCLI9 0x00b5
#define mmDAGB1_WRCLI9_BASE_IDX 1
#define mmDAGB1_WRCLI10 0x00b6
#define mmDAGB1_WRCLI10_BASE_IDX 1
#define mmDAGB1_WRCLI11 0x00b7
#define mmDAGB1_WRCLI11_BASE_IDX 1
#define mmDAGB1_WRCLI12 0x00b8
#define mmDAGB1_WRCLI12_BASE_IDX 1
#define mmDAGB1_WRCLI13 0x00b9
#define mmDAGB1_WRCLI13_BASE_IDX 1
#define mmDAGB1_WRCLI14 0x00ba
#define mmDAGB1_WRCLI14_BASE_IDX 1
#define mmDAGB1_WRCLI15 0x00bb
#define mmDAGB1_WRCLI15_BASE_IDX 1
#define mmDAGB1_WR_CNTL 0x00bc
#define mmDAGB1_WR_CNTL_BASE_IDX 1
#define mmDAGB1_WR_GMI_CNTL 0x00bd
#define mmDAGB1_WR_GMI_CNTL_BASE_IDX 1
#define mmDAGB1_WR_ADDR_DAGB 0x00be
#define mmDAGB1_WR_ADDR_DAGB_BASE_IDX 1
#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00bf
#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c0
#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
#define mmDAGB1_WR_CGTT_CLK_CTRL 0x00c1
#define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c2
#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c3
#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c4
#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c5
#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c6
#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c7
#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB1_WR_DATA_DAGB 0x00c8
#define mmDAGB1_WR_DATA_DAGB_BASE_IDX 1
#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00c9
#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00ca
#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cb
#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00cc
#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB1_WR_VC0_CNTL 0x00cd
#define mmDAGB1_WR_VC0_CNTL_BASE_IDX 1
#define mmDAGB1_WR_VC1_CNTL 0x00ce
#define mmDAGB1_WR_VC1_CNTL_BASE_IDX 1
#define mmDAGB1_WR_VC2_CNTL 0x00cf
#define mmDAGB1_WR_VC2_CNTL_BASE_IDX 1
#define mmDAGB1_WR_VC3_CNTL 0x00d0
#define mmDAGB1_WR_VC3_CNTL_BASE_IDX 1
#define mmDAGB1_WR_VC4_CNTL 0x00d1
#define mmDAGB1_WR_VC4_CNTL_BASE_IDX 1
#define mmDAGB1_WR_VC5_CNTL 0x00d2
#define mmDAGB1_WR_VC5_CNTL_BASE_IDX 1
#define mmDAGB1_WR_VC6_CNTL 0x00d3
#define mmDAGB1_WR_VC6_CNTL_BASE_IDX 1
#define mmDAGB1_WR_VC7_CNTL 0x00d4
#define mmDAGB1_WR_VC7_CNTL_BASE_IDX 1
#define mmDAGB1_WR_CNTL_MISC 0x00d5
#define mmDAGB1_WR_CNTL_MISC_BASE_IDX 1
#define mmDAGB1_WR_TLB_CREDIT 0x00d6
#define mmDAGB1_WR_TLB_CREDIT_BASE_IDX 1
#define mmDAGB1_WR_DATA_CREDIT 0x00d7
#define mmDAGB1_WR_DATA_CREDIT_BASE_IDX 1
#define mmDAGB1_WR_MISC_CREDIT 0x00d8
#define mmDAGB1_WR_MISC_CREDIT_BASE_IDX 1
#define mmDAGB1_WRCLI_ASK_PENDING 0x00dd
#define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX 1
#define mmDAGB1_WRCLI_GO_PENDING 0x00de
#define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX 1
#define mmDAGB1_WRCLI_GBLSEND_PENDING 0x00df
#define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 1
#define mmDAGB1_WRCLI_TLB_PENDING 0x00e0
#define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX 1
#define mmDAGB1_WRCLI_OARB_PENDING 0x00e1
#define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX 1
#define mmDAGB1_WRCLI_OSD_PENDING 0x00e2
#define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX 1
#define mmDAGB1_WRCLI_DBUS_ASK_PENDING 0x00e3
#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
#define mmDAGB1_WRCLI_DBUS_GO_PENDING 0x00e4
#define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
#define mmDAGB1_DAGB_DLY 0x00e5
#define mmDAGB1_DAGB_DLY_BASE_IDX 1
#define mmDAGB1_CNTL_MISC 0x00e6
#define mmDAGB1_CNTL_MISC_BASE_IDX 1
#define mmDAGB1_CNTL_MISC2 0x00e7
#define mmDAGB1_CNTL_MISC2_BASE_IDX 1
#define mmDAGB1_FIFO_EMPTY 0x00e8
#define mmDAGB1_FIFO_EMPTY_BASE_IDX 1
#define mmDAGB1_FIFO_FULL 0x00e9
#define mmDAGB1_FIFO_FULL_BASE_IDX 1
#define mmDAGB1_WR_CREDITS_FULL 0x00ea
#define mmDAGB1_WR_CREDITS_FULL_BASE_IDX 1
#define mmDAGB1_RD_CREDITS_FULL 0x00eb
#define mmDAGB1_RD_CREDITS_FULL_BASE_IDX 1
#define mmDAGB1_PERFCOUNTER_LO 0x00ec
#define mmDAGB1_PERFCOUNTER_LO_BASE_IDX 1
#define mmDAGB1_PERFCOUNTER_HI 0x00ed
#define mmDAGB1_PERFCOUNTER_HI_BASE_IDX 1
#define mmDAGB1_PERFCOUNTER0_CFG 0x00ee
#define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX 1
#define mmDAGB1_PERFCOUNTER1_CFG 0x00ef
#define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX 1
#define mmDAGB1_PERFCOUNTER2_CFG 0x00f0
#define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX 1
#define mmDAGB1_PERFCOUNTER_RSLT_CNTL 0x00f1
#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
#define mmDAGB1_RESERVE0 0x00f2
#define mmDAGB1_RESERVE0_BASE_IDX 1
#define mmDAGB1_RESERVE1 0x00f3
#define mmDAGB1_RESERVE1_BASE_IDX 1
#define mmDAGB1_RESERVE2 0x00f4
#define mmDAGB1_RESERVE2_BASE_IDX 1
#define mmDAGB1_RESERVE3 0x00f5
#define mmDAGB1_RESERVE3_BASE_IDX 1
#define mmDAGB1_RESERVE4 0x00f6
#define mmDAGB1_RESERVE4_BASE_IDX 1
#define mmDAGB1_RESERVE5 0x00f7
#define mmDAGB1_RESERVE5_BASE_IDX 1
#define mmDAGB1_RESERVE6 0x00f8
#define mmDAGB1_RESERVE6_BASE_IDX 1
#define mmDAGB1_RESERVE7 0x00f9
#define mmDAGB1_RESERVE7_BASE_IDX 1
#define mmDAGB1_RESERVE8 0x00fa
#define mmDAGB1_RESERVE8_BASE_IDX 1
#define mmDAGB1_RESERVE9 0x00fb
#define mmDAGB1_RESERVE9_BASE_IDX 1
#define mmDAGB1_RESERVE10 0x00fc
#define mmDAGB1_RESERVE10_BASE_IDX 1
#define mmDAGB1_RESERVE11 0x00fd
#define mmDAGB1_RESERVE11_BASE_IDX 1
#define mmDAGB1_RESERVE12 0x00fe
#define mmDAGB1_RESERVE12_BASE_IDX 1
#define mmDAGB1_RESERVE13 0x00ff
#define mmDAGB1_RESERVE13_BASE_IDX 1
// addressBlock: mmhub_dagb_dagbdec2
// base address: 0x68400
#define mmDAGB2_RDCLI0 0x0100
#define mmDAGB2_RDCLI0_BASE_IDX 1
#define mmDAGB2_RDCLI1 0x0101
#define mmDAGB2_RDCLI1_BASE_IDX 1
#define mmDAGB2_RDCLI2 0x0102
#define mmDAGB2_RDCLI2_BASE_IDX 1
#define mmDAGB2_RDCLI3 0x0103
#define mmDAGB2_RDCLI3_BASE_IDX 1
#define mmDAGB2_RDCLI4 0x0104
#define mmDAGB2_RDCLI4_BASE_IDX 1
#define mmDAGB2_RDCLI5 0x0105
#define mmDAGB2_RDCLI5_BASE_IDX 1
#define mmDAGB2_RDCLI6 0x0106
#define mmDAGB2_RDCLI6_BASE_IDX 1
#define mmDAGB2_RDCLI7 0x0107
#define mmDAGB2_RDCLI7_BASE_IDX 1
#define mmDAGB2_RDCLI8 0x0108
#define mmDAGB2_RDCLI8_BASE_IDX 1
#define mmDAGB2_RDCLI9 0x0109
#define mmDAGB2_RDCLI9_BASE_IDX 1
#define mmDAGB2_RDCLI10 0x010a
#define mmDAGB2_RDCLI10_BASE_IDX 1
#define mmDAGB2_RDCLI11 0x010b
#define mmDAGB2_RDCLI11_BASE_IDX 1
#define mmDAGB2_RDCLI12 0x010c
#define mmDAGB2_RDCLI12_BASE_IDX 1
#define mmDAGB2_RDCLI13 0x010d
#define mmDAGB2_RDCLI13_BASE_IDX 1
#define mmDAGB2_RDCLI14 0x010e
#define mmDAGB2_RDCLI14_BASE_IDX 1
#define mmDAGB2_RDCLI15 0x010f
#define mmDAGB2_RDCLI15_BASE_IDX 1
#define mmDAGB2_RD_CNTL 0x0110
#define mmDAGB2_RD_CNTL_BASE_IDX 1
#define mmDAGB2_RD_GMI_CNTL 0x0111
#define mmDAGB2_RD_GMI_CNTL_BASE_IDX 1
#define mmDAGB2_RD_ADDR_DAGB 0x0112
#define mmDAGB2_RD_ADDR_DAGB_BASE_IDX 1
#define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0x0113
#define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
#define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0x0114
#define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
#define mmDAGB2_RD_CGTT_CLK_CTRL 0x0115
#define mmDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0x0116
#define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0x0117
#define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0 0x0118
#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0x0119
#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1 0x011a
#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0x011b
#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB2_RD_VC0_CNTL 0x011c
#define mmDAGB2_RD_VC0_CNTL_BASE_IDX 1
#define mmDAGB2_RD_VC1_CNTL 0x011d
#define mmDAGB2_RD_VC1_CNTL_BASE_IDX 1
#define mmDAGB2_RD_VC2_CNTL 0x011e
#define mmDAGB2_RD_VC2_CNTL_BASE_IDX 1
#define mmDAGB2_RD_VC3_CNTL 0x011f
#define mmDAGB2_RD_VC3_CNTL_BASE_IDX 1
#define mmDAGB2_RD_VC4_CNTL 0x0120
#define mmDAGB2_RD_VC4_CNTL_BASE_IDX 1
#define mmDAGB2_RD_VC5_CNTL 0x0121
#define mmDAGB2_RD_VC5_CNTL_BASE_IDX 1
#define mmDAGB2_RD_VC6_CNTL 0x0122
#define mmDAGB2_RD_VC6_CNTL_BASE_IDX 1
#define mmDAGB2_RD_VC7_CNTL 0x0123
#define mmDAGB2_RD_VC7_CNTL_BASE_IDX 1
#define mmDAGB2_RD_CNTL_MISC 0x0124
#define mmDAGB2_RD_CNTL_MISC_BASE_IDX 1
#define mmDAGB2_RD_TLB_CREDIT 0x0125
#define mmDAGB2_RD_TLB_CREDIT_BASE_IDX 1
#define mmDAGB2_RDCLI_ASK_PENDING 0x0126
#define mmDAGB2_RDCLI_ASK_PENDING_BASE_IDX 1
#define mmDAGB2_RDCLI_GO_PENDING 0x0127
#define mmDAGB2_RDCLI_GO_PENDING_BASE_IDX 1
#define mmDAGB2_RDCLI_GBLSEND_PENDING 0x0128
#define mmDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX 1
#define mmDAGB2_RDCLI_TLB_PENDING 0x0129
#define mmDAGB2_RDCLI_TLB_PENDING_BASE_IDX 1
#define mmDAGB2_RDCLI_OARB_PENDING 0x012a
#define mmDAGB2_RDCLI_OARB_PENDING_BASE_IDX 1
#define mmDAGB2_RDCLI_OSD_PENDING 0x012b
#define mmDAGB2_RDCLI_OSD_PENDING_BASE_IDX 1
#define mmDAGB2_WRCLI0 0x012c
#define mmDAGB2_WRCLI0_BASE_IDX 1
#define mmDAGB2_WRCLI1 0x012d
#define mmDAGB2_WRCLI1_BASE_IDX 1
#define mmDAGB2_WRCLI2 0x012e
#define mmDAGB2_WRCLI2_BASE_IDX 1
#define mmDAGB2_WRCLI3 0x012f
#define mmDAGB2_WRCLI3_BASE_IDX 1
#define mmDAGB2_WRCLI4 0x0130
#define mmDAGB2_WRCLI4_BASE_IDX 1
#define mmDAGB2_WRCLI5 0x0131
#define mmDAGB2_WRCLI5_BASE_IDX 1
#define mmDAGB2_WRCLI6 0x0132
#define mmDAGB2_WRCLI6_BASE_IDX 1
#define mmDAGB2_WRCLI7 0x0133
#define mmDAGB2_WRCLI7_BASE_IDX 1
#define mmDAGB2_WRCLI8 0x0134
#define mmDAGB2_WRCLI8_BASE_IDX 1
#define mmDAGB2_WRCLI9 0x0135
#define mmDAGB2_WRCLI9_BASE_IDX 1
#define mmDAGB2_WRCLI10 0x0136
#define mmDAGB2_WRCLI10_BASE_IDX 1
#define mmDAGB2_WRCLI11 0x0137
#define mmDAGB2_WRCLI11_BASE_IDX 1
#define mmDAGB2_WRCLI12 0x0138
#define mmDAGB2_WRCLI12_BASE_IDX 1
#define mmDAGB2_WRCLI13 0x0139
#define mmDAGB2_WRCLI13_BASE_IDX 1
#define mmDAGB2_WRCLI14 0x013a
#define mmDAGB2_WRCLI14_BASE_IDX 1
#define mmDAGB2_WRCLI15 0x013b
#define mmDAGB2_WRCLI15_BASE_IDX 1
#define mmDAGB2_WR_CNTL 0x013c
#define mmDAGB2_WR_CNTL_BASE_IDX 1
#define mmDAGB2_WR_GMI_CNTL 0x013d
#define mmDAGB2_WR_GMI_CNTL_BASE_IDX 1
#define mmDAGB2_WR_ADDR_DAGB 0x013e
#define mmDAGB2_WR_ADDR_DAGB_BASE_IDX 1
#define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0x013f
#define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
#define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0x0140
#define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
#define mmDAGB2_WR_CGTT_CLK_CTRL 0x0141
#define mmDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0x0142
#define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0x0143
#define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0 0x0144
#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0x0145
#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1 0x0146
#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0x0147
#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB2_WR_DATA_DAGB 0x0148
#define mmDAGB2_WR_DATA_DAGB_BASE_IDX 1
#define mmDAGB2_WR_DATA_DAGB_MAX_BURST0 0x0149
#define mmDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0x014a
#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB2_WR_DATA_DAGB_MAX_BURST1 0x014b
#define mmDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0x014c
#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB2_WR_VC0_CNTL 0x014d
#define mmDAGB2_WR_VC0_CNTL_BASE_IDX 1
#define mmDAGB2_WR_VC1_CNTL 0x014e
#define mmDAGB2_WR_VC1_CNTL_BASE_IDX 1
#define mmDAGB2_WR_VC2_CNTL 0x014f
#define mmDAGB2_WR_VC2_CNTL_BASE_IDX 1
#define mmDAGB2_WR_VC3_CNTL 0x0150
#define mmDAGB2_WR_VC3_CNTL_BASE_IDX 1
#define mmDAGB2_WR_VC4_CNTL 0x0151
#define mmDAGB2_WR_VC4_CNTL_BASE_IDX 1
#define mmDAGB2_WR_VC5_CNTL 0x0152
#define mmDAGB2_WR_VC5_CNTL_BASE_IDX 1
#define mmDAGB2_WR_VC6_CNTL 0x0153
#define mmDAGB2_WR_VC6_CNTL_BASE_IDX 1
#define mmDAGB2_WR_VC7_CNTL 0x0154
#define mmDAGB2_WR_VC7_CNTL_BASE_IDX 1
#define mmDAGB2_WR_CNTL_MISC 0x0155
#define mmDAGB2_WR_CNTL_MISC_BASE_IDX 1
#define mmDAGB2_WR_TLB_CREDIT 0x0156
#define mmDAGB2_WR_TLB_CREDIT_BASE_IDX 1
#define mmDAGB2_WR_DATA_CREDIT 0x0157
#define mmDAGB2_WR_DATA_CREDIT_BASE_IDX 1
#define mmDAGB2_WR_MISC_CREDIT 0x0158
#define mmDAGB2_WR_MISC_CREDIT_BASE_IDX 1
#define mmDAGB2_WRCLI_ASK_PENDING 0x015d
#define mmDAGB2_WRCLI_ASK_PENDING_BASE_IDX 1
#define mmDAGB2_WRCLI_GO_PENDING 0x015e
#define mmDAGB2_WRCLI_GO_PENDING_BASE_IDX 1
#define mmDAGB2_WRCLI_GBLSEND_PENDING 0x015f
#define mmDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX 1
#define mmDAGB2_WRCLI_TLB_PENDING 0x0160
#define mmDAGB2_WRCLI_TLB_PENDING_BASE_IDX 1
#define mmDAGB2_WRCLI_OARB_PENDING 0x0161
#define mmDAGB2_WRCLI_OARB_PENDING_BASE_IDX 1
#define mmDAGB2_WRCLI_OSD_PENDING 0x0162
#define mmDAGB2_WRCLI_OSD_PENDING_BASE_IDX 1
#define mmDAGB2_WRCLI_DBUS_ASK_PENDING 0x0163
#define mmDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
#define mmDAGB2_WRCLI_DBUS_GO_PENDING 0x0164
#define mmDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
#define mmDAGB2_DAGB_DLY 0x0165
#define mmDAGB2_DAGB_DLY_BASE_IDX 1
#define mmDAGB2_CNTL_MISC 0x0166
#define mmDAGB2_CNTL_MISC_BASE_IDX 1
#define mmDAGB2_CNTL_MISC2 0x0167
#define mmDAGB2_CNTL_MISC2_BASE_IDX 1
#define mmDAGB2_FIFO_EMPTY 0x0168
#define mmDAGB2_FIFO_EMPTY_BASE_IDX 1
#define mmDAGB2_FIFO_FULL 0x0169
#define mmDAGB2_FIFO_FULL_BASE_IDX 1
#define mmDAGB2_WR_CREDITS_FULL 0x016a
#define mmDAGB2_WR_CREDITS_FULL_BASE_IDX 1
#define mmDAGB2_RD_CREDITS_FULL 0x016b
#define mmDAGB2_RD_CREDITS_FULL_BASE_IDX 1
#define mmDAGB2_PERFCOUNTER_LO 0x016c
#define mmDAGB2_PERFCOUNTER_LO_BASE_IDX 1
#define mmDAGB2_PERFCOUNTER_HI 0x016d
#define mmDAGB2_PERFCOUNTER_HI_BASE_IDX 1
#define mmDAGB2_PERFCOUNTER0_CFG 0x016e
#define mmDAGB2_PERFCOUNTER0_CFG_BASE_IDX 1
#define mmDAGB2_PERFCOUNTER1_CFG 0x016f
#define mmDAGB2_PERFCOUNTER1_CFG_BASE_IDX 1
#define mmDAGB2_PERFCOUNTER2_CFG 0x0170
#define mmDAGB2_PERFCOUNTER2_CFG_BASE_IDX 1
#define mmDAGB2_PERFCOUNTER_RSLT_CNTL 0x0171
#define mmDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
#define mmDAGB2_RESERVE0 0x0172
#define mmDAGB2_RESERVE0_BASE_IDX 1
#define mmDAGB2_RESERVE1 0x0173
#define mmDAGB2_RESERVE1_BASE_IDX 1
#define mmDAGB2_RESERVE2 0x0174
#define mmDAGB2_RESERVE2_BASE_IDX 1
#define mmDAGB2_RESERVE3 0x0175
#define mmDAGB2_RESERVE3_BASE_IDX 1
#define mmDAGB2_RESERVE4 0x0176
#define mmDAGB2_RESERVE4_BASE_IDX 1
#define mmDAGB2_RESERVE5 0x0177
#define mmDAGB2_RESERVE5_BASE_IDX 1
#define mmDAGB2_RESERVE6 0x0178
#define mmDAGB2_RESERVE6_BASE_IDX 1
#define mmDAGB2_RESERVE7 0x0179
#define mmDAGB2_RESERVE7_BASE_IDX 1
#define mmDAGB2_RESERVE8 0x017a
#define mmDAGB2_RESERVE8_BASE_IDX 1
#define mmDAGB2_RESERVE9 0x017b
#define mmDAGB2_RESERVE9_BASE_IDX 1
#define mmDAGB2_RESERVE10 0x017c
#define mmDAGB2_RESERVE10_BASE_IDX 1
#define mmDAGB2_RESERVE11 0x017d
#define mmDAGB2_RESERVE11_BASE_IDX 1
#define mmDAGB2_RESERVE12 0x017e
#define mmDAGB2_RESERVE12_BASE_IDX 1
#define mmDAGB2_RESERVE13 0x017f
#define mmDAGB2_RESERVE13_BASE_IDX 1
// addressBlock: mmhub_dagb_dagbdec3
// base address: 0x68600
#define mmDAGB3_RDCLI0 0x0180
#define mmDAGB3_RDCLI0_BASE_IDX 1
#define mmDAGB3_RDCLI1 0x0181
#define mmDAGB3_RDCLI1_BASE_IDX 1
#define mmDAGB3_RDCLI2 0x0182
#define mmDAGB3_RDCLI2_BASE_IDX 1
#define mmDAGB3_RDCLI3 0x0183
#define mmDAGB3_RDCLI3_BASE_IDX 1
#define mmDAGB3_RDCLI4 0x0184
#define mmDAGB3_RDCLI4_BASE_IDX 1
#define mmDAGB3_RDCLI5 0x0185
#define mmDAGB3_RDCLI5_BASE_IDX 1
#define mmDAGB3_RDCLI6 0x0186
#define mmDAGB3_RDCLI6_BASE_IDX 1
#define mmDAGB3_RDCLI7 0x0187
#define mmDAGB3_RDCLI7_BASE_IDX 1
#define mmDAGB3_RDCLI8 0x0188
#define mmDAGB3_RDCLI8_BASE_IDX 1
#define mmDAGB3_RDCLI9 0x0189
#define mmDAGB3_RDCLI9_BASE_IDX 1
#define mmDAGB3_RDCLI10 0x018a
#define mmDAGB3_RDCLI10_BASE_IDX 1
#define mmDAGB3_RDCLI11 0x018b
#define mmDAGB3_RDCLI11_BASE_IDX 1
#define mmDAGB3_RDCLI12 0x018c
#define mmDAGB3_RDCLI12_BASE_IDX 1
#define mmDAGB3_RDCLI13 0x018d
#define mmDAGB3_RDCLI13_BASE_IDX 1
#define mmDAGB3_RDCLI14 0x018e
#define mmDAGB3_RDCLI14_BASE_IDX 1
#define mmDAGB3_RDCLI15 0x018f
#define mmDAGB3_RDCLI15_BASE_IDX 1
#define mmDAGB3_RD_CNTL 0x0190
#define mmDAGB3_RD_CNTL_BASE_IDX 1
#define mmDAGB3_RD_GMI_CNTL 0x0191
#define mmDAGB3_RD_GMI_CNTL_BASE_IDX 1
#define mmDAGB3_RD_ADDR_DAGB 0x0192
#define mmDAGB3_RD_ADDR_DAGB_BASE_IDX 1
#define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0x0193
#define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
#define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0x0194
#define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
#define mmDAGB3_RD_CGTT_CLK_CTRL 0x0195
#define mmDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0x0196
#define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0x0197
#define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0 0x0198
#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0x0199
#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1 0x019a
#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0x019b
#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB3_RD_VC0_CNTL 0x019c
#define mmDAGB3_RD_VC0_CNTL_BASE_IDX 1
#define mmDAGB3_RD_VC1_CNTL 0x019d
#define mmDAGB3_RD_VC1_CNTL_BASE_IDX 1
#define mmDAGB3_RD_VC2_CNTL 0x019e
#define mmDAGB3_RD_VC2_CNTL_BASE_IDX 1
#define mmDAGB3_RD_VC3_CNTL 0x019f
#define mmDAGB3_RD_VC3_CNTL_BASE_IDX 1
#define mmDAGB3_RD_VC4_CNTL 0x01a0
#define mmDAGB3_RD_VC4_CNTL_BASE_IDX 1
#define mmDAGB3_RD_VC5_CNTL 0x01a1
#define mmDAGB3_RD_VC5_CNTL_BASE_IDX 1
#define mmDAGB3_RD_VC6_CNTL 0x01a2
#define mmDAGB3_RD_VC6_CNTL_BASE_IDX 1
#define mmDAGB3_RD_VC7_CNTL 0x01a3
#define mmDAGB3_RD_VC7_CNTL_BASE_IDX 1
#define mmDAGB3_RD_CNTL_MISC 0x01a4
#define mmDAGB3_RD_CNTL_MISC_BASE_IDX 1
#define mmDAGB3_RD_TLB_CREDIT 0x01a5
#define mmDAGB3_RD_TLB_CREDIT_BASE_IDX 1
#define mmDAGB3_RDCLI_ASK_PENDING 0x01a6
#define mmDAGB3_RDCLI_ASK_PENDING_BASE_IDX 1
#define mmDAGB3_RDCLI_GO_PENDING 0x01a7
#define mmDAGB3_RDCLI_GO_PENDING_BASE_IDX 1
#define mmDAGB3_RDCLI_GBLSEND_PENDING 0x01a8
#define mmDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX 1
#define mmDAGB3_RDCLI_TLB_PENDING 0x01a9
#define mmDAGB3_RDCLI_TLB_PENDING_BASE_IDX 1
#define mmDAGB3_RDCLI_OARB_PENDING 0x01aa
#define mmDAGB3_RDCLI_OARB_PENDING_BASE_IDX 1
#define mmDAGB3_RDCLI_OSD_PENDING 0x01ab
#define mmDAGB3_RDCLI_OSD_PENDING_BASE_IDX 1
#define mmDAGB3_WRCLI0 0x01ac
#define mmDAGB3_WRCLI0_BASE_IDX 1
#define mmDAGB3_WRCLI1 0x01ad
#define mmDAGB3_WRCLI1_BASE_IDX 1
#define mmDAGB3_WRCLI2 0x01ae
#define mmDAGB3_WRCLI2_BASE_IDX 1
#define mmDAGB3_WRCLI3 0x01af
#define mmDAGB3_WRCLI3_BASE_IDX 1
#define mmDAGB3_WRCLI4 0x01b0
#define mmDAGB3_WRCLI4_BASE_IDX 1
#define mmDAGB3_WRCLI5 0x01b1
#define mmDAGB3_WRCLI5_BASE_IDX 1
#define mmDAGB3_WRCLI6 0x01b2
#define mmDAGB3_WRCLI6_BASE_IDX 1
#define mmDAGB3_WRCLI7 0x01b3
#define mmDAGB3_WRCLI7_BASE_IDX 1
#define mmDAGB3_WRCLI8 0x01b4
#define mmDAGB3_WRCLI8_BASE_IDX 1
#define mmDAGB3_WRCLI9 0x01b5
#define mmDAGB3_WRCLI9_BASE_IDX 1
#define mmDAGB3_WRCLI10 0x01b6
#define mmDAGB3_WRCLI10_BASE_IDX 1
#define mmDAGB3_WRCLI11 0x01b7
#define mmDAGB3_WRCLI11_BASE_IDX 1
#define mmDAGB3_WRCLI12 0x01b8
#define mmDAGB3_WRCLI12_BASE_IDX 1
#define mmDAGB3_WRCLI13 0x01b9
#define mmDAGB3_WRCLI13_BASE_IDX 1
#define mmDAGB3_WRCLI14 0x01ba
#define mmDAGB3_WRCLI14_BASE_IDX 1
#define mmDAGB3_WRCLI15 0x01bb
#define mmDAGB3_WRCLI15_BASE_IDX 1
#define mmDAGB3_WR_CNTL 0x01bc
#define mmDAGB3_WR_CNTL_BASE_IDX 1
#define mmDAGB3_WR_GMI_CNTL 0x01bd
#define mmDAGB3_WR_GMI_CNTL_BASE_IDX 1
#define mmDAGB3_WR_ADDR_DAGB 0x01be
#define mmDAGB3_WR_ADDR_DAGB_BASE_IDX 1
#define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0x01bf
#define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
#define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0x01c0
#define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
#define mmDAGB3_WR_CGTT_CLK_CTRL 0x01c1
#define mmDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0x01c2
#define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0x01c3
#define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0 0x01c4
#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0x01c5
#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1 0x01c6
#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0x01c7
#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB3_WR_DATA_DAGB 0x01c8
#define mmDAGB3_WR_DATA_DAGB_BASE_IDX 1
#define mmDAGB3_WR_DATA_DAGB_MAX_BURST0 0x01c9
#define mmDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0x01ca
#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB3_WR_DATA_DAGB_MAX_BURST1 0x01cb
#define mmDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0x01cc
#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB3_WR_VC0_CNTL 0x01cd
#define mmDAGB3_WR_VC0_CNTL_BASE_IDX 1
#define mmDAGB3_WR_VC1_CNTL 0x01ce
#define mmDAGB3_WR_VC1_CNTL_BASE_IDX 1
#define mmDAGB3_WR_VC2_CNTL 0x01cf
#define mmDAGB3_WR_VC2_CNTL_BASE_IDX 1
#define mmDAGB3_WR_VC3_CNTL 0x01d0
#define mmDAGB3_WR_VC3_CNTL_BASE_IDX 1
#define mmDAGB3_WR_VC4_CNTL 0x01d1
#define mmDAGB3_WR_VC4_CNTL_BASE_IDX 1
#define mmDAGB3_WR_VC5_CNTL 0x01d2
#define mmDAGB3_WR_VC5_CNTL_BASE_IDX 1
#define mmDAGB3_WR_VC6_CNTL 0x01d3
#define mmDAGB3_WR_VC6_CNTL_BASE_IDX 1
#define mmDAGB3_WR_VC7_CNTL 0x01d4
#define mmDAGB3_WR_VC7_CNTL_BASE_IDX 1
#define mmDAGB3_WR_CNTL_MISC 0x01d5
#define mmDAGB3_WR_CNTL_MISC_BASE_IDX 1
#define mmDAGB3_WR_TLB_CREDIT 0x01d6
#define mmDAGB3_WR_TLB_CREDIT_BASE_IDX 1
#define mmDAGB3_WR_DATA_CREDIT 0x01d7
#define mmDAGB3_WR_DATA_CREDIT_BASE_IDX 1
#define mmDAGB3_WR_MISC_CREDIT 0x01d8
#define mmDAGB3_WR_MISC_CREDIT_BASE_IDX 1
#define mmDAGB3_WRCLI_ASK_PENDING 0x01dd
#define mmDAGB3_WRCLI_ASK_PENDING_BASE_IDX 1
#define mmDAGB3_WRCLI_GO_PENDING 0x01de
#define mmDAGB3_WRCLI_GO_PENDING_BASE_IDX 1
#define mmDAGB3_WRCLI_GBLSEND_PENDING 0x01df
#define mmDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX 1
#define mmDAGB3_WRCLI_TLB_PENDING 0x01e0
#define mmDAGB3_WRCLI_TLB_PENDING_BASE_IDX 1
#define mmDAGB3_WRCLI_OARB_PENDING 0x01e1
#define mmDAGB3_WRCLI_OARB_PENDING_BASE_IDX 1
#define mmDAGB3_WRCLI_OSD_PENDING 0x01e2
#define mmDAGB3_WRCLI_OSD_PENDING_BASE_IDX 1
#define mmDAGB3_WRCLI_DBUS_ASK_PENDING 0x01e3
#define mmDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
#define mmDAGB3_WRCLI_DBUS_GO_PENDING 0x01e4
#define mmDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
#define mmDAGB3_DAGB_DLY 0x01e5
#define mmDAGB3_DAGB_DLY_BASE_IDX 1
#define mmDAGB3_CNTL_MISC 0x01e6
#define mmDAGB3_CNTL_MISC_BASE_IDX 1
#define mmDAGB3_CNTL_MISC2 0x01e7
#define mmDAGB3_CNTL_MISC2_BASE_IDX 1
#define mmDAGB3_FIFO_EMPTY 0x01e8
#define mmDAGB3_FIFO_EMPTY_BASE_IDX 1
#define mmDAGB3_FIFO_FULL 0x01e9
#define mmDAGB3_FIFO_FULL_BASE_IDX 1
#define mmDAGB3_WR_CREDITS_FULL 0x01ea
#define mmDAGB3_WR_CREDITS_FULL_BASE_IDX 1
#define mmDAGB3_RD_CREDITS_FULL 0x01eb
#define mmDAGB3_RD_CREDITS_FULL_BASE_IDX 1
#define mmDAGB3_PERFCOUNTER_LO 0x01ec
#define mmDAGB3_PERFCOUNTER_LO_BASE_IDX 1
#define mmDAGB3_PERFCOUNTER_HI 0x01ed
#define mmDAGB3_PERFCOUNTER_HI_BASE_IDX 1
#define mmDAGB3_PERFCOUNTER0_CFG 0x01ee
#define mmDAGB3_PERFCOUNTER0_CFG_BASE_IDX 1
#define mmDAGB3_PERFCOUNTER1_CFG 0x01ef
#define mmDAGB3_PERFCOUNTER1_CFG_BASE_IDX 1
#define mmDAGB3_PERFCOUNTER2_CFG 0x01f0
#define mmDAGB3_PERFCOUNTER2_CFG_BASE_IDX 1
#define mmDAGB3_PERFCOUNTER_RSLT_CNTL 0x01f1
#define mmDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
#define mmDAGB3_RESERVE0 0x01f2
#define mmDAGB3_RESERVE0_BASE_IDX 1
#define mmDAGB3_RESERVE1 0x01f3
#define mmDAGB3_RESERVE1_BASE_IDX 1
#define mmDAGB3_RESERVE2 0x01f4
#define mmDAGB3_RESERVE2_BASE_IDX 1
#define mmDAGB3_RESERVE3 0x01f5
#define mmDAGB3_RESERVE3_BASE_IDX 1
#define mmDAGB3_RESERVE4 0x01f6
#define mmDAGB3_RESERVE4_BASE_IDX 1
#define mmDAGB3_RESERVE5 0x01f7
#define mmDAGB3_RESERVE5_BASE_IDX 1
#define mmDAGB3_RESERVE6 0x01f8
#define mmDAGB3_RESERVE6_BASE_IDX 1
#define mmDAGB3_RESERVE7 0x01f9
#define mmDAGB3_RESERVE7_BASE_IDX 1
#define mmDAGB3_RESERVE8 0x01fa
#define mmDAGB3_RESERVE8_BASE_IDX 1
#define mmDAGB3_RESERVE9 0x01fb
#define mmDAGB3_RESERVE9_BASE_IDX 1
#define mmDAGB3_RESERVE10 0x01fc
#define mmDAGB3_RESERVE10_BASE_IDX 1
#define mmDAGB3_RESERVE11 0x01fd
#define mmDAGB3_RESERVE11_BASE_IDX 1
#define mmDAGB3_RESERVE12 0x01fe
#define mmDAGB3_RESERVE12_BASE_IDX 1
#define mmDAGB3_RESERVE13 0x01ff
#define mmDAGB3_RESERVE13_BASE_IDX 1
// addressBlock: mmhub_dagb_dagbdec4
// base address: 0x68800
#define mmDAGB4_RDCLI0 0x0200
#define mmDAGB4_RDCLI0_BASE_IDX 1
#define mmDAGB4_RDCLI1 0x0201
#define mmDAGB4_RDCLI1_BASE_IDX 1
#define mmDAGB4_RDCLI2 0x0202
#define mmDAGB4_RDCLI2_BASE_IDX 1
#define mmDAGB4_RDCLI3 0x0203
#define mmDAGB4_RDCLI3_BASE_IDX 1
#define mmDAGB4_RDCLI4 0x0204
#define mmDAGB4_RDCLI4_BASE_IDX 1
#define mmDAGB4_RDCLI5 0x0205
#define mmDAGB4_RDCLI5_BASE_IDX 1
#define mmDAGB4_RDCLI6 0x0206
#define mmDAGB4_RDCLI6_BASE_IDX 1
#define mmDAGB4_RDCLI7 0x0207
#define mmDAGB4_RDCLI7_BASE_IDX 1
#define mmDAGB4_RDCLI8 0x0208
#define mmDAGB4_RDCLI8_BASE_IDX 1
#define mmDAGB4_RDCLI9 0x0209
#define mmDAGB4_RDCLI9_BASE_IDX 1
#define mmDAGB4_RDCLI10 0x020a
#define mmDAGB4_RDCLI10_BASE_IDX 1
#define mmDAGB4_RDCLI11 0x020b
#define mmDAGB4_RDCLI11_BASE_IDX 1
#define mmDAGB4_RDCLI12 0x020c
#define mmDAGB4_RDCLI12_BASE_IDX 1
#define mmDAGB4_RDCLI13 0x020d
#define mmDAGB4_RDCLI13_BASE_IDX 1
#define mmDAGB4_RDCLI14 0x020e
#define mmDAGB4_RDCLI14_BASE_IDX 1
#define mmDAGB4_RDCLI15 0x020f
#define mmDAGB4_RDCLI15_BASE_IDX 1
#define mmDAGB4_RD_CNTL 0x0210
#define mmDAGB4_RD_CNTL_BASE_IDX 1
#define mmDAGB4_RD_GMI_CNTL 0x0211
#define mmDAGB4_RD_GMI_CNTL_BASE_IDX 1
#define mmDAGB4_RD_ADDR_DAGB 0x0212
#define mmDAGB4_RD_ADDR_DAGB_BASE_IDX 1
#define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0x0213
#define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
#define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0x0214
#define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
#define mmDAGB4_RD_CGTT_CLK_CTRL 0x0215
#define mmDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0x0216
#define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0x0217
#define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0 0x0218
#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0x0219
#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1 0x021a
#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0x021b
#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB4_RD_VC0_CNTL 0x021c
#define mmDAGB4_RD_VC0_CNTL_BASE_IDX 1
#define mmDAGB4_RD_VC1_CNTL 0x021d
#define mmDAGB4_RD_VC1_CNTL_BASE_IDX 1
#define mmDAGB4_RD_VC2_CNTL 0x021e
#define mmDAGB4_RD_VC2_CNTL_BASE_IDX 1
#define mmDAGB4_RD_VC3_CNTL 0x021f
#define mmDAGB4_RD_VC3_CNTL_BASE_IDX 1
#define mmDAGB4_RD_VC4_CNTL 0x0220
#define mmDAGB4_RD_VC4_CNTL_BASE_IDX 1
#define mmDAGB4_RD_VC5_CNTL 0x0221
#define mmDAGB4_RD_VC5_CNTL_BASE_IDX 1
#define mmDAGB4_RD_VC6_CNTL 0x0222
#define mmDAGB4_RD_VC6_CNTL_BASE_IDX 1
#define mmDAGB4_RD_VC7_CNTL 0x0223
#define mmDAGB4_RD_VC7_CNTL_BASE_IDX 1
#define mmDAGB4_RD_CNTL_MISC 0x0224
#define mmDAGB4_RD_CNTL_MISC_BASE_IDX 1
#define mmDAGB4_RD_TLB_CREDIT 0x0225
#define mmDAGB4_RD_TLB_CREDIT_BASE_IDX 1
#define mmDAGB4_RDCLI_ASK_PENDING 0x0226
#define mmDAGB4_RDCLI_ASK_PENDING_BASE_IDX 1
#define mmDAGB4_RDCLI_GO_PENDING 0x0227
#define mmDAGB4_RDCLI_GO_PENDING_BASE_IDX 1
#define mmDAGB4_RDCLI_GBLSEND_PENDING 0x0228
#define mmDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX 1
#define mmDAGB4_RDCLI_TLB_PENDING 0x0229
#define mmDAGB4_RDCLI_TLB_PENDING_BASE_IDX 1
#define mmDAGB4_RDCLI_OARB_PENDING 0x022a
#define mmDAGB4_RDCLI_OARB_PENDING_BASE_IDX 1
#define mmDAGB4_RDCLI_OSD_PENDING 0x022b
#define mmDAGB4_RDCLI_OSD_PENDING_BASE_IDX 1
#define mmDAGB4_WRCLI0 0x022c
#define mmDAGB4_WRCLI0_BASE_IDX 1
#define mmDAGB4_WRCLI1 0x022d
#define mmDAGB4_WRCLI1_BASE_IDX 1
#define mmDAGB4_WRCLI2 0x022e
#define mmDAGB4_WRCLI2_BASE_IDX 1
#define mmDAGB4_WRCLI3 0x022f
#define mmDAGB4_WRCLI3_BASE_IDX 1
#define mmDAGB4_WRCLI4 0x0230
#define mmDAGB4_WRCLI4_BASE_IDX 1
#define mmDAGB4_WRCLI5 0x0231
#define mmDAGB4_WRCLI5_BASE_IDX 1
#define mmDAGB4_WRCLI6 0x0232
#define mmDAGB4_WRCLI6_BASE_IDX 1
#define mmDAGB4_WRCLI7 0x0233
#define mmDAGB4_WRCLI7_BASE_IDX 1
#define mmDAGB4_WRCLI8 0x0234
#define mmDAGB4_WRCLI8_BASE_IDX 1
#define mmDAGB4_WRCLI9 0x0235
#define mmDAGB4_WRCLI9_BASE_IDX 1
#define mmDAGB4_WRCLI10 0x0236
#define mmDAGB4_WRCLI10_BASE_IDX 1
#define mmDAGB4_WRCLI11 0x0237
#define mmDAGB4_WRCLI11_BASE_IDX 1
#define mmDAGB4_WRCLI12 0x0238
#define mmDAGB4_WRCLI12_BASE_IDX 1
#define mmDAGB4_WRCLI13 0x0239
#define mmDAGB4_WRCLI13_BASE_IDX 1
#define mmDAGB4_WRCLI14 0x023a
#define mmDAGB4_WRCLI14_BASE_IDX 1
#define mmDAGB4_WRCLI15 0x023b
#define mmDAGB4_WRCLI15_BASE_IDX 1
#define mmDAGB4_WR_CNTL 0x023c
#define mmDAGB4_WR_CNTL_BASE_IDX 1
#define mmDAGB4_WR_GMI_CNTL 0x023d
#define mmDAGB4_WR_GMI_CNTL_BASE_IDX 1
#define mmDAGB4_WR_ADDR_DAGB 0x023e
#define mmDAGB4_WR_ADDR_DAGB_BASE_IDX 1
#define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0x023f
#define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
#define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0x0240
#define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
#define mmDAGB4_WR_CGTT_CLK_CTRL 0x0241
#define mmDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0x0242
#define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0x0243
#define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0 0x0244
#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0x0245
#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1 0x0246
#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0x0247
#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB4_WR_DATA_DAGB 0x0248
#define mmDAGB4_WR_DATA_DAGB_BASE_IDX 1
#define mmDAGB4_WR_DATA_DAGB_MAX_BURST0 0x0249
#define mmDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0x024a
#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
#define mmDAGB4_WR_DATA_DAGB_MAX_BURST1 0x024b
#define mmDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0x024c
#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
#define mmDAGB4_WR_VC0_CNTL 0x024d
#define mmDAGB4_WR_VC0_CNTL_BASE_IDX 1
#define mmDAGB4_WR_VC1_CNTL 0x024e
#define mmDAGB4_WR_VC1_CNTL_BASE_IDX 1
#define mmDAGB4_WR_VC2_CNTL 0x024f
#define mmDAGB4_WR_VC2_CNTL_BASE_IDX 1
#define mmDAGB4_WR_VC3_CNTL 0x0250
#define mmDAGB4_WR_VC3_CNTL_BASE_IDX 1
#define mmDAGB4_WR_VC4_CNTL 0x0251
#define mmDAGB4_WR_VC4_CNTL_BASE_IDX 1
#define mmDAGB4_WR_VC5_CNTL 0x0252
#define mmDAGB4_WR_VC5_CNTL_BASE_IDX 1
#define mmDAGB4_WR_VC6_CNTL 0x0253
#define mmDAGB4_WR_VC6_CNTL_BASE_IDX 1
#define mmDAGB4_WR_VC7_CNTL 0x0254
#define mmDAGB4_WR_VC7_CNTL_BASE_IDX 1
#define mmDAGB4_WR_CNTL_MISC 0x0255
#define mmDAGB4_WR_CNTL_MISC_BASE_IDX 1
#define mmDAGB4_WR_TLB_CREDIT 0x0256
#define mmDAGB4_WR_TLB_CREDIT_BASE_IDX 1
#define mmDAGB4_WR_DATA_CREDIT 0x0257
#define mmDAGB4_WR_DATA_CREDIT_BASE_IDX 1
#define mmDAGB4_WR_MISC_CREDIT 0x0258
#define mmDAGB4_WR_MISC_CREDIT_BASE_IDX 1
#define mmDAGB4_WRCLI_ASK_PENDING 0x025d
#define mmDAGB4_WRCLI_ASK_PENDING_BASE_IDX 1
#define mmDAGB4_WRCLI_GO_PENDING 0x025e
#define mmDAGB4_WRCLI_GO_PENDING_BASE_IDX 1
#define mmDAGB4_WRCLI_GBLSEND_PENDING 0x025f
#define mmDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX 1
#define mmDAGB4_WRCLI_TLB_PENDING 0x0260
#define mmDAGB4_WRCLI_TLB_PENDING_BASE_IDX 1
#define mmDAGB4_WRCLI_OARB_PENDING 0x0261
#define mmDAGB4_WRCLI_OARB_PENDING_BASE_IDX 1
#define mmDAGB4_WRCLI_OSD_PENDING 0x0262
#define mmDAGB4_WRCLI_OSD_PENDING_BASE_IDX 1
#define mmDAGB4_WRCLI_DBUS_ASK_PENDING 0x0263
#define mmDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
#define mmDAGB4_WRCLI_DBUS_GO_PENDING 0x0264
#define mmDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
#define mmDAGB4_DAGB_DLY 0x0265
#define mmDAGB4_DAGB_DLY_BASE_IDX 1
#define mmDAGB4_CNTL_MISC 0x0266
#define mmDAGB4_CNTL_MISC_BASE_IDX 1
#define mmDAGB4_CNTL_MISC2 0x0267
#define mmDAGB4_CNTL_MISC2_BASE_IDX 1
#define mmDAGB4_FIFO_EMPTY 0x0268
#define mmDAGB4_FIFO_EMPTY_BASE_IDX 1
#define mmDAGB4_FIFO_FULL 0x0269
#define mmDAGB4_FIFO_FULL_BASE_IDX 1
#define mmDAGB4_WR_CREDITS_FULL 0x026a
#define mmDAGB4_WR_CREDITS_FULL_BASE_IDX 1
#define mmDAGB4_RD_CREDITS_FULL 0x026b
#define mmDAGB4_RD_CREDITS_FULL_BASE_IDX 1
#define mmDAGB4_PERFCOUNTER_LO 0x026c
#define mmDAGB4_PERFCOUNTER_LO_BASE_IDX 1
#define mmDAGB4_PERFCOUNTER_HI 0x026d
#define mmDAGB4_PERFCOUNTER_HI_BASE_IDX 1
#define mmDAGB4_PERFCOUNTER0_CFG 0x026e
#define mmDAGB4_PERFCOUNTER0_CFG_BASE_IDX 1
#define mmDAGB4_PERFCOUNTER1_CFG 0x026f
#define mmDAGB4_PERFCOUNTER1_CFG_BASE_IDX 1
#define mmDAGB4_PERFCOUNTER2_CFG 0x0270
#define mmDAGB4_PERFCOUNTER2_CFG_BASE_IDX 1
#define mmDAGB4_PERFCOUNTER_RSLT_CNTL 0x0271
#define mmDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
#define mmDAGB4_RESERVE0 0x0272
#define mmDAGB4_RESERVE0_BASE_IDX 1
#define mmDAGB4_RESERVE1 0x0273
#define mmDAGB4_RESERVE1_BASE_IDX 1
#define mmDAGB4_RESERVE2 0x0274
#define mmDAGB4_RESERVE2_BASE_IDX 1
#define mmDAGB4_RESERVE3 0x0275
#define mmDAGB4_RESERVE3_BASE_IDX 1
#define mmDAGB4_RESERVE4 0x0276
#define mmDAGB4_RESERVE4_BASE_IDX 1
#define mmDAGB4_RESERVE5 0x0277
#define mmDAGB4_RESERVE5_BASE_IDX 1
#define mmDAGB4_RESERVE6 0x0278
#define mmDAGB4_RESERVE6_BASE_IDX 1
#define mmDAGB4_RESERVE7 0x0279
#define mmDAGB4_RESERVE7_BASE_IDX 1
#define mmDAGB4_RESERVE8 0x027a
#define mmDAGB4_RESERVE8_BASE_IDX 1
#define mmDAGB4_RESERVE9 0x027b
#define mmDAGB4_RESERVE9_BASE_IDX 1
#define mmDAGB4_RESERVE10 0x027c
#define mmDAGB4_RESERVE10_BASE_IDX 1
#define mmDAGB4_RESERVE11 0x027d
#define mmDAGB4_RESERVE11_BASE_IDX 1
#define mmDAGB4_RESERVE12 0x027e
#define mmDAGB4_RESERVE12_BASE_IDX 1
#define mmDAGB4_RESERVE13 0x027f
#define mmDAGB4_RESERVE13_BASE_IDX 1
// addressBlock: mmhub_ea_mmeadec0
// base address: 0x68a00
#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0280
#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0281
#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0282
#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0283
#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0284
#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 1
#define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0285
#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 1
#define mmMMEA0_DRAM_RD_LAZY 0x0286
#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 1
#define mmMMEA0_DRAM_WR_LAZY 0x0287
#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 1
#define mmMMEA0_DRAM_RD_CAM_CNTL 0x0288
#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 1
#define mmMMEA0_DRAM_WR_CAM_CNTL 0x0289
#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 1
#define mmMMEA0_DRAM_PAGE_BURST 0x028a
#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 1
#define mmMMEA0_DRAM_RD_PRI_AGE 0x028b
#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 1
#define mmMMEA0_DRAM_WR_PRI_AGE 0x028c
#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 1
#define mmMMEA0_DRAM_RD_PRI_QUEUING 0x028d
#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 1
#define mmMMEA0_DRAM_WR_PRI_QUEUING 0x028e
#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 1
#define mmMMEA0_DRAM_RD_PRI_FIXED 0x028f
#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 1
#define mmMMEA0_DRAM_WR_PRI_FIXED 0x0290
#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 1
#define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0291
#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 1
#define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0292
#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 1
#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0293
#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0294
#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0295
#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0296
#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0297
#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0298
#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA0_GMI_RD_CLI2GRP_MAP0 0x0299
#define mmMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA0_GMI_RD_CLI2GRP_MAP1 0x029a
#define mmMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA0_GMI_WR_CLI2GRP_MAP0 0x029b
#define mmMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA0_GMI_WR_CLI2GRP_MAP1 0x029c
#define mmMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA0_GMI_RD_GRP2VC_MAP 0x029d
#define mmMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX 1
#define mmMMEA0_GMI_WR_GRP2VC_MAP 0x029e
#define mmMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX 1
#define mmMMEA0_GMI_RD_LAZY 0x029f
#define mmMMEA0_GMI_RD_LAZY_BASE_IDX 1
#define mmMMEA0_GMI_WR_LAZY 0x02a0
#define mmMMEA0_GMI_WR_LAZY_BASE_IDX 1
#define mmMMEA0_GMI_RD_CAM_CNTL 0x02a1
#define mmMMEA0_GMI_RD_CAM_CNTL_BASE_IDX 1
#define mmMMEA0_GMI_WR_CAM_CNTL 0x02a2
#define mmMMEA0_GMI_WR_CAM_CNTL_BASE_IDX 1
#define mmMMEA0_GMI_PAGE_BURST 0x02a3
#define mmMMEA0_GMI_PAGE_BURST_BASE_IDX 1
#define mmMMEA0_GMI_RD_PRI_AGE 0x02a4
#define mmMMEA0_GMI_RD_PRI_AGE_BASE_IDX 1
#define mmMMEA0_GMI_WR_PRI_AGE 0x02a5
#define mmMMEA0_GMI_WR_PRI_AGE_BASE_IDX 1
#define mmMMEA0_GMI_RD_PRI_QUEUING 0x02a6
#define mmMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX 1
#define mmMMEA0_GMI_WR_PRI_QUEUING 0x02a7
#define mmMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX 1
#define mmMMEA0_GMI_RD_PRI_FIXED 0x02a8
#define mmMMEA0_GMI_RD_PRI_FIXED_BASE_IDX 1
#define mmMMEA0_GMI_WR_PRI_FIXED 0x02a9
#define mmMMEA0_GMI_WR_PRI_FIXED_BASE_IDX 1
#define mmMMEA0_GMI_RD_PRI_URGENCY 0x02aa
#define mmMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX 1
#define mmMMEA0_GMI_WR_PRI_URGENCY 0x02ab
#define mmMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX 1
#define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING 0x02ac
#define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1
#define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING 0x02ad
#define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1
#define mmMMEA0_GMI_RD_PRI_QUANT_PRI1 0x02ae
#define mmMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA0_GMI_RD_PRI_QUANT_PRI2 0x02af
#define mmMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA0_GMI_RD_PRI_QUANT_PRI3 0x02b0
#define mmMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA0_GMI_WR_PRI_QUANT_PRI1 0x02b1
#define mmMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA0_GMI_WR_PRI_QUANT_PRI2 0x02b2
#define mmMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA0_GMI_WR_PRI_QUANT_PRI3 0x02b3
#define mmMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA0_ADDRNORM_BASE_ADDR0 0x02b4
#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 1
#define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x02b5
#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1
#define mmMMEA0_ADDRNORM_BASE_ADDR1 0x02b6
#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 1
#define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x02b7
#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1
#define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x02b8
#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1
#define mmMMEA0_ADDRNORM_BASE_ADDR2 0x02b9
#define mmMMEA0_ADDRNORM_BASE_ADDR2_BASE_IDX 1
#define mmMMEA0_ADDRNORM_LIMIT_ADDR2 0x02ba
#define mmMMEA0_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1
#define mmMMEA0_ADDRNORM_BASE_ADDR3 0x02bb
#define mmMMEA0_ADDRNORM_BASE_ADDR3_BASE_IDX 1
#define mmMMEA0_ADDRNORM_LIMIT_ADDR3 0x02bc
#define mmMMEA0_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1
#define mmMMEA0_ADDRNORM_OFFSET_ADDR3 0x02bd
#define mmMMEA0_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1
#define mmMMEA0_ADDRNORM_BASE_ADDR4 0x02be
#define mmMMEA0_ADDRNORM_BASE_ADDR4_BASE_IDX 1
#define mmMMEA0_ADDRNORM_LIMIT_ADDR4 0x02bf
#define mmMMEA0_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1
#define mmMMEA0_ADDRNORM_BASE_ADDR5 0x02c0
#define mmMMEA0_ADDRNORM_BASE_ADDR5_BASE_IDX 1
#define mmMMEA0_ADDRNORM_LIMIT_ADDR5 0x02c1
#define mmMMEA0_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1
#define mmMMEA0_ADDRNORM_OFFSET_ADDR5 0x02c2
#define mmMMEA0_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1
#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x02c3
#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1
#define mmMMEA0_ADDRNORMGMI_HOLE_CNTL 0x02c4
#define mmMMEA0_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1
#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x02c5
#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1
#define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 0x02c6
#define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1
#define mmMMEA0_ADDRDEC_BANK_CFG 0x02c7
#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 1
#define mmMMEA0_ADDRDEC_MISC_CFG 0x02c8
#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 1
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x02c9
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x02ca
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x02cb
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x02cc
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x02cd
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 0x02ce
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x02cf
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x02d0
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x02d1
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x02d2
#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1
#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x02d3
#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0 0x02d4
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1 0x02d5
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2 0x02d6
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3 0x02d7
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4 0x02d8
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5 0x02d9
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC 0x02da
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2 0x02db
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0 0x02dc
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1 0x02dd
#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1
#define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE 0x02de
#define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x02df
#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x02e0
#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x02e1
#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x02e2
#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x02e3
#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x02e4
#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x02e5
#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x02e6
#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x02e7
#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x02e8
#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x02e9
#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x02ea
#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x02eb
#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x02ec
#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x02ed
#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x02ee
#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0x02ef
#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0x02f0
#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x02f1
#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x02f2
#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x02f3
#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x02f4
#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x02f5
#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x02f6
#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x02f7
#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x02f8
#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x02f9
#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x02fa
#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x02fb
#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x02fc
#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x02fd
#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x02fe
#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x02ff
#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0300
#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0301
#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0302
#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0303
#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0304
#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0305
#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x0306
#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x0307
#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0308
#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0x0309
#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0x030a
#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x030b
#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x030c
#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x030d
#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x030e
#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x030f
#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0310
#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0311
#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0312
#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0 0x0313
#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1 0x0314
#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2 0x0315
#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3 0x0316
#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 0x0317
#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 0x0318
#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 0x0319
#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 0x031a
#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01 0x031b
#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23 0x031c
#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 0x031d
#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 0x031e
#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01 0x031f
#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23 0x0320
#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01 0x0321
#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23 0x0322
#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01 0x0323
#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23 0x0324
#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01 0x0325
#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23 0x0326
#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01 0x0327
#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23 0x0328
#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_RM_SEL_CS01 0x0329
#define mmMMEA0_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_RM_SEL_CS23 0x032a
#define mmMMEA0_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01 0x032b
#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1
#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23 0x032c
#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1
#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0x032d
#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1
#define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL 0x032e
#define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1
#define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x0355
#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x0356
#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x0357
#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x0358
#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA0_IO_RD_COMBINE_FLUSH 0x0359
#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 1
#define mmMMEA0_IO_WR_COMBINE_FLUSH 0x035a
#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 1
#define mmMMEA0_IO_GROUP_BURST 0x035b
#define mmMMEA0_IO_GROUP_BURST_BASE_IDX 1
#define mmMMEA0_IO_RD_PRI_AGE 0x035c
#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 1
#define mmMMEA0_IO_WR_PRI_AGE 0x035d
#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 1
#define mmMMEA0_IO_RD_PRI_QUEUING 0x035e
#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 1
#define mmMMEA0_IO_WR_PRI_QUEUING 0x035f
#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 1
#define mmMMEA0_IO_RD_PRI_FIXED 0x0360
#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 1
#define mmMMEA0_IO_WR_PRI_FIXED 0x0361
#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 1
#define mmMMEA0_IO_RD_PRI_URGENCY 0x0362
#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 1
#define mmMMEA0_IO_WR_PRI_URGENCY 0x0363
#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 1
#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0x0364
#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1
#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0x0365
#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1
#define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x0366
#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x0367
#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x0368
#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x0369
#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x036a
#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x036b
#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA0_SDP_ARB_DRAM 0x036c
#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 1
#define mmMMEA0_SDP_ARB_GMI 0x036d
#define mmMMEA0_SDP_ARB_GMI_BASE_IDX 1
#define mmMMEA0_SDP_ARB_FINAL 0x036e
#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 1
#define mmMMEA0_SDP_DRAM_PRIORITY 0x036f
#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 1
#define mmMMEA0_SDP_GMI_PRIORITY 0x0370
#define mmMMEA0_SDP_GMI_PRIORITY_BASE_IDX 1
#define mmMMEA0_SDP_IO_PRIORITY 0x0371
#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 1
#define mmMMEA0_SDP_CREDITS 0x0372
#define mmMMEA0_SDP_CREDITS_BASE_IDX 1
#define mmMMEA0_SDP_TAG_RESERVE0 0x0373
#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 1
#define mmMMEA0_SDP_TAG_RESERVE1 0x0374
#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 1
#define mmMMEA0_SDP_VCC_RESERVE0 0x0375
#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 1
#define mmMMEA0_SDP_VCC_RESERVE1 0x0376
#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 1
#define mmMMEA0_SDP_VCD_RESERVE0 0x0377
#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 1
#define mmMMEA0_SDP_VCD_RESERVE1 0x0378
#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 1
#define mmMMEA0_SDP_REQ_CNTL 0x0379
#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 1
#define mmMMEA0_MISC 0x037a
#define mmMMEA0_MISC_BASE_IDX 1
#define mmMMEA0_LATENCY_SAMPLING 0x037b
#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 1
#define mmMMEA0_PERFCOUNTER_LO 0x037c
#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 1
#define mmMMEA0_PERFCOUNTER_HI 0x037d
#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 1
#define mmMMEA0_PERFCOUNTER0_CFG 0x037e
#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 1
#define mmMMEA0_PERFCOUNTER1_CFG 0x037f
#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 1
#define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0380
#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
#define mmMMEA0_EDC_CNT 0x0386
#define mmMMEA0_EDC_CNT_BASE_IDX 1
#define mmMMEA0_EDC_CNT2 0x0387
#define mmMMEA0_EDC_CNT2_BASE_IDX 1
#define mmMMEA0_DSM_CNTL 0x0388
#define mmMMEA0_DSM_CNTL_BASE_IDX 1
#define mmMMEA0_DSM_CNTLA 0x0389
#define mmMMEA0_DSM_CNTLA_BASE_IDX 1
#define mmMMEA0_DSM_CNTLB 0x038a
#define mmMMEA0_DSM_CNTLB_BASE_IDX 1
#define mmMMEA0_DSM_CNTL2 0x038b
#define mmMMEA0_DSM_CNTL2_BASE_IDX 1
#define mmMMEA0_DSM_CNTL2A 0x038c
#define mmMMEA0_DSM_CNTL2A_BASE_IDX 1
#define mmMMEA0_DSM_CNTL2B 0x038d
#define mmMMEA0_DSM_CNTL2B_BASE_IDX 1
#define mmMMEA0_CGTT_CLK_CTRL 0x038f
#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 1
#define mmMMEA0_EDC_MODE 0x0390
#define mmMMEA0_EDC_MODE_BASE_IDX 1
#define mmMMEA0_ERR_STATUS 0x0391
#define mmMMEA0_ERR_STATUS_BASE_IDX 1
#define mmMMEA0_MISC2 0x0392
#define mmMMEA0_MISC2_BASE_IDX 1
#define mmMMEA0_ADDRDEC_SELECT 0x0393
#define mmMMEA0_ADDRDEC_SELECT_BASE_IDX 1
#define mmMMEA0_EDC_CNT3 0x0394
#define mmMMEA0_EDC_CNT3_BASE_IDX 1
// addressBlock: mmhub_ea_mmeadec1
// base address: 0x68f00
#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0x03c0
#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0x03c1
#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0x03c2
#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0x03c3
#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA1_DRAM_RD_GRP2VC_MAP 0x03c4
#define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 1
#define mmMMEA1_DRAM_WR_GRP2VC_MAP 0x03c5
#define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 1
#define mmMMEA1_DRAM_RD_LAZY 0x03c6
#define mmMMEA1_DRAM_RD_LAZY_BASE_IDX 1
#define mmMMEA1_DRAM_WR_LAZY 0x03c7
#define mmMMEA1_DRAM_WR_LAZY_BASE_IDX 1
#define mmMMEA1_DRAM_RD_CAM_CNTL 0x03c8
#define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 1
#define mmMMEA1_DRAM_WR_CAM_CNTL 0x03c9
#define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 1
#define mmMMEA1_DRAM_PAGE_BURST 0x03ca
#define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX 1
#define mmMMEA1_DRAM_RD_PRI_AGE 0x03cb
#define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 1
#define mmMMEA1_DRAM_WR_PRI_AGE 0x03cc
#define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 1
#define mmMMEA1_DRAM_RD_PRI_QUEUING 0x03cd
#define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 1
#define mmMMEA1_DRAM_WR_PRI_QUEUING 0x03ce
#define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 1
#define mmMMEA1_DRAM_RD_PRI_FIXED 0x03cf
#define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 1
#define mmMMEA1_DRAM_WR_PRI_FIXED 0x03d0
#define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 1
#define mmMMEA1_DRAM_RD_PRI_URGENCY 0x03d1
#define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 1
#define mmMMEA1_DRAM_WR_PRI_URGENCY 0x03d2
#define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 1
#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x03d3
#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x03d4
#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x03d5
#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x03d6
#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x03d7
#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x03d8
#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA1_GMI_RD_CLI2GRP_MAP0 0x03d9
#define mmMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA1_GMI_RD_CLI2GRP_MAP1 0x03da
#define mmMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA1_GMI_WR_CLI2GRP_MAP0 0x03db
#define mmMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA1_GMI_WR_CLI2GRP_MAP1 0x03dc
#define mmMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA1_GMI_RD_GRP2VC_MAP 0x03dd
#define mmMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX 1
#define mmMMEA1_GMI_WR_GRP2VC_MAP 0x03de
#define mmMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX 1
#define mmMMEA1_GMI_RD_LAZY 0x03df
#define mmMMEA1_GMI_RD_LAZY_BASE_IDX 1
#define mmMMEA1_GMI_WR_LAZY 0x03e0
#define mmMMEA1_GMI_WR_LAZY_BASE_IDX 1
#define mmMMEA1_GMI_RD_CAM_CNTL 0x03e1
#define mmMMEA1_GMI_RD_CAM_CNTL_BASE_IDX 1
#define mmMMEA1_GMI_WR_CAM_CNTL 0x03e2
#define mmMMEA1_GMI_WR_CAM_CNTL_BASE_IDX 1
#define mmMMEA1_GMI_PAGE_BURST 0x03e3
#define mmMMEA1_GMI_PAGE_BURST_BASE_IDX 1
#define mmMMEA1_GMI_RD_PRI_AGE 0x03e4
#define mmMMEA1_GMI_RD_PRI_AGE_BASE_IDX 1
#define mmMMEA1_GMI_WR_PRI_AGE 0x03e5
#define mmMMEA1_GMI_WR_PRI_AGE_BASE_IDX 1
#define mmMMEA1_GMI_RD_PRI_QUEUING 0x03e6
#define mmMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX 1
#define mmMMEA1_GMI_WR_PRI_QUEUING 0x03e7
#define mmMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX 1
#define mmMMEA1_GMI_RD_PRI_FIXED 0x03e8
#define mmMMEA1_GMI_RD_PRI_FIXED_BASE_IDX 1
#define mmMMEA1_GMI_WR_PRI_FIXED 0x03e9
#define mmMMEA1_GMI_WR_PRI_FIXED_BASE_IDX 1
#define mmMMEA1_GMI_RD_PRI_URGENCY 0x03ea
#define mmMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX 1
#define mmMMEA1_GMI_WR_PRI_URGENCY 0x03eb
#define mmMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX 1
#define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING 0x03ec
#define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1
#define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING 0x03ed
#define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1
#define mmMMEA1_GMI_RD_PRI_QUANT_PRI1 0x03ee
#define mmMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA1_GMI_RD_PRI_QUANT_PRI2 0x03ef
#define mmMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA1_GMI_RD_PRI_QUANT_PRI3 0x03f0
#define mmMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA1_GMI_WR_PRI_QUANT_PRI1 0x03f1
#define mmMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA1_GMI_WR_PRI_QUANT_PRI2 0x03f2
#define mmMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA1_GMI_WR_PRI_QUANT_PRI3 0x03f3
#define mmMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA1_ADDRNORM_BASE_ADDR0 0x03f4
#define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 1
#define mmMMEA1_ADDRNORM_LIMIT_ADDR0 0x03f5
#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1
#define mmMMEA1_ADDRNORM_BASE_ADDR1 0x03f6
#define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 1
#define mmMMEA1_ADDRNORM_LIMIT_ADDR1 0x03f7
#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1
#define mmMMEA1_ADDRNORM_OFFSET_ADDR1 0x03f8
#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1
#define mmMMEA1_ADDRNORM_BASE_ADDR2 0x03f9
#define mmMMEA1_ADDRNORM_BASE_ADDR2_BASE_IDX 1
#define mmMMEA1_ADDRNORM_LIMIT_ADDR2 0x03fa
#define mmMMEA1_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1
#define mmMMEA1_ADDRNORM_BASE_ADDR3 0x03fb
#define mmMMEA1_ADDRNORM_BASE_ADDR3_BASE_IDX 1
#define mmMMEA1_ADDRNORM_LIMIT_ADDR3 0x03fc
#define mmMMEA1_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1
#define mmMMEA1_ADDRNORM_OFFSET_ADDR3 0x03fd
#define mmMMEA1_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1
#define mmMMEA1_ADDRNORM_BASE_ADDR4 0x03fe
#define mmMMEA1_ADDRNORM_BASE_ADDR4_BASE_IDX 1
#define mmMMEA1_ADDRNORM_LIMIT_ADDR4 0x03ff
#define mmMMEA1_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1
#define mmMMEA1_ADDRNORM_BASE_ADDR5 0x0400
#define mmMMEA1_ADDRNORM_BASE_ADDR5_BASE_IDX 1
#define mmMMEA1_ADDRNORM_LIMIT_ADDR5 0x0401
#define mmMMEA1_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1
#define mmMMEA1_ADDRNORM_OFFSET_ADDR5 0x0402
#define mmMMEA1_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1
#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL 0x0403
#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1
#define mmMMEA1_ADDRNORMGMI_HOLE_CNTL 0x0404
#define mmMMEA1_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1
#define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0405
#define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1
#define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0406
#define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1
#define mmMMEA1_ADDRDEC_BANK_CFG 0x0407
#define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 1
#define mmMMEA1_ADDRDEC_MISC_CFG 0x0408
#define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 1
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0x0409
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0x040a
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0x040b
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0x040c
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0x040d
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5 0x040e
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0x040f
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0x0410
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0x0411
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0x0412
#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1
#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x0413
#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0 0x0414
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1 0x0415
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2 0x0416
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3 0x0417
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4 0x0418
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5 0x0419
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC 0x041a
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2 0x041b
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0 0x041c
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1 0x041d
#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1
#define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE 0x041e
#define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x041f
#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x0420
#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x0421
#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x0422
#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x0423
#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x0424
#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x0425
#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x0426
#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x0427
#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x0428
#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x0429
#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x042a
#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x042b
#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x042c
#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x042d
#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x042e
#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01 0x042f
#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23 0x0430
#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x0431
#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x0432
#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x0433
#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x0434
#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_RM_SEL_CS01 0x0435
#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_RM_SEL_CS23 0x0436
#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x0437
#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x0438
#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x0439
#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x043a
#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x043b
#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x043c
#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x043d
#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x043e
#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x043f
#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x0440
#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x0441
#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x0442
#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x0443
#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x0444
#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x0445
#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x0446
#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x0447
#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x0448
#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01 0x0449
#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23 0x044a
#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x044b
#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x044c
#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x044d
#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x044e
#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_RM_SEL_CS01 0x044f
#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_RM_SEL_CS23 0x0450
#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x0451
#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x0452
#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0 0x0453
#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1 0x0454
#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2 0x0455
#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3 0x0456
#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 0x0457
#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 0x0458
#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 0x0459
#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 0x045a
#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01 0x045b
#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23 0x045c
#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 0x045d
#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 0x045e
#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01 0x045f
#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23 0x0460
#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01 0x0461
#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23 0x0462
#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01 0x0463
#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23 0x0464
#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01 0x0465
#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23 0x0466
#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01 0x0467
#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23 0x0468
#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_RM_SEL_CS01 0x0469
#define mmMMEA1_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_RM_SEL_CS23 0x046a
#define mmMMEA1_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01 0x046b
#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1
#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23 0x046c
#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1
#define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL 0x046d
#define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1
#define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL 0x046e
#define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1
#define mmMMEA1_IO_RD_CLI2GRP_MAP0 0x0495
#define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA1_IO_RD_CLI2GRP_MAP1 0x0496
#define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA1_IO_WR_CLI2GRP_MAP0 0x0497
#define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA1_IO_WR_CLI2GRP_MAP1 0x0498
#define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA1_IO_RD_COMBINE_FLUSH 0x0499
#define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 1
#define mmMMEA1_IO_WR_COMBINE_FLUSH 0x049a
#define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 1
#define mmMMEA1_IO_GROUP_BURST 0x049b
#define mmMMEA1_IO_GROUP_BURST_BASE_IDX 1
#define mmMMEA1_IO_RD_PRI_AGE 0x049c
#define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX 1
#define mmMMEA1_IO_WR_PRI_AGE 0x049d
#define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX 1
#define mmMMEA1_IO_RD_PRI_QUEUING 0x049e
#define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 1
#define mmMMEA1_IO_WR_PRI_QUEUING 0x049f
#define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 1
#define mmMMEA1_IO_RD_PRI_FIXED 0x04a0
#define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX 1
#define mmMMEA1_IO_WR_PRI_FIXED 0x04a1
#define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX 1
#define mmMMEA1_IO_RD_PRI_URGENCY 0x04a2
#define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 1
#define mmMMEA1_IO_WR_PRI_URGENCY 0x04a3
#define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 1
#define mmMMEA1_IO_RD_PRI_URGENCY_MASKING 0x04a4
#define mmMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1
#define mmMMEA1_IO_WR_PRI_URGENCY_MASKING 0x04a5
#define mmMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1
#define mmMMEA1_IO_RD_PRI_QUANT_PRI1 0x04a6
#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA1_IO_RD_PRI_QUANT_PRI2 0x04a7
#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA1_IO_RD_PRI_QUANT_PRI3 0x04a8
#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA1_IO_WR_PRI_QUANT_PRI1 0x04a9
#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA1_IO_WR_PRI_QUANT_PRI2 0x04aa
#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA1_IO_WR_PRI_QUANT_PRI3 0x04ab
#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA1_SDP_ARB_DRAM 0x04ac
#define mmMMEA1_SDP_ARB_DRAM_BASE_IDX 1
#define mmMMEA1_SDP_ARB_GMI 0x04ad
#define mmMMEA1_SDP_ARB_GMI_BASE_IDX 1
#define mmMMEA1_SDP_ARB_FINAL 0x04ae
#define mmMMEA1_SDP_ARB_FINAL_BASE_IDX 1
#define mmMMEA1_SDP_DRAM_PRIORITY 0x04af
#define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 1
#define mmMMEA1_SDP_GMI_PRIORITY 0x04b0
#define mmMMEA1_SDP_GMI_PRIORITY_BASE_IDX 1
#define mmMMEA1_SDP_IO_PRIORITY 0x04b1
#define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX 1
#define mmMMEA1_SDP_CREDITS 0x04b2
#define mmMMEA1_SDP_CREDITS_BASE_IDX 1
#define mmMMEA1_SDP_TAG_RESERVE0 0x04b3
#define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX 1
#define mmMMEA1_SDP_TAG_RESERVE1 0x04b4
#define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX 1
#define mmMMEA1_SDP_VCC_RESERVE0 0x04b5
#define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX 1
#define mmMMEA1_SDP_VCC_RESERVE1 0x04b6
#define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX 1
#define mmMMEA1_SDP_VCD_RESERVE0 0x04b7
#define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX 1
#define mmMMEA1_SDP_VCD_RESERVE1 0x04b8
#define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX 1
#define mmMMEA1_SDP_REQ_CNTL 0x04b9
#define mmMMEA1_SDP_REQ_CNTL_BASE_IDX 1
#define mmMMEA1_MISC 0x04ba
#define mmMMEA1_MISC_BASE_IDX 1
#define mmMMEA1_LATENCY_SAMPLING 0x04bb
#define mmMMEA1_LATENCY_SAMPLING_BASE_IDX 1
#define mmMMEA1_PERFCOUNTER_LO 0x04bc
#define mmMMEA1_PERFCOUNTER_LO_BASE_IDX 1
#define mmMMEA1_PERFCOUNTER_HI 0x04bd
#define mmMMEA1_PERFCOUNTER_HI_BASE_IDX 1
#define mmMMEA1_PERFCOUNTER0_CFG 0x04be
#define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX 1
#define mmMMEA1_PERFCOUNTER1_CFG 0x04bf
#define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX 1
#define mmMMEA1_PERFCOUNTER_RSLT_CNTL 0x04c0
#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
#define mmMMEA1_EDC_CNT 0x04c6
#define mmMMEA1_EDC_CNT_BASE_IDX 1
#define mmMMEA1_EDC_CNT2 0x04c7
#define mmMMEA1_EDC_CNT2_BASE_IDX 1
#define mmMMEA1_DSM_CNTL 0x04c8
#define mmMMEA1_DSM_CNTL_BASE_IDX 1
#define mmMMEA1_DSM_CNTLA 0x04c9
#define mmMMEA1_DSM_CNTLA_BASE_IDX 1
#define mmMMEA1_DSM_CNTLB 0x04ca
#define mmMMEA1_DSM_CNTLB_BASE_IDX 1
#define mmMMEA1_DSM_CNTL2 0x04cb
#define mmMMEA1_DSM_CNTL2_BASE_IDX 1
#define mmMMEA1_DSM_CNTL2A 0x04cc
#define mmMMEA1_DSM_CNTL2A_BASE_IDX 1
#define mmMMEA1_DSM_CNTL2B 0x04cd
#define mmMMEA1_DSM_CNTL2B_BASE_IDX 1
#define mmMMEA1_CGTT_CLK_CTRL 0x04cf
#define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX 1
#define mmMMEA1_EDC_MODE 0x04d0
#define mmMMEA1_EDC_MODE_BASE_IDX 1
#define mmMMEA1_ERR_STATUS 0x04d1
#define mmMMEA1_ERR_STATUS_BASE_IDX 1
#define mmMMEA1_MISC2 0x04d2
#define mmMMEA1_MISC2_BASE_IDX 1
#define mmMMEA1_ADDRDEC_SELECT 0x04d3
#define mmMMEA1_ADDRDEC_SELECT_BASE_IDX 1
#define mmMMEA1_EDC_CNT3 0x04d4
#define mmMMEA1_EDC_CNT3_BASE_IDX 1
// addressBlock: mmhub_ea_mmeadec2
// base address: 0x69400
#define mmMMEA2_DRAM_RD_CLI2GRP_MAP0 0x0500
#define mmMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA2_DRAM_RD_CLI2GRP_MAP1 0x0501
#define mmMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA2_DRAM_WR_CLI2GRP_MAP0 0x0502
#define mmMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA2_DRAM_WR_CLI2GRP_MAP1 0x0503
#define mmMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA2_DRAM_RD_GRP2VC_MAP 0x0504
#define mmMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX 1
#define mmMMEA2_DRAM_WR_GRP2VC_MAP 0x0505
#define mmMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX 1
#define mmMMEA2_DRAM_RD_LAZY 0x0506
#define mmMMEA2_DRAM_RD_LAZY_BASE_IDX 1
#define mmMMEA2_DRAM_WR_LAZY 0x0507
#define mmMMEA2_DRAM_WR_LAZY_BASE_IDX 1
#define mmMMEA2_DRAM_RD_CAM_CNTL 0x0508
#define mmMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX 1
#define mmMMEA2_DRAM_WR_CAM_CNTL 0x0509
#define mmMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX 1
#define mmMMEA2_DRAM_PAGE_BURST 0x050a
#define mmMMEA2_DRAM_PAGE_BURST_BASE_IDX 1
#define mmMMEA2_DRAM_RD_PRI_AGE 0x050b
#define mmMMEA2_DRAM_RD_PRI_AGE_BASE_IDX 1
#define mmMMEA2_DRAM_WR_PRI_AGE 0x050c
#define mmMMEA2_DRAM_WR_PRI_AGE_BASE_IDX 1
#define mmMMEA2_DRAM_RD_PRI_QUEUING 0x050d
#define mmMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX 1
#define mmMMEA2_DRAM_WR_PRI_QUEUING 0x050e
#define mmMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX 1
#define mmMMEA2_DRAM_RD_PRI_FIXED 0x050f
#define mmMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX 1
#define mmMMEA2_DRAM_WR_PRI_FIXED 0x0510
#define mmMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX 1
#define mmMMEA2_DRAM_RD_PRI_URGENCY 0x0511
#define mmMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX 1
#define mmMMEA2_DRAM_WR_PRI_URGENCY 0x0512
#define mmMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX 1
#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1 0x0513
#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2 0x0514
#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3 0x0515
#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1 0x0516
#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2 0x0517
#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3 0x0518
#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA2_GMI_RD_CLI2GRP_MAP0 0x0519
#define mmMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA2_GMI_RD_CLI2GRP_MAP1 0x051a
#define mmMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA2_GMI_WR_CLI2GRP_MAP0 0x051b
#define mmMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1
#define mmMMEA2_GMI_WR_CLI2GRP_MAP1 0x051c
#define mmMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1
#define mmMMEA2_GMI_RD_GRP2VC_MAP 0x051d
#define mmMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX 1
#define mmMMEA2_GMI_WR_GRP2VC_MAP 0x051e
#define mmMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX 1
#define mmMMEA2_GMI_RD_LAZY 0x051f
#define mmMMEA2_GMI_RD_LAZY_BASE_IDX 1
#define mmMMEA2_GMI_WR_LAZY 0x0520
#define mmMMEA2_GMI_WR_LAZY_BASE_IDX 1
#define mmMMEA2_GMI_RD_CAM_CNTL 0x0521
#define mmMMEA2_GMI_RD_CAM_CNTL_BASE_IDX 1
#define mmMMEA2_GMI_WR_CAM_CNTL 0x0522
#define mmMMEA2_GMI_WR_CAM_CNTL_BASE_IDX 1
#define mmMMEA2_GMI_PAGE_BURST 0x0523
#define mmMMEA2_GMI_PAGE_BURST_BASE_IDX 1
#define mmMMEA2_GMI_RD_PRI_AGE 0x0524
#define mmMMEA2_GMI_RD_PRI_AGE_BASE_IDX 1
#define mmMMEA2_GMI_WR_PRI_AGE 0x0525
#define mmMMEA2_GMI_WR_PRI_AGE_BASE_IDX 1
#define mmMMEA2_GMI_RD_PRI_QUEUING 0x0526
#define mmMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX 1
#define mmMMEA2_GMI_WR_PRI_QUEUING 0x0527
#define mmMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX 1
#define mmMMEA2_GMI_RD_PRI_FIXED 0x0528
#define mmMMEA2_GMI_RD_PRI_FIXED_BASE_IDX 1
#define mmMMEA2_GMI_WR_PRI_FIXED 0x0529
#define mmMMEA2_GMI_WR_PRI_FIXED_BASE_IDX 1
#define mmMMEA2_GMI_RD_PRI_URGENCY 0x052a
#define mmMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX 1
#define mmMMEA2_GMI_WR_PRI_URGENCY 0x052b
#define mmMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX 1
#define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING 0x052c
#define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1
#define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING 0x052d
#define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1
#define mmMMEA2_GMI_RD_PRI_QUANT_PRI1 0x052e
#define mmMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA2_GMI_RD_PRI_QUANT_PRI2 0x052f
#define mmMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA2_GMI_RD_PRI_QUANT_PRI3 0x0530
#define mmMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA2_GMI_WR_PRI_QUANT_PRI1 0x0531
#define mmMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1
#define mmMMEA2_GMI_WR_PRI_QUANT_PRI2 0x0532
#define mmMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1
#define mmMMEA2_GMI_WR_PRI_QUANT_PRI3 0x0533
#define mmMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1
#define mmMMEA2_ADDRNORM_BASE_ADDR0 0x0534
#define mmMMEA2_ADDRNORM_BASE_ADDR0_BASE_IDX 1
#define mmMMEA2_ADDRNORM_LIMIT_ADDR0 0x0535
#define mmMMEA2_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1
#define mmMMEA2_ADDRNORM_BASE_ADDR1 0x0536
#define mmMMEA2_ADDRNORM_BASE_ADDR1_BASE_IDX 1
#define mmMMEA2_ADDRNORM_LIMIT_ADDR1 0x0537
#define mmMMEA2_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1
#define mmMMEA2_ADDRNORM_OFFSET_ADDR1 0x0538
#define mmMMEA2_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1
#define mmMMEA2_ADDRNORM_BASE_ADDR2 0x0539
#define mmMMEA2_ADDRNORM_BASE_ADDR2_BASE_IDX 1
#define mmMMEA2_ADDRNORM_LIMIT_ADDR2 0x053a
#define mmMMEA2_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1
#define mmMMEA2_ADDRNORM_BASE_ADDR3 0x053b
#define mmMMEA2_ADDRNORM_BASE_ADDR3_BASE_IDX 1
#define mmMMEA2_ADDRNORM_LIMIT_ADDR3 0x053c
#define mmMMEA2_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1
#define mmMMEA2_ADDRNORM_OFFSET_ADDR3 0x053d
#define mmMMEA2_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1
#define mmMMEA2_ADDRNORM_BASE_ADDR4 0x053e
#define mmMMEA2_ADDRNORM_BASE_ADDR4_BASE_IDX 1
#define mmMMEA2_ADDRNORM_LIMIT_ADDR4 0x053f
#define mmMMEA2_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1
#define mmMMEA2_ADDRNORM_BASE_ADDR5 0x0540
#define mmMMEA2_ADDRNORM_BASE_ADDR5_BASE_IDX 1
#define mmMMEA2_ADDRNORM_LIMIT_ADDR5 0x0541
#define mmMMEA2_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1
#define mmMMEA2_ADDRNORM_OFFSET_ADDR5 0x0542
#define mmMMEA2_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1
#define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL 0x0543
#define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1
#define mmMMEA2_ADDRNORMGMI_HOLE_CNTL 0x0544
#define mmMMEA2_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1
#define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0545
#define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1
#define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0546
#define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1
#define mmMMEA2_ADDRDEC_BANK_CFG 0x0547
#define mmMMEA2_ADDRDEC_BANK_CFG_BASE_IDX 1
#define mmMMEA2_ADDRDEC_MISC_CFG 0x0548
#define mmMMEA2_ADDRDEC_MISC_CFG_BASE_IDX 1
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0 0x0549
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1 0x054a
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2 0x054b
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3 0x054c
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4 0x054d
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5 0x054e
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC 0x054f
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2 0x0550
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0 0x0551
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1 0x0552
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1
#define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE 0x0553
#define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0 0x0554
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1 0x0555
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2 0x0556
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3 0x0557
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4 0x0558
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5 0x0559
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC 0x055a
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2 0x055b
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0 0x055c
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1 0x055d
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1
#define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE 0x055e
#define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0 0x055f
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1 0x0560
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2 0x0561
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3 0x0562
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0 0x0563
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1 0x0564
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2 0x0565
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3 0x0566
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01 0x0567
#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23 0x0568
#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01 0x0569
#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23 0x056a
#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01 0x056b
#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23 0x056c
#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01 0x056d
#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23 0x056e
#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01 0x056f
#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23 0x0570
#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01 0x0571
#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23 0x0572
#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01 0x0573
#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23 0x0574
#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_RM_SEL_CS01 0x0575
#define mmMMEA2_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_RM_SEL_CS23 0x0576
#define mmMMEA2_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01 0x0577
#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23 0x0578
#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0 0x0579
#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1 0x057a
#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2 0x057b
#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3 0x057c
#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0 0x057d
#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1 0x057e
#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2 0x057f
#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3 0x0580
#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01 0x0581
#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23 0x0582
#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01 0x0583
#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23 0x0584
#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01 0x0585
#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23 0x0586
#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01 0x0587
#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23 0x0588
#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01 0x0589
#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23 0x058a
#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01 0x058b
#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23 0x058c
#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01 0x058d
#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23 0x058e
#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_RM_SEL_CS01 0x058f
#define mmMMEA2_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_RM_SEL_CS23 0x0590
#define mmMMEA2_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01 0x0591
#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23 0x0592
#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0 0x0593
#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1 0x0594
#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2 0x0595
#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3 0x0596
#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0 0x0597
#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1 0x0598
#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2 0x0599
#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3 0x059a
#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01 0x059b
#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23 0x059c
#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01 0x059d
#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23 0x059e
#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01 0x059f
#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23 0x05a0
#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01 0x05a1
#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23 0x05a2
#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01 0x05a3
#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23 0x05a4
#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01 0x05a5
#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23 0x05a6
#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01 0x05a7
#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23 0x05a8
#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_RM_SEL_CS01 0x05a9
#define mmMMEA2_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_RM_SEL_CS23 0x05aa
#define mmMMEA2_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01 0x05ab
#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1
#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23 0x05ac
#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1
#define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL 0x05ad
#define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1
#define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL 0x05ae
#define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1
#define mmMMEA2_IO_RD_CLI2GRP_MAP0 0x05d5
#define mmMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX 1
#define