| /* |
| * Copyright (C) 2017 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included |
| * in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef _sdma1_4_0_OFFSET_HEADER |
| #define _sdma1_4_0_OFFSET_HEADER |
| |
| |
| |
| // addressBlock: sdma1_sdma1dec |
| // base address: 0x5180 |
| #define mmSDMA1_UCODE_ADDR 0x0000 |
| #define mmSDMA1_UCODE_ADDR_BASE_IDX 0 |
| #define mmSDMA1_UCODE_DATA 0x0001 |
| #define mmSDMA1_UCODE_DATA_BASE_IDX 0 |
| #define mmSDMA1_VM_CNTL 0x0004 |
| #define mmSDMA1_VM_CNTL_BASE_IDX 0 |
| #define mmSDMA1_VM_CTX_LO 0x0005 |
| #define mmSDMA1_VM_CTX_LO_BASE_IDX 0 |
| #define mmSDMA1_VM_CTX_HI 0x0006 |
| #define mmSDMA1_VM_CTX_HI_BASE_IDX 0 |
| #define mmSDMA1_ACTIVE_FCN_ID 0x0007 |
| #define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0 |
| #define mmSDMA1_VM_CTX_CNTL 0x0008 |
| #define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0 |
| #define mmSDMA1_VIRT_RESET_REQ 0x0009 |
| #define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0 |
| #define mmSDMA1_VF_ENABLE 0x000a |
| #define mmSDMA1_VF_ENABLE_BASE_IDX 0 |
| #define mmSDMA1_CONTEXT_REG_TYPE0 0x000b |
| #define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0 |
| #define mmSDMA1_CONTEXT_REG_TYPE1 0x000c |
| #define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0 |
| #define mmSDMA1_CONTEXT_REG_TYPE2 0x000d |
| #define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0 |
| #define mmSDMA1_CONTEXT_REG_TYPE3 0x000e |
| #define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0 |
| #define mmSDMA1_PUB_REG_TYPE0 0x000f |
| #define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0 |
| #define mmSDMA1_PUB_REG_TYPE1 0x0010 |
| #define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0 |
| #define mmSDMA1_PUB_REG_TYPE2 0x0011 |
| #define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0 |
| #define mmSDMA1_PUB_REG_TYPE3 0x0012 |
| #define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0 |
| #define mmSDMA1_MMHUB_CNTL 0x0013 |
| #define mmSDMA1_MMHUB_CNTL_BASE_IDX 0 |
| #define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019 |
| #define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 |
| #define mmSDMA1_POWER_CNTL 0x001a |
| #define mmSDMA1_POWER_CNTL_BASE_IDX 0 |
| #define mmSDMA1_CLK_CTRL 0x001b |
| #define mmSDMA1_CLK_CTRL_BASE_IDX 0 |
| #define mmSDMA1_CNTL 0x001c |
| #define mmSDMA1_CNTL_BASE_IDX 0 |
| #define mmSDMA1_CHICKEN_BITS 0x001d |
| #define mmSDMA1_CHICKEN_BITS_BASE_IDX 0 |
| #define mmSDMA1_GB_ADDR_CONFIG 0x001e |
| #define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 |
| #define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f |
| #define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 |
| #define mmSDMA1_RB_RPTR_FETCH_HI 0x0020 |
| #define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 |
| #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 |
| #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RB_RPTR_FETCH 0x0022 |
| #define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0 |
| #define mmSDMA1_IB_OFFSET_FETCH 0x0023 |
| #define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 |
| #define mmSDMA1_PROGRAM 0x0024 |
| #define mmSDMA1_PROGRAM_BASE_IDX 0 |
| #define mmSDMA1_STATUS_REG 0x0025 |
| #define mmSDMA1_STATUS_REG_BASE_IDX 0 |
| #define mmSDMA1_STATUS1_REG 0x0026 |
| #define mmSDMA1_STATUS1_REG_BASE_IDX 0 |
| #define mmSDMA1_RD_BURST_CNTL 0x0027 |
| #define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0 |
| #define mmSDMA1_HBM_PAGE_CONFIG 0x0028 |
| #define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 |
| #define mmSDMA1_UCODE_CHECKSUM 0x0029 |
| #define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0 |
| #define mmSDMA1_F32_CNTL 0x002a |
| #define mmSDMA1_F32_CNTL_BASE_IDX 0 |
| #define mmSDMA1_FREEZE 0x002b |
| #define mmSDMA1_FREEZE_BASE_IDX 0 |
| #define mmSDMA1_PHASE0_QUANTUM 0x002c |
| #define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0 |
| #define mmSDMA1_PHASE1_QUANTUM 0x002d |
| #define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0 |
| #define mmSDMA1_EDC_CONFIG 0x0032 |
| #define mmSDMA1_EDC_CONFIG_BASE_IDX 0 |
| #define mmSDMA1_BA_THRESHOLD 0x0033 |
| #define mmSDMA1_BA_THRESHOLD_BASE_IDX 0 |
| #define mmSDMA1_ID 0x0034 |
| #define mmSDMA1_ID_BASE_IDX 0 |
| #define mmSDMA1_VERSION 0x0035 |
| #define mmSDMA1_VERSION_BASE_IDX 0 |
| #define mmSDMA1_EDC_COUNTER 0x0036 |
| #define mmSDMA1_EDC_COUNTER_BASE_IDX 0 |
| #define mmSDMA1_EDC_COUNTER_CLEAR 0x0037 |
| #define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 |
| #define mmSDMA1_STATUS2_REG 0x0038 |
| #define mmSDMA1_STATUS2_REG_BASE_IDX 0 |
| #define mmSDMA1_ATOMIC_CNTL 0x0039 |
| #define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0 |
| #define mmSDMA1_ATOMIC_PREOP_LO 0x003a |
| #define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 |
| #define mmSDMA1_ATOMIC_PREOP_HI 0x003b |
| #define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_CNTL 0x003c |
| #define mmSDMA1_UTCL1_CNTL_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_WATERMK 0x003d |
| #define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_RD_STATUS 0x003e |
| #define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_WR_STATUS 0x003f |
| #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_INV0 0x0040 |
| #define mmSDMA1_UTCL1_INV0_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_INV1 0x0041 |
| #define mmSDMA1_UTCL1_INV1_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_INV2 0x0042 |
| #define mmSDMA1_UTCL1_INV2_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_RD_XNACK0 0x0043 |
| #define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_RD_XNACK1 0x0044 |
| #define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_WR_XNACK0 0x0045 |
| #define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_WR_XNACK1 0x0046 |
| #define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_TIMEOUT 0x0047 |
| #define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 |
| #define mmSDMA1_UTCL1_PAGE 0x0048 |
| #define mmSDMA1_UTCL1_PAGE_BASE_IDX 0 |
| #define mmSDMA1_POWER_CNTL_IDLE 0x0049 |
| #define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 |
| #define mmSDMA1_RELAX_ORDERING_LUT 0x004a |
| #define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 |
| #define mmSDMA1_CHICKEN_BITS_2 0x004b |
| #define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0 |
| #define mmSDMA1_STATUS3_REG 0x004c |
| #define mmSDMA1_STATUS3_REG_BASE_IDX 0 |
| #define mmSDMA1_PHYSICAL_ADDR_LO 0x004d |
| #define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_PHYSICAL_ADDR_HI 0x004e |
| #define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_PHASE2_QUANTUM 0x004f |
| #define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0 |
| #define mmSDMA1_ERROR_LOG 0x0050 |
| #define mmSDMA1_ERROR_LOG_BASE_IDX 0 |
| #define mmSDMA1_PUB_DUMMY_REG0 0x0051 |
| #define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 |
| #define mmSDMA1_PUB_DUMMY_REG1 0x0052 |
| #define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 |
| #define mmSDMA1_PUB_DUMMY_REG2 0x0053 |
| #define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 |
| #define mmSDMA1_PUB_DUMMY_REG3 0x0054 |
| #define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 |
| #define mmSDMA1_F32_COUNTER 0x0055 |
| #define mmSDMA1_F32_COUNTER_BASE_IDX 0 |
| #define mmSDMA1_UNBREAKABLE 0x0056 |
| #define mmSDMA1_UNBREAKABLE_BASE_IDX 0 |
| #define mmSDMA1_PERFMON_CNTL 0x0057 |
| #define mmSDMA1_PERFMON_CNTL_BASE_IDX 0 |
| #define mmSDMA1_PERFCOUNTER0_RESULT 0x0058 |
| #define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0 |
| #define mmSDMA1_PERFCOUNTER1_RESULT 0x0059 |
| #define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0 |
| #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a |
| #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 |
| #define mmSDMA1_CRD_CNTL 0x005b |
| #define mmSDMA1_CRD_CNTL_BASE_IDX 0 |
| #define mmSDMA1_MMHUB_TRUSTLVL 0x005c |
| #define mmSDMA1_MMHUB_TRUSTLVL_BASE_IDX 0 |
| #define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d |
| #define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 |
| #define mmSDMA1_ULV_CNTL 0x005e |
| #define mmSDMA1_ULV_CNTL_BASE_IDX 0 |
| #define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060 |
| #define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 |
| #define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061 |
| #define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_CNTL 0x0080 |
| #define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_BASE 0x0081 |
| #define mmSDMA1_GFX_RB_BASE_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_BASE_HI 0x0082 |
| #define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_RPTR 0x0083 |
| #define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_RPTR_HI 0x0084 |
| #define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_WPTR 0x0085 |
| #define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_WPTR_HI 0x0086 |
| #define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087 |
| #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088 |
| #define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089 |
| #define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_GFX_IB_CNTL 0x008a |
| #define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0 |
| #define mmSDMA1_GFX_IB_RPTR 0x008b |
| #define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0 |
| #define mmSDMA1_GFX_IB_OFFSET 0x008c |
| #define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0 |
| #define mmSDMA1_GFX_IB_BASE_LO 0x008d |
| #define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 |
| #define mmSDMA1_GFX_IB_BASE_HI 0x008e |
| #define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 |
| #define mmSDMA1_GFX_IB_SIZE 0x008f |
| #define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0 |
| #define mmSDMA1_GFX_SKIP_CNTL 0x0090 |
| #define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 |
| #define mmSDMA1_GFX_CONTEXT_STATUS 0x0091 |
| #define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 |
| #define mmSDMA1_GFX_DOORBELL 0x0092 |
| #define mmSDMA1_GFX_DOORBELL_BASE_IDX 0 |
| #define mmSDMA1_GFX_CONTEXT_CNTL 0x0093 |
| #define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 |
| #define mmSDMA1_GFX_STATUS 0x00a8 |
| #define mmSDMA1_GFX_STATUS_BASE_IDX 0 |
| #define mmSDMA1_GFX_DOORBELL_LOG 0x00a9 |
| #define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 |
| #define mmSDMA1_GFX_WATERMARK 0x00aa |
| #define mmSDMA1_GFX_WATERMARK_BASE_IDX 0 |
| #define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab |
| #define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 |
| #define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac |
| #define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad |
| #define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af |
| #define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 |
| #define mmSDMA1_GFX_PREEMPT 0x00b0 |
| #define mmSDMA1_GFX_PREEMPT_BASE_IDX 0 |
| #define mmSDMA1_GFX_DUMMY_REG 0x00b1 |
| #define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 |
| #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 |
| #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4 |
| #define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 |
| #define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5 |
| #define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 |
| #define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0 |
| #define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 |
| #define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1 |
| #define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 |
| #define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2 |
| #define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 |
| #define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3 |
| #define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 |
| #define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4 |
| #define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 |
| #define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5 |
| #define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 |
| #define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6 |
| #define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 |
| #define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7 |
| #define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 |
| #define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8 |
| #define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 |
| #define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9 |
| #define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_CNTL 0x00e0 |
| #define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_BASE 0x00e1 |
| #define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_BASE_HI 0x00e2 |
| #define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_RPTR 0x00e3 |
| #define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4 |
| #define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_WPTR 0x00e5 |
| #define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6 |
| #define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7 |
| #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8 |
| #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9 |
| #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_PAGE_IB_CNTL 0x00ea |
| #define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0 |
| #define mmSDMA1_PAGE_IB_RPTR 0x00eb |
| #define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0 |
| #define mmSDMA1_PAGE_IB_OFFSET 0x00ec |
| #define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 |
| #define mmSDMA1_PAGE_IB_BASE_LO 0x00ed |
| #define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 |
| #define mmSDMA1_PAGE_IB_BASE_HI 0x00ee |
| #define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 |
| #define mmSDMA1_PAGE_IB_SIZE 0x00ef |
| #define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0 |
| #define mmSDMA1_PAGE_SKIP_CNTL 0x00f0 |
| #define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 |
| #define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1 |
| #define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 |
| #define mmSDMA1_PAGE_DOORBELL 0x00f2 |
| #define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0 |
| #define mmSDMA1_PAGE_STATUS 0x0108 |
| #define mmSDMA1_PAGE_STATUS_BASE_IDX 0 |
| #define mmSDMA1_PAGE_DOORBELL_LOG 0x0109 |
| #define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 |
| #define mmSDMA1_PAGE_WATERMARK 0x010a |
| #define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0 |
| #define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b |
| #define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 |
| #define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c |
| #define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d |
| #define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f |
| #define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 |
| #define mmSDMA1_PAGE_PREEMPT 0x0110 |
| #define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0 |
| #define mmSDMA1_PAGE_DUMMY_REG 0x0111 |
| #define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 |
| #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 |
| #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114 |
| #define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 |
| #define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115 |
| #define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 |
| #define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120 |
| #define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 |
| #define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121 |
| #define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 |
| #define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122 |
| #define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 |
| #define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123 |
| #define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 |
| #define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124 |
| #define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 |
| #define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125 |
| #define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 |
| #define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126 |
| #define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 |
| #define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127 |
| #define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 |
| #define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128 |
| #define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 |
| #define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129 |
| #define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_CNTL 0x0140 |
| #define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_BASE 0x0141 |
| #define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_BASE_HI 0x0142 |
| #define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_RPTR 0x0143 |
| #define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_RPTR_HI 0x0144 |
| #define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_WPTR 0x0145 |
| #define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_WPTR_HI 0x0146 |
| #define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147 |
| #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148 |
| #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149 |
| #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_RLC0_IB_CNTL 0x014a |
| #define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RLC0_IB_RPTR 0x014b |
| #define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0 |
| #define mmSDMA1_RLC0_IB_OFFSET 0x014c |
| #define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 |
| #define mmSDMA1_RLC0_IB_BASE_LO 0x014d |
| #define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 |
| #define mmSDMA1_RLC0_IB_BASE_HI 0x014e |
| #define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC0_IB_SIZE 0x014f |
| #define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0 |
| #define mmSDMA1_RLC0_SKIP_CNTL 0x0150 |
| #define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151 |
| #define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 |
| #define mmSDMA1_RLC0_DOORBELL 0x0152 |
| #define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0 |
| #define mmSDMA1_RLC0_STATUS 0x0168 |
| #define mmSDMA1_RLC0_STATUS_BASE_IDX 0 |
| #define mmSDMA1_RLC0_DOORBELL_LOG 0x0169 |
| #define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 |
| #define mmSDMA1_RLC0_WATERMARK 0x016a |
| #define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0 |
| #define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b |
| #define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 |
| #define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c |
| #define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d |
| #define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f |
| #define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 |
| #define mmSDMA1_RLC0_PREEMPT 0x0170 |
| #define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0 |
| #define mmSDMA1_RLC0_DUMMY_REG 0x0171 |
| #define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 |
| #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 |
| #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174 |
| #define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175 |
| #define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 |
| #define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180 |
| #define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 |
| #define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181 |
| #define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 |
| #define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182 |
| #define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 |
| #define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183 |
| #define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 |
| #define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184 |
| #define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 |
| #define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185 |
| #define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 |
| #define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186 |
| #define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 |
| #define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187 |
| #define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 |
| #define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188 |
| #define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 |
| #define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189 |
| #define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_CNTL 0x01a0 |
| #define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_BASE 0x01a1 |
| #define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_BASE_HI 0x01a2 |
| #define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_RPTR 0x01a3 |
| #define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4 |
| #define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_WPTR 0x01a5 |
| #define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6 |
| #define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7 |
| #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8 |
| #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9 |
| #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_RLC1_IB_CNTL 0x01aa |
| #define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RLC1_IB_RPTR 0x01ab |
| #define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0 |
| #define mmSDMA1_RLC1_IB_OFFSET 0x01ac |
| #define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 |
| #define mmSDMA1_RLC1_IB_BASE_LO 0x01ad |
| #define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 |
| #define mmSDMA1_RLC1_IB_BASE_HI 0x01ae |
| #define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC1_IB_SIZE 0x01af |
| #define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0 |
| #define mmSDMA1_RLC1_SKIP_CNTL 0x01b0 |
| #define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1 |
| #define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 |
| #define mmSDMA1_RLC1_DOORBELL 0x01b2 |
| #define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0 |
| #define mmSDMA1_RLC1_STATUS 0x01c8 |
| #define mmSDMA1_RLC1_STATUS_BASE_IDX 0 |
| #define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9 |
| #define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 |
| #define mmSDMA1_RLC1_WATERMARK 0x01ca |
| #define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0 |
| #define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb |
| #define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 |
| #define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc |
| #define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd |
| #define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf |
| #define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 |
| #define mmSDMA1_RLC1_PREEMPT 0x01d0 |
| #define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0 |
| #define mmSDMA1_RLC1_DUMMY_REG 0x01d1 |
| #define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 |
| #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 |
| #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
| #define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4 |
| #define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 |
| #define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5 |
| #define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 |
| #define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0 |
| #define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 |
| #define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1 |
| #define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 |
| #define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2 |
| #define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 |
| #define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3 |
| #define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 |
| #define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4 |
| #define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 |
| #define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5 |
| #define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 |
| #define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6 |
| #define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 |
| #define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7 |
| #define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 |
| #define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8 |
| #define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 |
| #define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9 |
| #define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 |
| |
| #endif |
