blob: cd7893065a4b3c25b7c503de089c21b381a1a946 [file] [log] [blame]
/*
* SMU_7_1_0 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef SMU_7_1_0_SH_MASK_H
#define SMU_7_1_0_SH_MASK_H
#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00
#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
#define SMC_RESP_0__SMC_RESP_MASK 0xffff
#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
#define SMC_RESP_1__SMC_RESP_MASK 0xffff
#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
#define SMC_RESP_2__SMC_RESP_MASK 0xffff
#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
#define SMC_RESP_3__SMC_RESP_MASK 0xffff
#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
#define SMC_RESP_4__SMC_RESP_MASK 0xffff
#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
#define SMC_RESP_5__SMC_RESP_MASK 0xffff
#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
#define SMC_RESP_6__SMC_RESP_MASK 0xffff
#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
#define SMC_RESP_7__SMC_RESP_MASK 0xffff
#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
#define SMC_RESP_8__SMC_RESP_MASK 0xffff
#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
#define SMC_RESP_9__SMC_RESP_MASK 0xffff
#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
#define SMC_RESP_10__SMC_RESP_MASK 0xffff
#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
#define SMC_RESP_11__SMC_RESP_MASK 0xffff
#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
#define SMC_PC_C__smc_pc_c__SHIFT 0x0
#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
#define GPIOPAD_A__GPIO_A__SHIFT 0x0
#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
#define CG_FPS_CNT__FPS_CNT_MASK 0xff
#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000
#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe
#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000
#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf
#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000
#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10
#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000
#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11
#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000
#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12
#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000
#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13
#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000
#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14
#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000
#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16
#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000
#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17
#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000
#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18
#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfe000000
#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19
#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
#define SMU_STATUS__SMU_DONE_MASK 0x1
#define SMU_STATUS__SMU_DONE__SHIFT 0x0
#define SMU_STATUS__SMU_PASS_MASK 0x2
#define SMU_STATUS__SMU_PASS__SHIFT 0x1
#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff
#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0
#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff
#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0
#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff
#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0
#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff
#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0
#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff
#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0
#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff
#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0
#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff
#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0
#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000
#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10
#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff
#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0
#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00
#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8
#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000
#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10
#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff
#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0
#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00
#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8
#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000
#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10
#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff
#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0
#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00
#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8
#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000
#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10
#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff
#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0
#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00
#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8
#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000
#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10
#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff
#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0
#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00
#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8
#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000
#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10
#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff
#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0
#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00
#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8
#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000
#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10
#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff
#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0
#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00
#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8
#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000
#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10
#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff
#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0
#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00
#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8
#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000
#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10
#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff
#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0
#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00
#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8
#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000
#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10
#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff
#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0
#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00
#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8
#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000
#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10
#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff
#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0
#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00
#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8
#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000
#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10
#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff
#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0
#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00
#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8
#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000
#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10
#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff
#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0
#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00
#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8
#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000
#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10
#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff
#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0
#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00
#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8
#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000
#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10
#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff
#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0
#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00
#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8
#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff
#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0
#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000
#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10
#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff
#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0
#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00
#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8
#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000
#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10
#define DPM_TABLE_68__UvdLevelCount_MASK 0xff
#define DPM_TABLE_68__UvdLevelCount__SHIFT 0x0
#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00
#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8
#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000
#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10
#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000
#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18
#define DPM_TABLE_69__MasterDeepSleepControl_MASK 0xff
#define DPM_TABLE_69__MasterDeepSleepControl__SHIFT 0x0
#define DPM_TABLE_69__SamuLevelCount_MASK 0xff00
#define DPM_TABLE_69__SamuLevelCount__SHIFT 0x8
#define DPM_TABLE_69__AcpLevelCount_MASK 0xff0000
#define DPM_TABLE_69__AcpLevelCount__SHIFT 0x10
#define DPM_TABLE_69__VceLevelCount_MASK 0xff000000
#define DPM_TABLE_69__VceLevelCount__SHIFT 0x18
#define DPM_TABLE_70__DefaultTdp_MASK 0xffff
#define DPM_TABLE_70__DefaultTdp__SHIFT 0x0
#define DPM_TABLE_70__TargetTdp_MASK 0xffff0000
#define DPM_TABLE_70__TargetTdp__SHIFT 0x10
#define DPM_TABLE_71__Reserved_1_MASK 0xffffffff
#define DPM_TABLE_71__Reserved_1__SHIFT 0x0
#define DPM_TABLE_72__Reserved_2_MASK 0xffffffff
#define DPM_TABLE_72__Reserved_2__SHIFT 0x0
#define DPM_TABLE_73__Reserved_3_MASK 0xffffffff
#define DPM_TABLE_73__Reserved_3__SHIFT 0x0
#define DPM_TABLE_74__Reserved_4_MASK 0xffffffff
#define DPM_TABLE_74__Reserved_4__SHIFT 0x0
#define DPM_TABLE_75__GraphicsLevel_0_Flags_MASK 0xffffffff
#define DPM_TABLE_75__GraphicsLevel_0_Flags__SHIFT 0x0
#define DPM_TABLE_76__GraphicsLevel_0_MinVddc_MASK 0xffffffff
#define DPM_TABLE_76__GraphicsLevel_0_MinVddc__SHIFT 0x0
#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel_MASK 0xffff
#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
#define DPM_TABLE_79__GraphicsLevel_0_padding1_MASK 0xff0000
#define DPM_TABLE_79__GraphicsLevel_0_padding1__SHIFT 0x10
#define DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000
#define DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18
#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
#define DPM_TABLE_86__GraphicsLevel_0_SclkDid_MASK 0xff000000
#define DPM_TABLE_86__GraphicsLevel_0_SclkDid__SHIFT 0x18
#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle_MASK 0xff
#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_87__GraphicsLevel_0_DownHyst_MASK 0xff0000
#define DPM_TABLE_87__GraphicsLevel_0_DownHyst__SHIFT 0x10
#define DPM_TABLE_87__GraphicsLevel_0_UpHyst_MASK 0xff000000
#define DPM_TABLE_87__GraphicsLevel_0_UpHyst__SHIFT 0x18
#define DPM_TABLE_88__GraphicsLevel_0_padding_2_MASK 0xff
#define DPM_TABLE_88__GraphicsLevel_0_padding_2__SHIFT 0x0
#define DPM_TABLE_88__GraphicsLevel_0_padding_1_MASK 0xff00
#define DPM_TABLE_88__GraphicsLevel_0_padding_1__SHIFT 0x8
#define DPM_TABLE_88__GraphicsLevel_0_padding_0_MASK 0xff0000
#define DPM_TABLE_88__GraphicsLevel_0_padding_0__SHIFT 0x10
#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId_MASK 0xff000000
#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x18
#define DPM_TABLE_89__GraphicsLevel_1_Flags_MASK 0xffffffff
#define DPM_TABLE_89__GraphicsLevel_1_Flags__SHIFT 0x0
#define DPM_TABLE_90__GraphicsLevel_1_MinVddc_MASK 0xffffffff
#define DPM_TABLE_90__GraphicsLevel_1_MinVddc__SHIFT 0x0
#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel_MASK 0xffff
#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
#define DPM_TABLE_93__GraphicsLevel_1_padding1_MASK 0xff0000
#define DPM_TABLE_93__GraphicsLevel_1_padding1__SHIFT 0x10
#define DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000
#define DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18
#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
#define DPM_TABLE_100__GraphicsLevel_1_SclkDid_MASK 0xff000000
#define DPM_TABLE_100__GraphicsLevel_1_SclkDid__SHIFT 0x18
#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle_MASK 0xff
#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_101__GraphicsLevel_1_DownHyst_MASK 0xff0000
#define DPM_TABLE_101__GraphicsLevel_1_DownHyst__SHIFT 0x10
#define DPM_TABLE_101__GraphicsLevel_1_UpHyst_MASK 0xff000000
#define DPM_TABLE_101__GraphicsLevel_1_UpHyst__SHIFT 0x18
#define DPM_TABLE_102__GraphicsLevel_1_padding_2_MASK 0xff
#define DPM_TABLE_102__GraphicsLevel_1_padding_2__SHIFT 0x0
#define DPM_TABLE_102__GraphicsLevel_1_padding_1_MASK 0xff00
#define DPM_TABLE_102__GraphicsLevel_1_padding_1__SHIFT 0x8
#define DPM_TABLE_102__GraphicsLevel_1_padding_0_MASK 0xff0000
#define DPM_TABLE_102__GraphicsLevel_1_padding_0__SHIFT 0x10
#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId_MASK 0xff000000
#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x18
#define DPM_TABLE_103__GraphicsLevel_2_Flags_MASK 0xffffffff
#define DPM_TABLE_103__GraphicsLevel_2_Flags__SHIFT 0x0
#define DPM_TABLE_104__GraphicsLevel_2_MinVddc_MASK 0xffffffff
#define DPM_TABLE_104__GraphicsLevel_2_MinVddc__SHIFT 0x0
#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel_MASK 0xffff
#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
#define DPM_TABLE_107__GraphicsLevel_2_padding1_MASK 0xff0000
#define DPM_TABLE_107__GraphicsLevel_2_padding1__SHIFT 0x10
#define DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000
#define DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18
#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
#define DPM_TABLE_114__GraphicsLevel_2_SclkDid_MASK 0xff000000
#define DPM_TABLE_114__GraphicsLevel_2_SclkDid__SHIFT 0x18
#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle_MASK 0xff
#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_115__GraphicsLevel_2_DownHyst_MASK 0xff0000
#define DPM_TABLE_115__GraphicsLevel_2_DownHyst__SHIFT 0x10
#define DPM_TABLE_115__GraphicsLevel_2_UpHyst_MASK 0xff000000
#define DPM_TABLE_115__GraphicsLevel_2_UpHyst__SHIFT 0x18
#define DPM_TABLE_116__GraphicsLevel_2_padding_2_MASK 0xff
#define DPM_TABLE_116__GraphicsLevel_2_padding_2__SHIFT 0x0
#define DPM_TABLE_116__GraphicsLevel_2_padding_1_MASK 0xff00
#define DPM_TABLE_116__GraphicsLevel_2_padding_1__SHIFT 0x8
#define DPM_TABLE_116__GraphicsLevel_2_padding_0_MASK 0xff0000
#define DPM_TABLE_116__GraphicsLevel_2_padding_0__SHIFT 0x10
#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId_MASK 0xff000000
#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x18
#define DPM_TABLE_117__GraphicsLevel_3_Flags_MASK 0xffffffff
#define DPM_TABLE_117__GraphicsLevel_3_Flags__SHIFT 0x0
#define DPM_TABLE_118__GraphicsLevel_3_MinVddc_MASK 0xffffffff
#define DPM_TABLE_118__GraphicsLevel_3_MinVddc__SHIFT 0x0
#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel_MASK 0xffff
#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
#define DPM_TABLE_121__GraphicsLevel_3_padding1_MASK 0xff0000
#define DPM_TABLE_121__GraphicsLevel_3_padding1__SHIFT 0x10
#define DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000
#define DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18
#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
#define DPM_TABLE_128__GraphicsLevel_3_SclkDid_MASK 0xff000000
#define DPM_TABLE_128__GraphicsLevel_3_SclkDid__SHIFT 0x18
#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle_MASK 0xff
#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_129__GraphicsLevel_3_DownHyst_MASK 0xff0000
#define DPM_TABLE_129__GraphicsLevel_3_DownHyst__SHIFT 0x10
#define DPM_TABLE_129__GraphicsLevel_3_UpHyst_MASK 0xff000000
#define DPM_TABLE_129__GraphicsLevel_3_UpHyst__SHIFT 0x18
#define DPM_TABLE_130__GraphicsLevel_3_padding_2_MASK 0xff
#define DPM_TABLE_130__GraphicsLevel_3_padding_2__SHIFT 0x0
#define DPM_TABLE_130__GraphicsLevel_3_padding_1_MASK 0xff00
#define DPM_TABLE_130__GraphicsLevel_3_padding_1__SHIFT 0x8
#define DPM_TABLE_130__GraphicsLevel_3_padding_0_MASK 0xff0000
#define DPM_TABLE_130__GraphicsLevel_3_padding_0__SHIFT 0x10
#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff000000
#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x18
#define DPM_TABLE_131__GraphicsLevel_4_Flags_MASK 0xffffffff
#define DPM_TABLE_131__GraphicsLevel_4_Flags__SHIFT 0x0
#define DPM_TABLE_132__GraphicsLevel_4_MinVddc_MASK 0xffffffff
#define DPM_TABLE_132__GraphicsLevel_4_MinVddc__SHIFT 0x0
#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel_MASK 0xffff
#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
#define DPM_TABLE_135__GraphicsLevel_4_padding1_MASK 0xff0000
#define DPM_TABLE_135__GraphicsLevel_4_padding1__SHIFT 0x10
#define DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000
#define DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18
#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
#define DPM_TABLE_142__GraphicsLevel_4_SclkDid_MASK 0xff000000
#define DPM_TABLE_142__GraphicsLevel_4_SclkDid__SHIFT 0x18
#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle_MASK 0xff
#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_143__GraphicsLevel_4_DownHyst_MASK 0xff0000
#define DPM_TABLE_143__GraphicsLevel_4_DownHyst__SHIFT 0x10
#define DPM_TABLE_143__GraphicsLevel_4_UpHyst_MASK 0xff000000
#define DPM_TABLE_143__GraphicsLevel_4_UpHyst__SHIFT 0x18
#define DPM_TABLE_144__GraphicsLevel_4_padding_2_MASK 0xff
#define DPM_TABLE_144__GraphicsLevel_4_padding_2__SHIFT 0x0
#define DPM_TABLE_144__GraphicsLevel_4_padding_1_MASK 0xff00
#define DPM_TABLE_144__GraphicsLevel_4_padding_1__SHIFT 0x8
#define DPM_TABLE_144__GraphicsLevel_4_padding_0_MASK 0xff0000
#define DPM_TABLE_144__GraphicsLevel_4_padding_0__SHIFT 0x10
#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId_MASK 0xff000000
#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x18
#define DPM_TABLE_145__GraphicsLevel_5_Flags_MASK 0xffffffff
#define DPM_TABLE_145__GraphicsLevel_5_Flags__SHIFT 0x0
#define DPM_TABLE_146__GraphicsLevel_5_MinVddc_MASK 0xffffffff
#define DPM_TABLE_146__GraphicsLevel_5_MinVddc__SHIFT 0x0
#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel_MASK 0xffff
#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
#define DPM_TABLE_149__GraphicsLevel_5_padding1_MASK 0xff0000
#define DPM_TABLE_149__GraphicsLevel_5_padding1__SHIFT 0x10
#define DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000
#define DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18
#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
#define DPM_TABLE_156__GraphicsLevel_5_SclkDid_MASK 0xff000000
#define DPM_TABLE_156__GraphicsLevel_5_SclkDid__SHIFT 0x18
#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle_MASK 0xff
#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_157__GraphicsLevel_5_DownHyst_MASK 0xff0000
#define DPM_TABLE_157__GraphicsLevel_5_DownHyst__SHIFT 0x10
#define DPM_TABLE_157__GraphicsLevel_5_UpHyst_MASK 0xff000000
#define DPM_TABLE_157__GraphicsLevel_5_UpHyst__SHIFT 0x18
#define DPM_TABLE_158__GraphicsLevel_5_padding_2_MASK 0xff
#define DPM_TABLE_158__GraphicsLevel_5_padding_2__SHIFT 0x0
#define DPM_TABLE_158__GraphicsLevel_5_padding_1_MASK 0xff00
#define DPM_TABLE_158__GraphicsLevel_5_padding_1__SHIFT 0x8
#define DPM_TABLE_158__GraphicsLevel_5_padding_0_MASK 0xff0000
#define DPM_TABLE_158__GraphicsLevel_5_padding_0__SHIFT 0x10
#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId_MASK 0xff000000
#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x18
#define DPM_TABLE_159__GraphicsLevel_6_Flags_MASK 0xffffffff
#define DPM_TABLE_159__GraphicsLevel_6_Flags__SHIFT 0x0
#define DPM_TABLE_160__GraphicsLevel_6_MinVddc_MASK 0xffffffff
#define DPM_TABLE_160__GraphicsLevel_6_MinVddc__SHIFT 0x0
#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff
#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
#define DPM_TABLE_163__GraphicsLevel_6_padding1_MASK 0xff0000
#define DPM_TABLE_163__GraphicsLevel_6_padding1__SHIFT 0x10
#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000
#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18
#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000
#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18
#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff
#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000
#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10
#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000
#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18
#define DPM_TABLE_172__GraphicsLevel_6_padding_2_MASK 0xff
#define DPM_TABLE_172__GraphicsLevel_6_padding_2__SHIFT 0x0
#define DPM_TABLE_172__GraphicsLevel_6_padding_1_MASK 0xff00
#define DPM_TABLE_172__GraphicsLevel_6_padding_1__SHIFT 0x8
#define DPM_TABLE_172__GraphicsLevel_6_padding_0_MASK 0xff0000
#define DPM_TABLE_172__GraphicsLevel_6_padding_0__SHIFT 0x10
#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId_MASK 0xff000000
#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x18
#define DPM_TABLE_173__GraphicsLevel_7_Flags_MASK 0xffffffff
#define DPM_TABLE_173__GraphicsLevel_7_Flags__SHIFT 0x0
#define DPM_TABLE_174__GraphicsLevel_7_MinVddc_MASK 0xffffffff
#define DPM_TABLE_174__GraphicsLevel_7_MinVddc__SHIFT 0x0
#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel_MASK 0xffff
#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
#define DPM_TABLE_177__GraphicsLevel_7_padding1_MASK 0xff0000
#define DPM_TABLE_177__GraphicsLevel_7_padding1__SHIFT 0x10
#define DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000
#define DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18
#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
#define DPM_TABLE_184__GraphicsLevel_7_SclkDid_MASK 0xff000000
#define DPM_TABLE_184__GraphicsLevel_7_SclkDid__SHIFT 0x18
#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle_MASK 0xff
#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_185__GraphicsLevel_7_DownHyst_MASK 0xff0000
#define DPM_TABLE_185__GraphicsLevel_7_DownHyst__SHIFT 0x10
#define DPM_TABLE_185__GraphicsLevel_7_UpHyst_MASK 0xff000000
#define DPM_TABLE_185__GraphicsLevel_7_UpHyst__SHIFT 0x18
#define DPM_TABLE_186__GraphicsLevel_7_padding_2_MASK 0xff
#define DPM_TABLE_186__GraphicsLevel_7_padding_2__SHIFT 0x0
#define DPM_TABLE_186__GraphicsLevel_7_padding_1_MASK 0xff00
#define DPM_TABLE_186__GraphicsLevel_7_padding_1__SHIFT 0x8
#define DPM_TABLE_186__GraphicsLevel_7_padding_0_MASK 0xff0000
#define DPM_TABLE_186__GraphicsLevel_7_padding_0__SHIFT 0x10
#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId_MASK 0xff000000
#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x18
#define DPM_TABLE_187__MemoryACPILevel_MinVddc_MASK 0xffffffff
#define DPM_TABLE_187__MemoryACPILevel_MinVddc__SHIFT 0x0
#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_189__MemoryACPILevel_MinVddci_MASK 0xffffffff
#define DPM_TABLE_189__MemoryACPILevel_MinVddci__SHIFT 0x0
#define DPM_TABLE_190__MemoryACPILevel_MinMvdd_MASK 0xffffffff
#define DPM_TABLE_190__MemoryACPILevel_MinMvdd__SHIFT 0x0
#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency__SHIFT 0x0
#define DPM_TABLE_192__MemoryACPILevel_StutterEnable_MASK 0xff
#define DPM_TABLE_192__MemoryACPILevel_StutterEnable__SHIFT 0x0
#define DPM_TABLE_192__MemoryACPILevel_RttEnable_MASK 0xff00
#define DPM_TABLE_192__MemoryACPILevel_RttEnable__SHIFT 0x8
#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000
#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10
#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable_MASK 0xff000000
#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable__SHIFT 0x18
#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity_MASK 0xff
#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio_MASK 0xff0000
#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio__SHIFT 0x10
#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable_MASK 0xff000000
#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable__SHIFT 0x18
#define DPM_TABLE_194__MemoryACPILevel_padding_MASK 0xff
#define DPM_TABLE_194__MemoryACPILevel_padding__SHIFT 0x0
#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_194__MemoryACPILevel_DownHyst_MASK 0xff0000
#define DPM_TABLE_194__MemoryACPILevel_DownHyst__SHIFT 0x10
#define DPM_TABLE_194__MemoryACPILevel_UpHyst_MASK 0xff000000
#define DPM_TABLE_194__MemoryACPILevel_UpHyst__SHIFT 0x18
#define DPM_TABLE_195__MemoryACPILevel_padding1_MASK 0xff
#define DPM_TABLE_195__MemoryACPILevel_padding1__SHIFT 0x0
#define DPM_TABLE_195__MemoryACPILevel_DisplayWatermark_MASK 0xff00
#define DPM_TABLE_195__MemoryACPILevel_DisplayWatermark__SHIFT 0x8
#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel__SHIFT 0x10
#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff
#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0
#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff
#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0
#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff
#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0
#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff
#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0
#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff
#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0
#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff
#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0
#define DPM_TABLE_202__MemoryACPILevel_DllCntl_MASK 0xffffffff
#define DPM_TABLE_202__MemoryACPILevel_DllCntl__SHIFT 0x0
#define DPM_TABLE_203__MemoryACPILevel_MpllSs1_MASK 0xffffffff
#define DPM_TABLE_203__MemoryACPILevel_MpllSs1__SHIFT 0x0
#define DPM_TABLE_204__MemoryACPILevel_MpllSs2_MASK 0xffffffff
#define DPM_TABLE_204__MemoryACPILevel_MpllSs2__SHIFT 0x0
#define DPM_TABLE_205__MemoryLevel_0_MinVddc_MASK 0xffffffff
#define DPM_TABLE_205__MemoryLevel_0_MinVddc__SHIFT 0x0
#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_207__MemoryLevel_0_MinVddci_MASK 0xffffffff
#define DPM_TABLE_207__MemoryLevel_0_MinVddci__SHIFT 0x0
#define DPM_TABLE_208__MemoryLevel_0_MinMvdd_MASK 0xffffffff
#define DPM_TABLE_208__MemoryLevel_0_MinMvdd__SHIFT 0x0
#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency__SHIFT 0x0
#define DPM_TABLE_210__MemoryLevel_0_StutterEnable_MASK 0xff
#define DPM_TABLE_210__MemoryLevel_0_StutterEnable__SHIFT 0x0
#define DPM_TABLE_210__MemoryLevel_0_RttEnable_MASK 0xff00
#define DPM_TABLE_210__MemoryLevel_0_RttEnable__SHIFT 0x8
#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000
#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10
#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable_MASK 0xff000000
#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable__SHIFT 0x18
#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity_MASK 0xff
#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio_MASK 0xff0000
#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio__SHIFT 0x10
#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable_MASK 0xff000000
#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable__SHIFT 0x18
#define DPM_TABLE_212__MemoryLevel_0_padding_MASK 0xff
#define DPM_TABLE_212__MemoryLevel_0_padding__SHIFT 0x0
#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_212__MemoryLevel_0_DownHyst_MASK 0xff0000
#define DPM_TABLE_212__MemoryLevel_0_DownHyst__SHIFT 0x10
#define DPM_TABLE_212__MemoryLevel_0_UpHyst_MASK 0xff000000
#define DPM_TABLE_212__MemoryLevel_0_UpHyst__SHIFT 0x18
#define DPM_TABLE_213__MemoryLevel_0_padding1_MASK 0xff
#define DPM_TABLE_213__MemoryLevel_0_padding1__SHIFT 0x0
#define DPM_TABLE_213__MemoryLevel_0_DisplayWatermark_MASK 0xff00
#define DPM_TABLE_213__MemoryLevel_0_DisplayWatermark__SHIFT 0x8
#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel__SHIFT 0x10
#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff
#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0
#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff
#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0
#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff
#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0
#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff
#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0
#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff
#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0
#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff
#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0
#define DPM_TABLE_220__MemoryLevel_0_DllCntl_MASK 0xffffffff
#define DPM_TABLE_220__MemoryLevel_0_DllCntl__SHIFT 0x0
#define DPM_TABLE_221__MemoryLevel_0_MpllSs1_MASK 0xffffffff
#define DPM_TABLE_221__MemoryLevel_0_MpllSs1__SHIFT 0x0
#define DPM_TABLE_222__MemoryLevel_0_MpllSs2_MASK 0xffffffff
#define DPM_TABLE_222__MemoryLevel_0_MpllSs2__SHIFT 0x0
#define DPM_TABLE_223__MemoryLevel_1_MinVddc_MASK 0xffffffff
#define DPM_TABLE_223__MemoryLevel_1_MinVddc__SHIFT 0x0
#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_225__MemoryLevel_1_MinVddci_MASK 0xffffffff
#define DPM_TABLE_225__MemoryLevel_1_MinVddci__SHIFT 0x0
#define DPM_TABLE_226__MemoryLevel_1_MinMvdd_MASK 0xffffffff
#define DPM_TABLE_226__MemoryLevel_1_MinMvdd__SHIFT 0x0
#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency__SHIFT 0x0
#define DPM_TABLE_228__MemoryLevel_1_StutterEnable_MASK 0xff
#define DPM_TABLE_228__MemoryLevel_1_StutterEnable__SHIFT 0x0
#define DPM_TABLE_228__MemoryLevel_1_RttEnable_MASK 0xff00
#define DPM_TABLE_228__MemoryLevel_1_RttEnable__SHIFT 0x8
#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000
#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10
#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable_MASK 0xff000000
#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable__SHIFT 0x18
#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity_MASK 0xff
#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio_MASK 0xff0000
#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio__SHIFT 0x10
#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable_MASK 0xff000000
#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable__SHIFT 0x18
#define DPM_TABLE_230__MemoryLevel_1_padding_MASK 0xff
#define DPM_TABLE_230__MemoryLevel_1_padding__SHIFT 0x0
#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_230__MemoryLevel_1_DownHyst_MASK 0xff0000
#define DPM_TABLE_230__MemoryLevel_1_DownHyst__SHIFT 0x10
#define DPM_TABLE_230__MemoryLevel_1_UpHyst_MASK 0xff000000
#define DPM_TABLE_230__MemoryLevel_1_UpHyst__SHIFT 0x18
#define DPM_TABLE_231__MemoryLevel_1_padding1_MASK 0xff
#define DPM_TABLE_231__MemoryLevel_1_padding1__SHIFT 0x0
#define DPM_TABLE_231__MemoryLevel_1_DisplayWatermark_MASK 0xff00
#define DPM_TABLE_231__MemoryLevel_1_DisplayWatermark__SHIFT 0x8
#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel__SHIFT 0x10
#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff
#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0
#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff
#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0
#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff
#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0
#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff
#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0
#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff
#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0
#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff
#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0
#define DPM_TABLE_238__MemoryLevel_1_DllCntl_MASK 0xffffffff
#define DPM_TABLE_238__MemoryLevel_1_DllCntl__SHIFT 0x0
#define DPM_TABLE_239__MemoryLevel_1_MpllSs1_MASK 0xffffffff
#define DPM_TABLE_239__MemoryLevel_1_MpllSs1__SHIFT 0x0
#define DPM_TABLE_240__MemoryLevel_1_MpllSs2_MASK 0xffffffff
#define DPM_TABLE_240__MemoryLevel_1_MpllSs2__SHIFT 0x0
#define DPM_TABLE_241__MemoryLevel_2_MinVddc_MASK 0xffffffff
#define DPM_TABLE_241__MemoryLevel_2_MinVddc__SHIFT 0x0
#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_243__MemoryLevel_2_MinVddci_MASK 0xffffffff
#define DPM_TABLE_243__MemoryLevel_2_MinVddci__SHIFT 0x0
#define DPM_TABLE_244__MemoryLevel_2_MinMvdd_MASK 0xffffffff
#define DPM_TABLE_244__MemoryLevel_2_MinMvdd__SHIFT 0x0
#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency__SHIFT 0x0
#define DPM_TABLE_246__MemoryLevel_2_StutterEnable_MASK 0xff
#define DPM_TABLE_246__MemoryLevel_2_StutterEnable__SHIFT 0x0
#define DPM_TABLE_246__MemoryLevel_2_RttEnable_MASK 0xff00
#define DPM_TABLE_246__MemoryLevel_2_RttEnable__SHIFT 0x8
#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000
#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10
#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable_MASK 0xff000000
#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable__SHIFT 0x18
#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity_MASK 0xff
#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio_MASK 0xff0000
#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio__SHIFT 0x10
#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable_MASK 0xff000000
#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable__SHIFT 0x18
#define DPM_TABLE_248__MemoryLevel_2_padding_MASK 0xff
#define DPM_TABLE_248__MemoryLevel_2_padding__SHIFT 0x0
#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_248__MemoryLevel_2_DownHyst_MASK 0xff0000
#define DPM_TABLE_248__MemoryLevel_2_DownHyst__SHIFT 0x10
#define DPM_TABLE_248__MemoryLevel_2_UpHyst_MASK 0xff000000
#define DPM_TABLE_248__MemoryLevel_2_UpHyst__SHIFT 0x18
#define DPM_TABLE_249__MemoryLevel_2_padding1_MASK 0xff
#define DPM_TABLE_249__MemoryLevel_2_padding1__SHIFT 0x0
#define DPM_TABLE_249__MemoryLevel_2_DisplayWatermark_MASK 0xff00
#define DPM_TABLE_249__MemoryLevel_2_DisplayWatermark__SHIFT 0x8
#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel__SHIFT 0x10
#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff
#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0
#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff
#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0
#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff
#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0
#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff
#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0
#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff
#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0
#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff
#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0
#define DPM_TABLE_256__MemoryLevel_2_DllCntl_MASK 0xffffffff
#define DPM_TABLE_256__MemoryLevel_2_DllCntl__SHIFT 0x0
#define DPM_TABLE_257__MemoryLevel_2_MpllSs1_MASK 0xffffffff
#define DPM_TABLE_257__MemoryLevel_2_MpllSs1__SHIFT 0x0
#define DPM_TABLE_258__MemoryLevel_2_MpllSs2_MASK 0xffffffff
#define DPM_TABLE_258__MemoryLevel_2_MpllSs2__SHIFT 0x0
#define DPM_TABLE_259__MemoryLevel_3_MinVddc_MASK 0xffffffff
#define DPM_TABLE_259__MemoryLevel_3_MinVddc__SHIFT 0x0
#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_261__MemoryLevel_3_MinVddci_MASK 0xffffffff
#define DPM_TABLE_261__MemoryLevel_3_MinVddci__SHIFT 0x0
#define DPM_TABLE_262__MemoryLevel_3_MinMvdd_MASK 0xffffffff
#define DPM_TABLE_262__MemoryLevel_3_MinMvdd__SHIFT 0x0
#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency__SHIFT 0x0
#define DPM_TABLE_264__MemoryLevel_3_StutterEnable_MASK 0xff
#define DPM_TABLE_264__MemoryLevel_3_StutterEnable__SHIFT 0x0
#define DPM_TABLE_264__MemoryLevel_3_RttEnable_MASK 0xff00
#define DPM_TABLE_264__MemoryLevel_3_RttEnable__SHIFT 0x8
#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000
#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10
#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable_MASK 0xff000000
#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable__SHIFT 0x18
#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity_MASK 0xff
#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio_MASK 0xff0000
#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio__SHIFT 0x10
#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable_MASK 0xff000000
#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable__SHIFT 0x18
#define DPM_TABLE_266__MemoryLevel_3_padding_MASK 0xff
#define DPM_TABLE_266__MemoryLevel_3_padding__SHIFT 0x0
#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_266__MemoryLevel_3_DownHyst_MASK 0xff0000
#define DPM_TABLE_266__MemoryLevel_3_DownHyst__SHIFT 0x10
#define DPM_TABLE_266__MemoryLevel_3_UpHyst_MASK 0xff000000
#define DPM_TABLE_266__MemoryLevel_3_UpHyst__SHIFT 0x18
#define DPM_TABLE_267__MemoryLevel_3_padding1_MASK 0xff
#define DPM_TABLE_267__MemoryLevel_3_padding1__SHIFT 0x0
#define DPM_TABLE_267__MemoryLevel_3_DisplayWatermark_MASK 0xff00
#define DPM_TABLE_267__MemoryLevel_3_DisplayWatermark__SHIFT 0x8
#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel__SHIFT 0x10
#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff
#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0
#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff
#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0
#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff
#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0
#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff
#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0
#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff
#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0
#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff
#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0
#define DPM_TABLE_274__MemoryLevel_3_DllCntl_MASK 0xffffffff
#define DPM_TABLE_274__MemoryLevel_3_DllCntl__SHIFT 0x0
#define DPM_TABLE_275__MemoryLevel_3_MpllSs1_MASK 0xffffffff
#define DPM_TABLE_275__MemoryLevel_3_MpllSs1__SHIFT 0x0
#define DPM_TABLE_276__MemoryLevel_3_MpllSs2_MASK 0xffffffff
#define DPM_TABLE_276__MemoryLevel_3_MpllSs2__SHIFT 0x0
#define DPM_TABLE_277__MemoryLevel_4_MinVddc_MASK 0xffffffff
#define DPM_TABLE_277__MemoryLevel_4_MinVddc__SHIFT 0x0
#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_279__MemoryLevel_4_MinVddci_MASK 0xffffffff
#define DPM_TABLE_279__MemoryLevel_4_MinVddci__SHIFT 0x0
#define DPM_TABLE_280__MemoryLevel_4_MinMvdd_MASK 0xffffffff
#define DPM_TABLE_280__MemoryLevel_4_MinMvdd__SHIFT 0x0
#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency_MASK 0xffffffff
#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency__SHIFT 0x0
#define DPM_TABLE_282__MemoryLevel_4_StutterEnable_MASK 0xff
#define DPM_TABLE_282__MemoryLevel_4_StutterEnable__SHIFT 0x0
#define DPM_TABLE_282__MemoryLevel_4_RttEnable_MASK 0xff00
#define DPM_TABLE_282__MemoryLevel_4_RttEnable__SHIFT 0x8
#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable_MASK 0xff0000
#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable__SHIFT 0x10
#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable_MASK 0xff000000
#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable__SHIFT 0x18
#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity_MASK 0xff
#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity__SHIFT 0x0
#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle_MASK 0xff00
#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle__SHIFT 0x8
#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio_MASK 0xff0000
#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio__SHIFT 0x10
#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable_MASK 0xff000000
#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable__SHIFT 0x18
#define DPM_TABLE_284__MemoryLevel_4_padding_MASK 0xff
#define DPM_TABLE_284__MemoryLevel_4_padding__SHIFT 0x0
#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_284__MemoryLevel_4_DownHyst_MASK 0xff0000
#define DPM_TABLE_284__MemoryLevel_4_DownHyst__SHIFT 0x10
#define DPM_TABLE_284__MemoryLevel_4_UpHyst_MASK 0xff000000
#define DPM_TABLE_284__MemoryLevel_4_UpHyst__SHIFT 0x18
#define DPM_TABLE_285__MemoryLevel_4_padding1_MASK 0xff
#define DPM_TABLE_285__MemoryLevel_4_padding1__SHIFT 0x0
#define DPM_TABLE_285__MemoryLevel_4_DisplayWatermark_MASK 0xff00
#define DPM_TABLE_285__MemoryLevel_4_DisplayWatermark__SHIFT 0x8
#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel_MASK 0xffff0000
#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel__SHIFT 0x10
#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl_MASK 0xffffffff
#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl__SHIFT 0x0
#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1_MASK 0xffffffff
#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1__SHIFT 0x0
#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2_MASK 0xffffffff
#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2__SHIFT 0x0
#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl_MASK 0xffffffff
#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl__SHIFT 0x0
#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl_MASK 0xffffffff
#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl__SHIFT 0x0
#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl_MASK 0xffffffff
#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl__SHIFT 0x0
#define DPM_TABLE_292__MemoryLevel_4_DllCntl_MASK 0xffffffff
#define DPM_TABLE_292__MemoryLevel_4_DllCntl__SHIFT 0x0
#define DPM_TABLE_293__MemoryLevel_4_MpllSs1_MASK 0xffffffff
#define DPM_TABLE_293__MemoryLevel_4_MpllSs1__SHIFT 0x0
#define DPM_TABLE_294__MemoryLevel_4_MpllSs2_MASK 0xffffffff
#define DPM_TABLE_294__MemoryLevel_4_MpllSs2__SHIFT 0x0
#define DPM_TABLE_295__MemoryLevel_5_MinVddc_MASK 0xffffffff
#define DPM_TABLE_295__MemoryLevel_5_MinVddc__SHIFT 0x0
#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_297__MemoryLevel_5_MinVddci_MASK 0xffffffff
#define DPM_TABLE_297__MemoryLevel_5_MinVddci__SHIFT 0x0
#define DPM_TABLE_298__MemoryLevel_5_MinMvdd_MASK 0xffffffff
#define DPM_TABLE_298__MemoryLevel_5_MinMvdd__SHIFT 0x0
#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency_MASK 0xffffffff
#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency__SHIFT 0x0
#define DPM_TABLE_300__MemoryLevel_5_StutterEnable_MASK 0xff
#define DPM_TABLE_300__MemoryLevel_5_StutterEnable__SHIFT 0x0
#define DPM_TABLE_300__MemoryLevel_5_RttEnable_MASK 0xff00
#define DPM_TABLE_300__MemoryLevel_5_RttEnable__SHIFT 0x8
#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable_MASK 0xff0000
#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable__SHIFT 0x10
#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable_MASK 0xff000000
#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable__SHIFT 0x18
#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity_MASK 0xff
#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity__SHIFT 0x0
#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle_MASK 0xff00
#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle__SHIFT 0x8
#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio_MASK 0xff0000
#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio__SHIFT 0x10
#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable_MASK 0xff000000
#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable__SHIFT 0x18
#define DPM_TABLE_302__MemoryLevel_5_padding_MASK 0xff
#define DPM_TABLE_302__MemoryLevel_5_padding__SHIFT 0x0
#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst_MASK 0xff00
#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst__SHIFT 0x8
#define DPM_TABLE_302__MemoryLevel_5_DownHyst_MASK 0xff0000
#define DPM_TABLE_302__MemoryLevel_5_DownHyst__SHIFT 0x10
#define DPM_TABLE_302__MemoryLevel_5_UpHyst_MASK 0xff000000
#define DPM_TABLE_302__MemoryLevel_5_UpHyst__SHIFT 0x18
#define DPM_TABLE_303__MemoryLevel_5_padding1_MASK 0xff
#define DPM_TABLE_303__MemoryLevel_5_padding1__SHIFT 0x0
#define DPM_TABLE_303__MemoryLevel_5_DisplayWatermark_MASK 0xff00
#define DPM_TABLE_303__MemoryLevel_5_DisplayWatermark__SHIFT 0x8
#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel_MASK 0xffff0000
#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel__SHIFT 0x10
#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl_MASK 0xffffffff
#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl__SHIFT 0x0
#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1_MASK 0xffffffff
#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1__SHIFT 0x0
#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2_MASK 0xffffffff
#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2__SHIFT 0x0
#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl_MASK 0xffffffff
#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl__SHIFT 0x0
#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl_MASK 0xffffffff
#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl__SHIFT 0x0
#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl_MASK 0xffffffff
#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl__SHIFT 0x0
#define DPM_TABLE_310__MemoryLevel_5_DllCntl_MASK 0xffffffff
#define DPM_TABLE_310__MemoryLevel_5_DllCntl__SHIFT 0x0
#define DPM_TABLE_311__MemoryLevel_5_MpllSs1_MASK 0xffffffff
#define DPM_TABLE_311__MemoryLevel_5_MpllSs1__SHIFT 0x0
#define DPM_TABLE_312__MemoryLevel_5_MpllSs2_MASK 0xffffffff
#define DPM_TABLE_312__MemoryLevel_5_MpllSs2__SHIFT 0x0
#define DPM_TABLE_313__LinkLevel_0_Padding_MASK 0xff
#define DPM_TABLE_313__LinkLevel_0_Padding__SHIFT 0x0
#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount_MASK 0xff0000
#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount__SHIFT 0x10
#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
#define DPM_TABLE_314__LinkLevel_0_DownThreshold_MASK 0xffffffff
#define DPM_TABLE_314__LinkLevel_0_DownThreshold__SHIFT 0x0
#define DPM_TABLE_315__LinkLevel_0_UpThreshold_MASK 0xffffffff
#define DPM_TABLE_315__LinkLevel_0_UpThreshold__SHIFT 0x0
#define DPM_TABLE_316__LinkLevel_0_Reserved_MASK 0xffffffff
#define DPM_TABLE_316__LinkLevel_0_Reserved__SHIFT 0x0
#define DPM_TABLE_317__LinkLevel_1_Padding_MASK 0xff
#define DPM_TABLE_317__LinkLevel_1_Padding__SHIFT 0x0
#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount_MASK 0xff0000
#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount__SHIFT 0x10
#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
#define DPM_TABLE_318__LinkLevel_1_DownThreshold_MASK 0xffffffff
#define DPM_TABLE_318__LinkLevel_1_DownThreshold__SHIFT 0x0
#define DPM_TABLE_319__LinkLevel_1_UpThreshold_MASK 0xffffffff
#define DPM_TABLE_319__LinkLevel_1_UpThreshold__SHIFT 0x0
#define DPM_TABLE_320__LinkLevel_1_Reserved_MASK 0xffffffff
#define DPM_TABLE_320__LinkLevel_1_Reserved__SHIFT 0x0
#define DPM_TABLE_321__LinkLevel_2_Padding_MASK 0xff
#define DPM_TABLE_321__LinkLevel_2_Padding__SHIFT 0x0
#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount_MASK 0xff0000
#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount__SHIFT 0x10
#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
#define DPM_TABLE_322__LinkLevel_2_DownThreshold_MASK 0xffffffff
#define DPM_TABLE_322__LinkLevel_2_DownThreshold__SHIFT 0x0
#define DPM_TABLE_323__LinkLevel_2_UpThreshold_MASK 0xffffffff
#define DPM_TABLE_323__LinkLevel_2_UpThreshold__SHIFT 0x0
#define DPM_TABLE_324__LinkLevel_2_Reserved_MASK 0xffffffff
#define DPM_TABLE_324__LinkLevel_2_Reserved__SHIFT 0x0
#define DPM_TABLE_325__LinkLevel_3_Padding_MASK 0xff
#define DPM_TABLE_325__LinkLevel_3_Padding__SHIFT 0x0
#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000
#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount__SHIFT 0x10
#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
#define DPM_TABLE_326__LinkLevel_3_DownThreshold_MASK 0xffffffff
#define DPM_TABLE_326__LinkLevel_3_DownThreshold__SHIFT 0x0
#define DPM_TABLE_327__LinkLevel_3_UpThreshold_MASK 0xffffffff
#define DPM_TABLE_327__LinkLevel_3_UpThreshold__SHIFT 0x0
#define DPM_TABLE_328__LinkLevel_3_Reserved_MASK 0xffffffff
#define DPM_TABLE_328__LinkLevel_3_Reserved__SHIFT 0x0
#define DPM_TABLE_329__LinkLevel_4_Padding_MASK 0xff
#define DPM_TABLE_329__LinkLevel_4_Padding__SHIFT 0x0
#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount_MASK 0xff0000
#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount__SHIFT 0x10
#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
#define DPM_TABLE_330__LinkLevel_4_DownThreshold_MASK 0xffffffff
#define DPM_TABLE_330__LinkLevel_4_DownThreshold__SHIFT 0x0
#define DPM_TABLE_331__LinkLevel_4_UpThreshold_MASK 0xffffffff
#define DPM_TABLE_331__LinkLevel_4_UpThreshold__SHIFT 0x0
#define DPM_TABLE_332__LinkLevel_4_Reserved_MASK 0xffffffff
#define DPM_TABLE_332__LinkLevel_4_Reserved__SHIFT 0x0
#define DPM_TABLE_333__LinkLevel_5_Padding_MASK 0xff
#define DPM_TABLE_333__LinkLevel_5_Padding__SHIFT 0x0
#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount_MASK 0xff0000
#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10
#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
#define DPM_TABLE_334__LinkLevel_5_DownThreshold_MASK 0xffffffff
#define DPM_TABLE_334__LinkLevel_5_DownThreshold__SHIFT 0x0
#define DPM_TABLE_335__LinkLevel_5_UpThreshold_MASK 0xffffffff
#define DPM_TABLE_335__LinkLevel_5_UpThreshold__SHIFT 0x0
#define DPM_TABLE_336__LinkLevel_5_Reserved_MASK 0xffffffff
#define DPM_TABLE_336__LinkLevel_5_Reserved__SHIFT 0x0
#define DPM_TABLE_337__LinkLevel_6_Padding_MASK 0xff
#define DPM_TABLE_337__LinkLevel_6_Padding__SHIFT 0x0
#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount_MASK 0xff0000
#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount__SHIFT 0x10
#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
#define DPM_TABLE_338__LinkLevel_6_DownThreshold_MASK 0xffffffff
#define DPM_TABLE_338__LinkLevel_6_DownThreshold__SHIFT 0x0
#define DPM_TABLE_339__LinkLevel_6_UpThreshold_MASK 0xffffffff
#define DPM_TABLE_339__LinkLevel_6_UpThreshold__SHIFT 0x0
#define DPM_TABLE_340__LinkLevel_6_Reserved_MASK 0xffffffff
#define DPM_TABLE_340__LinkLevel_6_Reserved__SHIFT 0x0
#define DPM_TABLE_341__LinkLevel_7_Padding_MASK 0xff
#define DPM_TABLE_341__LinkLevel_7_Padding__SHIFT 0x0
#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity_MASK 0xff00
#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity__SHIFT 0x8
#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount_MASK 0xff0000
#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount__SHIFT 0x10
#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
#define DPM_TABLE_342__LinkLevel_7_DownThreshold_MASK 0xffffffff
#define DPM_TABLE_342__LinkLevel_7_DownThreshold__SHIFT 0x0
#define DPM_TABLE_343__LinkLevel_7_UpThreshold_MASK 0xffffffff
#define DPM_TABLE_343__LinkLevel_7_UpThreshold__SHIFT 0x0
#define DPM_TABLE_344__LinkLevel_7_Reserved_MASK 0xffffffff
#define DPM_TABLE_344__LinkLevel_7_Reserved__SHIFT 0x0
#define DPM_TABLE_345__ACPILevel_Flags_MASK 0xffffffff
#define DPM_TABLE_345__ACPILevel_Flags__SHIFT 0x0
#define DPM_TABLE_346__ACPILevel_MinVddc_MASK 0xffffffff
#define DPM_TABLE_346__ACPILevel_MinVddc__SHIFT 0x0
#define DPM_TABLE_347__ACPILevel_MinVddcPhases_MASK 0xffffffff
#define DPM_TABLE_347__ACPILevel_MinVddcPhases__SHIFT 0x0
#define DPM_TABLE_348__ACPILevel_SclkFrequency_MASK 0xffffffff
#define DPM_TABLE_348__ACPILevel_SclkFrequency__SHIFT 0x0
#define DPM_TABLE_349__ACPILevel_padding_MASK 0xff
#define DPM_TABLE_349__ACPILevel_padding__SHIFT 0x0
#define DPM_TABLE_349__ACPILevel_DeepSleepDivId_MASK 0xff00
#define DPM_TABLE_349__ACPILevel_DeepSleepDivId__SHIFT 0x8
#define DPM_TABLE_349__ACPILevel_DisplayWatermark_MASK 0xff0000
#define DPM_TABLE_349__ACPILevel_DisplayWatermark__SHIFT 0x10
#define DPM_TABLE_349__ACPILevel_SclkDid_MASK 0xff000000
#define DPM_TABLE_349__ACPILevel_SclkDid__SHIFT 0x18
#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
#define DPM_TABLE_356__ACPILevel_CcPwrDynRm_MASK 0xffffffff
#define DPM_TABLE_356__ACPILevel_CcPwrDynRm__SHIFT 0x0
#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1__SHIFT 0x0
#define DPM_TABLE_358__UvdLevel_0_VclkFrequency_MASK 0xffffffff
#define DPM_TABLE_358__UvdLevel_0_VclkFrequency__SHIFT 0x0
#define DPM_TABLE_359__UvdLevel_0_DclkFrequency_MASK 0xffffffff
#define DPM_TABLE_359__UvdLevel_0_DclkFrequency__SHIFT 0x0
#define DPM_TABLE_360__UvdLevel_0_VclkDivider_MASK 0xff
#define DPM_TABLE_360__UvdLevel_0_VclkDivider__SHIFT 0x0
#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases_MASK 0xff00
#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases__SHIFT 0x8
#define DPM_TABLE_360__UvdLevel_0_MinVddc_MASK 0xffff0000
#define DPM_TABLE_360__UvdLevel_0_MinVddc__SHIFT 0x10
#define DPM_TABLE_361__UvdLevel_0_padding_2_MASK 0xff
#define DPM_TABLE_361__UvdLevel_0_padding_2__SHIFT 0x0
#define DPM_TABLE_361__UvdLevel_0_padding_1_MASK 0xff00
#define DPM_TABLE_361__UvdLevel_0_padding_1__SHIFT 0x8
#define DPM_TABLE_361__UvdLevel_0_padding_0_MASK 0xff0000
#define DPM_TABLE_361__UvdLevel_0_padding_0__SHIFT 0x10
#define DPM_TABLE_361__UvdLevel_0_DclkDivider_MASK 0xff000000
#define DPM_TABLE_361__UvdLevel_0_DclkDivider__SHIFT 0x18
#define DPM_TABLE_362__UvdLevel_1_VclkFrequency_MASK 0xffffffff
#define DPM_TABLE_362__UvdLevel_1_VclkFrequency__SHIFT 0x0
#define DPM_TABLE_363__UvdLevel_1_DclkFrequency_MASK 0xffffffff
#define DPM_TABLE_363__UvdLevel_1_DclkFrequency__SHIFT 0x0
#define DPM_TABLE_364__UvdLevel_1_VclkDivider_MASK 0xff
#define DPM_TABLE_364__UvdLevel_1_VclkDivider__SHIFT 0x0
#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases_MASK 0xff00
#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases__SHIFT 0x8
#define DPM_TABLE_364__UvdLevel_1_MinVddc_MASK 0xffff0000
#define DPM_TABLE_364__UvdLevel_1_MinVddc__SHIFT 0x10
#define DPM_TABLE_365__UvdLevel_1_padding_2_MASK 0xff
#define DPM_TABLE_365__UvdLevel_1_padding_2__SHIFT 0x0
#define DPM_TABLE_365__UvdLevel_1_padding_1_MASK 0xff00
#define DPM_TABLE_365__UvdLevel_1_padding_1__SHIFT 0x8
#define DPM_TABLE_365__UvdLevel_1_padding_0_MASK 0xff0000
#define DPM_TABLE_365__UvdLevel_1_padding_0__SHIFT 0x10
#define DPM_TABLE_365__UvdLevel_1_DclkDivider_MASK 0xff000000
#define DPM_TABLE_365__UvdLevel_1_DclkDivider__SHIFT 0x18
#define DPM_TABLE_366__UvdLevel_2_VclkFrequency_MASK 0xffffffff
#define DPM_TABLE_366__UvdLevel_2_VclkFrequency__SHIFT 0x0
#define DPM_TABLE_367__UvdLevel_2_DclkFrequency_MASK 0xffffffff
#define DPM_TABLE_367__UvdLevel_2_DclkFrequency__SHIFT 0x0
#define DPM_TABLE_368__UvdLevel_2_VclkDivider_MASK 0xff
#define DPM_TABLE_368__UvdLevel_2_VclkDivider__SHIFT 0x0
#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases_MASK 0xff00
#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases__SHIFT 0x8
#define DPM_TABLE_368__UvdLevel_2_MinVddc_MASK 0xffff0000
#define DPM_TABLE_368__UvdLevel_2_MinVddc__SHIFT 0x10
#define DPM_TABLE_369__UvdLevel_2_padding_2_MASK 0xff
#define DPM_TABLE_369__UvdLevel_2_padding_2__SHIFT 0x0
#define DPM_TABLE_369__UvdLevel_2_padding_1_MASK 0xff00
#define DPM_TABLE_369__UvdLevel_2_padding_1__SHIFT 0x8
#define DPM_TABLE_369__UvdLevel_2_padding_0_MASK 0xff0000
#define DPM_TABLE_369__UvdLevel_2_padding_0__SHIFT 0x10
#define DPM_TABLE_369__UvdLevel_2_DclkDivider_MASK 0xff000000
#define DPM_TABLE_369__UvdLevel_2_DclkDivider__SHIFT 0x18
#define DPM_TABLE_370__UvdLevel_3_VclkFrequency_MASK 0xffffffff
#define DPM_TABLE_370__UvdLevel_3_VclkFrequency__SHIFT 0x0
#define DPM_TABLE_371__UvdLevel_3_DclkFrequency_MASK 0xffffffff
#define DPM_TABLE_371__UvdLevel_3_DclkFrequency__SHIFT 0x0
#define DPM_TABLE_372__UvdLevel_3_VclkDivider_MASK 0xff
#define DPM_TABLE_372__UvdLevel_3_VclkDivider__SHIFT 0x0
#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases_MASK 0xff00
#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases__SHIFT 0x8
#define DPM_TABLE_372__UvdLevel_3_MinVddc_MASK 0xffff0000
#define DPM_TABLE_372__UvdLevel_3_MinVddc__SHIFT 0x10
#define DPM_TABLE_373__UvdLevel_3_padding_2_MASK 0xff
#define DPM_TABLE_373__UvdLevel_3_padding_2__SHIFT 0x0
#define DPM_TABLE_373__UvdLevel_3_padding_1_MASK 0xff00
#define DPM_TABLE_373__UvdLevel_3_padding_1__SHIFT 0x8
#define DPM_TABLE_373__UvdLevel_3_padding_0_MASK 0xff0000
#define DPM_TABLE_373__UvdLevel_3_padding_0__SHIFT 0x10
#define DPM_TABLE_373__UvdLevel_3_DclkDivider_MASK 0xff000000
#define DPM_TABLE_373__UvdLevel_3_DclkDivider__SHIFT 0x18
#define DPM_TABLE_374__UvdLevel_4_VclkFrequency_MASK 0xffffffff
#define DPM_TABLE_374__UvdLevel_4_VclkFrequency__SHIFT 0x0
#define DPM_TABLE_375__UvdLevel_4_DclkFrequency_MASK 0xffffffff
#define DPM_TABLE_375__UvdLevel_4_DclkFrequency__SHIFT 0x0
#define DPM_TABLE_376__UvdLevel_4_VclkDivider_MASK 0xff
#define DPM_TABLE_376__UvdLevel_4_VclkDivider__SHIFT 0x0
#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases_MASK 0xff00
#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases__SHIFT 0x8
#define DPM_TABLE_376__UvdLevel_4_MinVddc_MASK 0xffff0000
#define DPM_TABLE_376__UvdLevel_4_MinVddc__SHIFT 0x10
#define DPM_TABLE_377__UvdLevel_4_padding_2_MASK 0xff
#define DPM_TABLE_377__UvdLevel_4_padding_2__SHIFT 0x0
#define DPM_TABLE_377__UvdLevel_4_padding_1_MASK 0xff00
#define DPM_TABLE_377__UvdLevel_4_padding_1__SHIFT 0x8
#define DPM_TABLE_377__UvdLevel_4_padding_0_MASK 0xff0000
#define DPM_TABLE_377__UvdLevel_4_padding_0__SHIFT 0x10
#define DPM_TABLE_377__UvdLevel_4_DclkDivider_MASK 0xff000000
#define DPM_TABLE_377__UvdLevel_4_DclkDivider__SHIFT 0x18
#define DPM_TABLE_378__UvdLevel_5_VclkFrequency_MASK 0xffffffff
#define DPM_TABLE_378__UvdLevel_5_VclkFrequency__SHIFT 0x0
#define DPM_TABLE_379__UvdLevel_5_DclkFrequency_MASK 0xffffffff
#define DPM_TABLE_379__UvdLevel_5_DclkFrequency__SHIFT 0x0
#define DPM_TABLE_380__UvdLevel_5_VclkDivider_MASK 0xff
#define DPM_TABLE_380__UvdLevel_5_VclkDivider__SHIFT 0x0
#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases_MASK 0xff00
#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8
#define DPM_TABLE_380__UvdLevel_5_MinVddc_MASK 0xffff0000
#define DPM_TABLE_380__UvdLevel_5_MinVddc__SHIFT 0x10
#define DPM_TABLE_381__UvdLevel_5_padding_2_MASK 0xff
#define DPM_TABLE_381__UvdLevel_5_padding_2__SHIFT 0x0
#define DPM_TABLE_381__UvdLevel_5_padding_1_MASK 0xff00
#define DPM_TABLE_381__UvdLevel_5_padding_1__SHIFT 0x8
#define DPM_TABLE_381__UvdLevel_5_padding_0_MASK 0xff0000
#define DPM_TABLE_381__UvdLevel_5_padding_0__SHIFT 0x10
#define DPM_TABLE_381__UvdLevel_5_DclkDivider_MASK 0xff000000
#define DPM_TABLE_381__UvdLevel_5_DclkDivider__SHIFT 0x18
#define DPM_TABLE_382__UvdLevel_6_VclkFrequency_MASK 0xffffffff
#define DPM_TABLE_382__UvdLevel_6_VclkFrequency__SHIFT 0x0
#define DPM_TABLE_383__UvdLevel_6_DclkFrequency_MASK 0xffffffff
#define DPM_TABLE_383__UvdLevel_6_DclkFrequency__SHIFT 0x0
#define DPM_TABLE_384__UvdLevel_6_VclkDivider_MASK 0xff
#define DPM_TABLE_384__UvdLevel_6_VclkDivider__SHIFT 0x0
#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases_MASK 0xff00
#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases__SHIFT 0x8
#define DPM_TABLE_384__UvdLevel_6_MinVddc_MASK 0xffff0000
#define DPM_TABLE_384__UvdLevel_6_MinVddc__SHIFT 0x10
#define DPM_TABLE_385__UvdLevel_6_padding_2_MASK 0xff
#define DPM_TABLE_385__UvdLevel_6_padding_2__SHIFT 0x0
#define DPM_TABLE_385__UvdLevel_6_padding_1_MASK 0xff00
#define DPM_TABLE_385__UvdLevel_6_padding_1__SHIFT 0x8
#define DPM_TABLE_385__UvdLevel_6_padding_0_MASK 0xff0000
#define DPM_TABLE_385__UvdLevel_6_padding_0__SHIFT 0x10
#define DPM_TABLE_385__UvdLevel_6_DclkDivider_MASK 0xff000000
#define DPM_TABLE_385__UvdLevel_6_DclkDivider__SHIFT 0x18
#define DPM_TABLE_386__UvdLevel_7_VclkFrequency_MASK 0xffffffff
#define DPM_TABLE_386__UvdLevel_7_VclkFrequency__SHIFT 0x0
#define DPM_TABLE_387__UvdLevel_7_DclkFrequency_MASK 0xffffffff
#define DPM_TABLE_387__UvdLevel_7_DclkFrequency__SHIFT 0x0
#define DPM_TABLE_388__UvdLevel_7_VclkDivider_MASK 0xff
#define DPM_TABLE_388__UvdLevel_7_VclkDivider__SHIFT 0x0
#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00
#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases__SHIFT 0x8
#define DPM_TABLE_388__UvdLevel_7_MinVddc_MASK 0xffff0000
#define DPM_TABLE_388__UvdLevel_7_MinVddc__SHIFT 0x10
#define DPM_TABLE_389__UvdLevel_7_padding_2_MASK 0xff
#define DPM_TABLE_389__UvdLevel_7_padding_2__SHIFT 0x0
#define DPM_TABLE_389__UvdLevel_7_padding_1_MASK 0xff00
#define DPM_TABLE_389__UvdLevel_7_padding_1__SHIFT 0x8
#define DPM_TABLE_389__UvdLevel_7_padding_0_MASK 0xff0000
#define DPM_TABLE_389__UvdLevel_7_padding_0__SHIFT 0x10
#define DPM_TABLE_389__UvdLevel_7_DclkDivider_MASK 0xff000000
#define DPM_TABLE_389__UvdLevel_7_DclkDivider__SHIFT 0x18
#define DPM_TABLE_390__VceLevel_0_Frequency_MASK 0xffffffff
#define DPM_TABLE_390__VceLevel_0_Frequency__SHIFT 0x0
#define DPM_TABLE_391__VceLevel_0_Divider_MASK 0xff
#define DPM_TABLE_391__VceLevel_0_Divider__SHIFT 0x0
#define DPM_TABLE_391__VceLevel_0_MinPhases_MASK 0xff00
#define DPM_TABLE_391__VceLevel_0_MinPhases__SHIFT 0x8
#define DPM_TABLE_391__VceLevel_0_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_391__VceLevel_0_MinVoltage__SHIFT 0x10
#define DPM_TABLE_392__VceLevel_1_Frequency_MASK 0xffffffff
#define DPM_TABLE_392__VceLevel_1_Frequency__SHIFT 0x0
#define DPM_TABLE_393__VceLevel_1_Divider_MASK 0xff
#define DPM_TABLE_393__VceLevel_1_Divider__SHIFT 0x0
#define DPM_TABLE_393__VceLevel_1_MinPhases_MASK 0xff00
#define DPM_TABLE_393__VceLevel_1_MinPhases__SHIFT 0x8
#define DPM_TABLE_393__VceLevel_1_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_393__VceLevel_1_MinVoltage__SHIFT 0x10
#define DPM_TABLE_394__VceLevel_2_Frequency_MASK 0xffffffff
#define DPM_TABLE_394__VceLevel_2_Frequency__SHIFT 0x0
#define DPM_TABLE_395__VceLevel_2_Divider_MASK 0xff
#define DPM_TABLE_395__VceLevel_2_Divider__SHIFT 0x0
#define DPM_TABLE_395__VceLevel_2_MinPhases_MASK 0xff00
#define DPM_TABLE_395__VceLevel_2_MinPhases__SHIFT 0x8
#define DPM_TABLE_395__VceLevel_2_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_395__VceLevel_2_MinVoltage__SHIFT 0x10
#define DPM_TABLE_396__VceLevel_3_Frequency_MASK 0xffffffff
#define DPM_TABLE_396__VceLevel_3_Frequency__SHIFT 0x0
#define DPM_TABLE_397__VceLevel_3_Divider_MASK 0xff
#define DPM_TABLE_397__VceLevel_3_Divider__SHIFT 0x0
#define DPM_TABLE_397__VceLevel_3_MinPhases_MASK 0xff00
#define DPM_TABLE_397__VceLevel_3_MinPhases__SHIFT 0x8
#define DPM_TABLE_397__VceLevel_3_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_397__VceLevel_3_MinVoltage__SHIFT 0x10
#define DPM_TABLE_398__VceLevel_4_Frequency_MASK 0xffffffff
#define DPM_TABLE_398__VceLevel_4_Frequency__SHIFT 0x0
#define DPM_TABLE_399__VceLevel_4_Divider_MASK 0xff
#define DPM_TABLE_399__VceLevel_4_Divider__SHIFT 0x0
#define DPM_TABLE_399__VceLevel_4_MinPhases_MASK 0xff00
#define DPM_TABLE_399__VceLevel_4_MinPhases__SHIFT 0x8
#define DPM_TABLE_399__VceLevel_4_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_399__VceLevel_4_MinVoltage__SHIFT 0x10
#define DPM_TABLE_400__VceLevel_5_Frequency_MASK 0xffffffff
#define DPM_TABLE_400__VceLevel_5_Frequency__SHIFT 0x0
#define DPM_TABLE_401__VceLevel_5_Divider_MASK 0xff
#define DPM_TABLE_401__VceLevel_5_Divider__SHIFT 0x0
#define DPM_TABLE_401__VceLevel_5_MinPhases_MASK 0xff00
#define DPM_TABLE_401__VceLevel_5_MinPhases__SHIFT 0x8
#define DPM_TABLE_401__VceLevel_5_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_401__VceLevel_5_MinVoltage__SHIFT 0x10
#define DPM_TABLE_402__VceLevel_6_Frequency_MASK 0xffffffff
#define DPM_TABLE_402__VceLevel_6_Frequency__SHIFT 0x0
#define DPM_TABLE_403__VceLevel_6_Divider_MASK 0xff
#define DPM_TABLE_403__VceLevel_6_Divider__SHIFT 0x0
#define DPM_TABLE_403__VceLevel_6_MinPhases_MASK 0xff00
#define DPM_TABLE_403__VceLevel_6_MinPhases__SHIFT 0x8
#define DPM_TABLE_403__VceLevel_6_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_403__VceLevel_6_MinVoltage__SHIFT 0x10
#define DPM_TABLE_404__VceLevel_7_Frequency_MASK 0xffffffff
#define DPM_TABLE_404__VceLevel_7_Frequency__SHIFT 0x0
#define DPM_TABLE_405__VceLevel_7_Divider_MASK 0xff
#define DPM_TABLE_405__VceLevel_7_Divider__SHIFT 0x0
#define DPM_TABLE_405__VceLevel_7_MinPhases_MASK 0xff00
#define DPM_TABLE_405__VceLevel_7_MinPhases__SHIFT 0x8
#define DPM_TABLE_405__VceLevel_7_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_405__VceLevel_7_MinVoltage__SHIFT 0x10
#define DPM_TABLE_406__AcpLevel_0_Frequency_MASK 0xffffffff
#define DPM_TABLE_406__AcpLevel_0_Frequency__SHIFT 0x0
#define DPM_TABLE_407__AcpLevel_0_Divider_MASK 0xff
#define DPM_TABLE_407__AcpLevel_0_Divider__SHIFT 0x0
#define DPM_TABLE_407__AcpLevel_0_MinPhases_MASK 0xff00
#define DPM_TABLE_407__AcpLevel_0_MinPhases__SHIFT 0x8
#define DPM_TABLE_407__AcpLevel_0_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_407__AcpLevel_0_MinVoltage__SHIFT 0x10
#define DPM_TABLE_408__AcpLevel_1_Frequency_MASK 0xffffffff
#define DPM_TABLE_408__AcpLevel_1_Frequency__SHIFT 0x0
#define DPM_TABLE_409__AcpLevel_1_Divider_MASK 0xff
#define DPM_TABLE_409__AcpLevel_1_Divider__SHIFT 0x0
#define DPM_TABLE_409__AcpLevel_1_MinPhases_MASK 0xff00
#define DPM_TABLE_409__AcpLevel_1_MinPhases__SHIFT 0x8
#define DPM_TABLE_409__AcpLevel_1_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_409__AcpLevel_1_MinVoltage__SHIFT 0x10
#define DPM_TABLE_410__AcpLevel_2_Frequency_MASK 0xffffffff
#define DPM_TABLE_410__AcpLevel_2_Frequency__SHIFT 0x0
#define DPM_TABLE_411__AcpLevel_2_Divider_MASK 0xff
#define DPM_TABLE_411__AcpLevel_2_Divider__SHIFT 0x0
#define DPM_TABLE_411__AcpLevel_2_MinPhases_MASK 0xff00
#define DPM_TABLE_411__AcpLevel_2_MinPhases__SHIFT 0x8
#define DPM_TABLE_411__AcpLevel_2_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_411__AcpLevel_2_MinVoltage__SHIFT 0x10
#define DPM_TABLE_412__AcpLevel_3_Frequency_MASK 0xffffffff
#define DPM_TABLE_412__AcpLevel_3_Frequency__SHIFT 0x0
#define DPM_TABLE_413__AcpLevel_3_Divider_MASK 0xff
#define DPM_TABLE_413__AcpLevel_3_Divider__SHIFT 0x0
#define DPM_TABLE_413__AcpLevel_3_MinPhases_MASK 0xff00
#define DPM_TABLE_413__AcpLevel_3_MinPhases__SHIFT 0x8
#define DPM_TABLE_413__AcpLevel_3_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_413__AcpLevel_3_MinVoltage__SHIFT 0x10
#define DPM_TABLE_414__AcpLevel_4_Frequency_MASK 0xffffffff
#define DPM_TABLE_414__AcpLevel_4_Frequency__SHIFT 0x0
#define DPM_TABLE_415__AcpLevel_4_Divider_MASK 0xff
#define DPM_TABLE_415__AcpLevel_4_Divider__SHIFT 0x0
#define DPM_TABLE_415__AcpLevel_4_MinPhases_MASK 0xff00
#define DPM_TABLE_415__AcpLevel_4_MinPhases__SHIFT 0x8
#define DPM_TABLE_415__AcpLevel_4_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_415__AcpLevel_4_MinVoltage__SHIFT 0x10
#define DPM_TABLE_416__AcpLevel_5_Frequency_MASK 0xffffffff
#define DPM_TABLE_416__AcpLevel_5_Frequency__SHIFT 0x0
#define DPM_TABLE_417__AcpLevel_5_Divider_MASK 0xff
#define DPM_TABLE_417__AcpLevel_5_Divider__SHIFT 0x0
#define DPM_TABLE_417__AcpLevel_5_MinPhases_MASK 0xff00
#define DPM_TABLE_417__AcpLevel_5_MinPhases__SHIFT 0x8
#define DPM_TABLE_417__AcpLevel_5_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_417__AcpLevel_5_MinVoltage__SHIFT 0x10
#define DPM_TABLE_418__AcpLevel_6_Frequency_MASK 0xffffffff
#define DPM_TABLE_418__AcpLevel_6_Frequency__SHIFT 0x0
#define DPM_TABLE_419__AcpLevel_6_Divider_MASK 0xff
#define DPM_TABLE_419__AcpLevel_6_Divider__SHIFT 0x0
#define DPM_TABLE_419__AcpLevel_6_MinPhases_MASK 0xff00
#define DPM_TABLE_419__AcpLevel_6_MinPhases__SHIFT 0x8
#define DPM_TABLE_419__AcpLevel_6_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_419__AcpLevel_6_MinVoltage__SHIFT 0x10
#define DPM_TABLE_420__AcpLevel_7_Frequency_MASK 0xffffffff
#define DPM_TABLE_420__AcpLevel_7_Frequency__SHIFT 0x0
#define DPM_TABLE_421__AcpLevel_7_Divider_MASK 0xff
#define DPM_TABLE_421__AcpLevel_7_Divider__SHIFT 0x0
#define DPM_TABLE_421__AcpLevel_7_MinPhases_MASK 0xff00
#define DPM_TABLE_421__AcpLevel_7_MinPhases__SHIFT 0x8
#define DPM_TABLE_421__AcpLevel_7_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_421__AcpLevel_7_MinVoltage__SHIFT 0x10
#define DPM_TABLE_422__SamuLevel_0_Frequency_MASK 0xffffffff
#define DPM_TABLE_422__SamuLevel_0_Frequency__SHIFT 0x0
#define DPM_TABLE_423__SamuLevel_0_Divider_MASK 0xff
#define DPM_TABLE_423__SamuLevel_0_Divider__SHIFT 0x0
#define DPM_TABLE_423__SamuLevel_0_MinPhases_MASK 0xff00
#define DPM_TABLE_423__SamuLevel_0_MinPhases__SHIFT 0x8
#define DPM_TABLE_423__SamuLevel_0_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_423__SamuLevel_0_MinVoltage__SHIFT 0x10
#define DPM_TABLE_424__SamuLevel_1_Frequency_MASK 0xffffffff
#define DPM_TABLE_424__SamuLevel_1_Frequency__SHIFT 0x0
#define DPM_TABLE_425__SamuLevel_1_Divider_MASK 0xff
#define DPM_TABLE_425__SamuLevel_1_Divider__SHIFT 0x0
#define DPM_TABLE_425__SamuLevel_1_MinPhases_MASK 0xff00
#define DPM_TABLE_425__SamuLevel_1_MinPhases__SHIFT 0x8
#define DPM_TABLE_425__SamuLevel_1_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_425__SamuLevel_1_MinVoltage__SHIFT 0x10
#define DPM_TABLE_426__SamuLevel_2_Frequency_MASK 0xffffffff
#define DPM_TABLE_426__SamuLevel_2_Frequency__SHIFT 0x0
#define DPM_TABLE_427__SamuLevel_2_Divider_MASK 0xff
#define DPM_TABLE_427__SamuLevel_2_Divider__SHIFT 0x0
#define DPM_TABLE_427__SamuLevel_2_MinPhases_MASK 0xff00
#define DPM_TABLE_427__SamuLevel_2_MinPhases__SHIFT 0x8
#define DPM_TABLE_427__SamuLevel_2_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_427__SamuLevel_2_MinVoltage__SHIFT 0x10
#define DPM_TABLE_428__SamuLevel_3_Frequency_MASK 0xffffffff
#define DPM_TABLE_428__SamuLevel_3_Frequency__SHIFT 0x0
#define DPM_TABLE_429__SamuLevel_3_Divider_MASK 0xff
#define DPM_TABLE_429__SamuLevel_3_Divider__SHIFT 0x0
#define DPM_TABLE_429__SamuLevel_3_MinPhases_MASK 0xff00
#define DPM_TABLE_429__SamuLevel_3_MinPhases__SHIFT 0x8
#define DPM_TABLE_429__SamuLevel_3_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_429__SamuLevel_3_MinVoltage__SHIFT 0x10
#define DPM_TABLE_430__SamuLevel_4_Frequency_MASK 0xffffffff
#define DPM_TABLE_430__SamuLevel_4_Frequency__SHIFT 0x0
#define DPM_TABLE_431__SamuLevel_4_Divider_MASK 0xff
#define DPM_TABLE_431__SamuLevel_4_Divider__SHIFT 0x0
#define DPM_TABLE_431__SamuLevel_4_MinPhases_MASK 0xff00
#define DPM_TABLE_431__SamuLevel_4_MinPhases__SHIFT 0x8
#define DPM_TABLE_431__SamuLevel_4_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_431__SamuLevel_4_MinVoltage__SHIFT 0x10
#define DPM_TABLE_432__SamuLevel_5_Frequency_MASK 0xffffffff
#define DPM_TABLE_432__SamuLevel_5_Frequency__SHIFT 0x0
#define DPM_TABLE_433__SamuLevel_5_Divider_MASK 0xff
#define DPM_TABLE_433__SamuLevel_5_Divider__SHIFT 0x0
#define DPM_TABLE_433__SamuLevel_5_MinPhases_MASK 0xff00
#define DPM_TABLE_433__SamuLevel_5_MinPhases__SHIFT 0x8
#define DPM_TABLE_433__SamuLevel_5_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_433__SamuLevel_5_MinVoltage__SHIFT 0x10
#define DPM_TABLE_434__SamuLevel_6_Frequency_MASK 0xffffffff
#define DPM_TABLE_434__SamuLevel_6_Frequency__SHIFT 0x0
#define DPM_TABLE_435__SamuLevel_6_Divider_MASK 0xff
#define DPM_TABLE_435__SamuLevel_6_Divider__SHIFT 0x0
#define DPM_TABLE_435__SamuLevel_6_MinPhases_MASK 0xff00
#define DPM_TABLE_435__SamuLevel_6_MinPhases__SHIFT 0x8
#define DPM_TABLE_435__SamuLevel_6_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_435__SamuLevel_6_MinVoltage__SHIFT 0x10
#define DPM_TABLE_436__SamuLevel_7_Frequency_MASK 0xffffffff
#define DPM_TABLE_436__SamuLevel_7_Frequency__SHIFT 0x0
#define DPM_TABLE_437__SamuLevel_7_Divider_MASK 0xff
#define DPM_TABLE_437__SamuLevel_7_Divider__SHIFT 0x0
#define DPM_TABLE_437__SamuLevel_7_MinPhases_MASK 0xff00
#define DPM_TABLE_437__SamuLevel_7_MinPhases__SHIFT 0x8
#define DPM_TABLE_437__SamuLevel_7_MinVoltage_MASK 0xffff0000
#define DPM_TABLE_437__SamuLevel_7_MinVoltage__SHIFT 0x10
#define DPM_TABLE_438__Ulv_CcPwrDynRm_MASK 0xffffffff
#define DPM_TABLE_438__Ulv_CcPwrDynRm__SHIFT 0x0
#define DPM_TABLE_439__Ulv_CcPwrDynRm1_MASK 0xffffffff
#define DPM_TABLE_439__Ulv_CcPwrDynRm1__SHIFT 0x0
#define DPM_TABLE_440__Ulv_VddcPhase_MASK 0xff
#define DPM_TABLE_440__Ulv_VddcPhase__SHIFT 0x0
#define DPM_TABLE_440__Ulv_VddcOffsetVid_MASK 0xff00
#define DPM_TABLE_440__Ulv_VddcOffsetVid__SHIFT 0x8
#define DPM_TABLE_440__Ulv_VddcOffset_MASK 0xffff0000
#define DPM_TABLE_440__Ulv_VddcOffset__SHIFT 0x10
#define DPM_TABLE_441__Ulv_Reserved_MASK 0xffffffff
#define DPM_TABLE_441__Ulv_Reserved__SHIFT 0x0
#define DPM_TABLE_442__SclkStepSize_MASK 0xffffffff
#define DPM_TABLE_442__SclkStepSize__SHIFT 0x0
#define DPM_TABLE_443__Smio_0_MASK 0xffffffff
#define DPM_TABLE_443__Smio_0__SHIFT 0x0
#define DPM_TABLE_444__Smio_1_MASK 0xffffffff
#define DPM_TABLE_444__Smio_1__SHIFT 0x0
#define DPM_TABLE_445__Smio_2_MASK 0xffffffff
#define DPM_TABLE_445__Smio_2__SHIFT 0x0
#define DPM_TABLE_446__Smio_3_MASK 0xffffffff
#define DPM_TABLE_446__Smio_3__SHIFT 0x0
#define DPM_TABLE_447__Smio_4_MASK 0xffffffff
#define DPM_TABLE_447__Smio_4__SHIFT 0x0
#define DPM_TABLE_448__Smio_5_MASK 0xffffffff
#define DPM_TABLE_448__Smio_5__SHIFT 0x0
#define DPM_TABLE_449__Smio_6_MASK 0xffffffff
#define DPM_TABLE_449__Smio_6__SHIFT 0x0
#define DPM_TABLE_450__Smio_7_MASK 0xffffffff
#define DPM_TABLE_450__Smio_7__SHIFT 0x0
#define DPM_TABLE_451__Smio_8_MASK 0xffffffff
#define DPM_TABLE_451__Smio_8__SHIFT 0x0
#define DPM_TABLE_452__Smio_9_MASK 0xffffffff
#define DPM_TABLE_452__Smio_9__SHIFT 0x0
#define DPM_TABLE_453__Smio_10_MASK 0xffffffff
#define DPM_TABLE_453__Smio_10__SHIFT 0x0
#define DPM_TABLE_454__Smio_11_MASK 0xffffffff
#define DPM_TABLE_454__Smio_11__SHIFT 0x0
#define DPM_TABLE_455__Smio_12_MASK 0xffffffff
#define DPM_TABLE_455__Smio_12__SHIFT 0x0
#define DPM_TABLE_456__Smio_13_MASK 0xffffffff
#define DPM_TABLE_456__Smio_13__SHIFT 0x0
#define DPM_TABLE_457__Smio_14_MASK 0xffffffff
#define DPM_TABLE_457__Smio_14__SHIFT 0x0
#define DPM_TABLE_458__Smio_15_MASK 0xffffffff
#define DPM_TABLE_458__Smio_15__SHIFT 0x0
#define DPM_TABLE_459__Smio_16_MASK 0xffffffff
#define DPM_TABLE_459__Smio_16__SHIFT 0x0
#define DPM_TABLE_460__Smio_17_MASK 0xffffffff
#define DPM_TABLE_460__Smio_17__SHIFT 0x0
#define DPM_TABLE_461__Smio_18_MASK 0xffffffff
#define DPM_TABLE_461__Smio_18__SHIFT 0x0
#define DPM_TABLE_462__Smio_19_MASK 0xffffffff
#define DPM_TABLE_462__Smio_19__SHIFT 0x0
#define DPM_TABLE_463__Smio_20_MASK 0xffffffff
#define DPM_TABLE_463__Smio_20__SHIFT 0x0
#define DPM_TABLE_464__Smio_21_MASK 0xffffffff
#define DPM_TABLE_464__Smio_21__SHIFT 0x0
#define DPM_TABLE_465__Smio_22_MASK 0xffffffff
#define DPM_TABLE_465__Smio_22__SHIFT 0x0
#define DPM_TABLE_466__Smio_23_MASK 0xffffffff
#define DPM_TABLE_466__Smio_23__SHIFT 0x0
#define DPM_TABLE_467__Smio_24_MASK 0xffffffff
#define DPM_TABLE_467__Smio_24__SHIFT 0x0
#define DPM_TABLE_468__Smio_25_MASK 0xffffffff
#define DPM_TABLE_468__Smio_25__SHIFT 0x0
#define DPM_TABLE_469__Smio_26_MASK 0xffffffff
#define DPM_TABLE_469__Smio_26__SHIFT 0x0
#define DPM_TABLE_470__Smio_27_MASK 0xffffffff
#define DPM_TABLE_470__Smio_27__SHIFT 0x0
#define DPM_TABLE_471__Smio_28_MASK 0xffffffff
#define DPM_TABLE_471__Smio_28__SHIFT 0x0
#define DPM_TABLE_472__Smio_29_MASK 0xffffffff
#define DPM_TABLE_472__Smio_29__SHIFT 0x0
#define DPM_TABLE_473__Smio_30_MASK 0xffffffff
#define DPM_TABLE_473__Smio_30__SHIFT 0x0
#define DPM_TABLE_474__Smio_31_MASK 0xffffffff
#define DPM_TABLE_474__Smio_31__SHIFT 0x0
#define DPM_TABLE_475__SamuBootLevel_MASK 0xff
#define DPM_TABLE_475__SamuBootLevel__SHIFT 0x0
#define DPM_TABLE_475__AcpBootLevel_MASK 0xff00
#define DPM_TABLE_475__AcpBootLevel__SHIFT 0x8
#define DPM_TABLE_475__VceBootLevel_MASK 0xff0000
#define DPM_TABLE_475__VceBootLevel__SHIFT 0x10
#define DPM_TABLE_475__UvdBootLevel_MASK 0xff000000
#define DPM_TABLE_475__UvdBootLevel__SHIFT 0x18
#define DPM_TABLE_476__SAMUInterval_MASK 0xff
#define DPM_TABLE_476__SAMUInterval__SHIFT 0x0
#define DPM_TABLE_476__ACPInterval_MASK 0xff00
#define DPM_TABLE_476__ACPInterval__SHIFT 0x8
#define DPM_TABLE_476__VCEInterval_MASK 0xff0000
#define DPM_TABLE_476__VCEInterval__SHIFT 0x10
#define DPM_TABLE_476__UVDInterval_MASK 0xff000000
#define DPM_TABLE_476__UVDInterval__SHIFT 0x18
#define DPM_TABLE_477__GraphicsInterval_MASK 0xff
#define DPM_TABLE_477__GraphicsInterval__SHIFT 0x0
#define DPM_TABLE_477__GraphicsThermThrottleEnable_MASK 0xff00
#define DPM_TABLE_477__GraphicsThermThrottleEnable__SHIFT 0x8
#define DPM_TABLE_477__GraphicsVoltageChangeEnable_MASK 0xff0000
#define DPM_TABLE_477__GraphicsVoltageChangeEnable__SHIFT 0x10
#define DPM_TABLE_477__GraphicsBootLevel_MASK 0xff000000
#define DPM_TABLE_477__GraphicsBootLevel__SHIFT 0x18
#define DPM_TABLE_478__TemperatureLimitHigh_MASK 0xffff
#define DPM_TABLE_478__TemperatureLimitHigh__SHIFT 0x0
#define DPM_TABLE_478__ThermalInterval_MASK 0xff0000
#define DPM_TABLE_478__ThermalInterval__SHIFT 0x10
#define DPM_TABLE_478__VoltageInterval_MASK 0xff000000
#define DPM_TABLE_478__VoltageInterval__SHIFT 0x18
#define DPM_TABLE_479__MemoryVoltageChangeEnable_MASK 0xff
#define DPM_TABLE_479__MemoryVoltageChangeEnable__SHIFT 0x0
#define DPM_TABLE_479__MemoryBootLevel_MASK 0xff00
#define DPM_TABLE_479__MemoryBootLevel__SHIFT 0x8
#define DPM_TABLE_479__TemperatureLimitLow_MASK 0xffff0000
#define DPM_TABLE_479__TemperatureLimitLow__SHIFT 0x10
#define DPM_TABLE_480__VddcVddciDelta_MASK 0xffff
#define DPM_TABLE_480__VddcVddciDelta__SHIFT 0x0
#define DPM_TABLE_480__MemoryThermThrottleEnable_MASK 0xff0000
#define DPM_TABLE_480__MemoryThermThrottleEnable__SHIFT 0x10
#define DPM_TABLE_480__MemoryInterval_MASK 0xff000000
#define DPM_TABLE_480__MemoryInterval__SHIFT 0x18
#define DPM_TABLE_481__PhaseResponseTime_MASK 0xffff
#define DPM_TABLE_481__PhaseResponseTime__SHIFT 0x0
#define DPM_TABLE_481__VoltageResponseTime_MASK 0xffff0000
#define DPM_TABLE_481__VoltageResponseTime__SHIFT 0x10
#define DPM_TABLE_482__DTEMode_MASK 0xff
#define DPM_TABLE_482__DTEMode__SHIFT 0x0
#define DPM_TABLE_482__DTEInterval_MASK 0xff00
#define DPM_TABLE_482__DTEInterval__SHIFT 0x8
#define DPM_TABLE_482__PCIeGenInterval_MASK 0xff0000
#define DPM_TABLE_482__PCIeGenInterval__SHIFT 0x10
#define DPM_TABLE_482__PCIeBootLinkLevel_MASK 0xff000000
#define DPM_TABLE_482__PCIeBootLinkLevel__SHIFT 0x18
#define DPM_TABLE_483__ThermGpio_MASK 0xff
#define DPM_TABLE_483__ThermGpio__SHIFT 0x0
#define DPM_TABLE_483__AcDcGpio_MASK 0xff00
#define DPM_TABLE_483__AcDcGpio__SHIFT 0x8
#define DPM_TABLE_483__VRHotGpio_MASK 0xff0000
#define DPM_TABLE_483__VRHotGpio__SHIFT 0x10
#define DPM_TABLE_483__SVI2Enable_MASK 0xff000000
#define DPM_TABLE_483__SVI2Enable__SHIFT 0x18
#define DPM_TABLE_484__PPM_TemperatureLimit_MASK 0xffff
#define DPM_TABLE_484__PPM_TemperatureLimit__SHIFT 0x0
#define DPM_TABLE_484__PPM_PkgPwrLimit_MASK 0xffff0000
#define DPM_TABLE_484__PPM_PkgPwrLimit__SHIFT 0x10
#define DPM_TABLE_485__TargetTdp_MASK 0xffff
#define DPM_TABLE_485__TargetTdp__SHIFT 0x0
#define DPM_TABLE_485__DefaultTdp_MASK 0xffff0000
#define DPM_TABLE_485__DefaultTdp__SHIFT 0x10
#define DPM_TABLE_486__FpsLowThreshold_MASK 0xffff
#define DPM_TABLE_486__FpsLowThreshold__SHIFT 0x0
#define DPM_TABLE_486__FpsHighThreshold_MASK 0xffff0000
#define DPM_TABLE_486__FpsHighThreshold__SHIFT 0x10
#define DPM_TABLE_487__BAPMTI_R_0_1_0_MASK 0xffff
#define DPM_TABLE_487__BAPMTI_R_0_1_0__SHIFT 0x0
#define DPM_TABLE_487__BAPMTI_R_0_0_0_MASK 0xffff0000
#define DPM_TABLE_487__BAPMTI_R_0_0_0__SHIFT 0x10
#define DPM_TABLE_488__BAPMTI_R_1_0_0_MASK 0xffff
#define DPM_TABLE_488__BAPMTI_R_1_0_0__SHIFT 0x0
#define DPM_TABLE_488__BAPMTI_R_0_2_0_MASK 0xffff0000
#define DPM_TABLE_488__BAPMTI_R_0_2_0__SHIFT 0x10
#define DPM_TABLE_489__BAPMTI_R_1_2_0_MASK 0xffff
#define DPM_TABLE_489__BAPMTI_R_1_2_0__SHIFT 0x0
#define DPM_TABLE_489__BAPMTI_R_1_1_0_MASK 0xffff0000
#define DPM_TABLE_489__BAPMTI_R_1_1_0__SHIFT 0x10
#define DPM_TABLE_490__BAPMTI_R_2_1_0_MASK 0xffff
#define DPM_TABLE_490__BAPMTI_R_2_1_0__SHIFT 0x0
#define DPM_TABLE_490__BAPMTI_R_2_0_0_MASK 0xffff0000
#define DPM_TABLE_490__BAPMTI_R_2_0_0__SHIFT 0x10
#define DPM_TABLE_491__BAPMTI_R_3_0_0_MASK 0xffff
#define DPM_TABLE_491__BAPMTI_R_3_0_0__SHIFT 0x0
#define DPM_TABLE_491__BAPMTI_R_2_2_0_MASK 0xffff0000
#define DPM_TABLE_491__BAPMTI_R_2_2_0__SHIFT 0x10
#define DPM_TABLE_492__BAPMTI_R_3_2_0_MASK 0xffff
#define DPM_TABLE_492__BAPMTI_R_3_2_0__SHIFT 0x0
#define DPM_TABLE_492__BAPMTI_R_3_1_0_MASK 0xffff0000
#define DPM_TABLE_492__BAPMTI_R_3_1_0__SHIFT 0x10
#define DPM_TABLE_493__BAPMTI_R_4_1_0_MASK 0xffff
#define DPM_TABLE_493__BAPMTI_R_4_1_0__SHIFT 0x0
#define DPM_TABLE_493__BAPMTI_R_4_0_0_MASK 0xffff0000
#define DPM_TABLE_493__BAPMTI_R_4_0_0__SHIFT 0x10
#define DPM_TABLE_494__BAPMTI_RC_0_0_0_MASK 0xffff
#define DPM_TABLE_494__BAPMTI_RC_0_0_0__SHIFT 0x0
#define DPM_TABLE_494__BAPMTI_R_4_2_0_MASK 0xffff0000
#define DPM_TABLE_494__BAPMTI_R_4_2_0__SHIFT 0x10
#define DPM_TABLE_495__BAPMTI_RC_0_2_0_MASK 0xffff
#define DPM_TABLE_495__BAPMTI_RC_0_2_0__SHIFT 0x0
#define DPM_TABLE_495__BAPMTI_RC_0_1_0_MASK 0xffff0000
#define DPM_TABLE_495__BAPMTI_RC_0_1_0__SHIFT 0x10
#define DPM_TABLE_496__BAPMTI_RC_1_1_0_MASK 0xffff
#define DPM_TABLE_496__BAPMTI_RC_1_1_0__SHIFT 0x0
#define DPM_TABLE_496__BAPMTI_RC_1_0_0_MASK 0xffff0000
#define DPM_TABLE_496__BAPMTI_RC_1_0_0__SHIFT 0x10
#define DPM_TABLE_497__BAPMTI_RC_2_0_0_MASK 0xffff
#define DPM_TABLE_497__BAPMTI_RC_2_0_0__SHIFT 0x0
#define DPM_TABLE_497__BAPMTI_RC_1_2_0_MASK 0xffff0000
#define DPM_TABLE_497__BAPMTI_RC_1_2_0__SHIFT 0x10
#define DPM_TABLE_498__BAPMTI_RC_2_2_0_MASK 0xffff
#define DPM_TABLE_498__BAPMTI_RC_2_2_0__SHIFT 0x0
#define DPM_TABLE_498__BAPMTI_RC_2_1_0_MASK 0xffff0000
#define DPM_TABLE_498__BAPMTI_RC_2_1_0__SHIFT 0x10
#define DPM_TABLE_499__BAPMTI_RC_3_1_0_MASK 0xffff
#define DPM_TABLE_499__BAPMTI_RC_3_1_0__SHIFT 0x0
#define DPM_TABLE_499__BAPMTI_RC_3_0_0_MASK 0xffff0000
#define DPM_TABLE_499__BAPMTI_RC_3_0_0__SHIFT 0x10
#define DPM_TABLE_500__BAPMTI_RC_4_0_0_MASK 0xffff
#define DPM_TABLE_500__BAPMTI_RC_4_0_0__SHIFT 0x0
#define DPM_TABLE_500__BAPMTI_RC_3_2_0_MASK 0xffff0000
#define DPM_TABLE_500__BAPMTI_RC_3_2_0__SHIFT 0x10
#define DPM_TABLE_501__BAPMTI_RC_4_2_0_MASK 0xffff
#define DPM_TABLE_501__BAPMTI_RC_4_2_0__SHIFT 0x0
#define DPM_TABLE_501__BAPMTI_RC_4_1_0_MASK 0xffff0000
#define DPM_TABLE_501__BAPMTI_RC_4_1_0__SHIFT 0x10
#define DPM_TABLE_502__GpuTjHyst_MASK 0xff
#define DPM_TABLE_502__GpuTjHyst__SHIFT 0x0
#define DPM_TABLE_502__GpuTjMax_MASK 0xff00
#define DPM_TABLE_502__GpuTjMax__SHIFT 0x8
#define DPM_TABLE_502__DTETjOffset_MASK 0xff0000
#define DPM_TABLE_502__DTETjOffset__SHIFT 0x10
#define DPM_TABLE_502__DTEAmbientTempBase_MASK 0xff000000
#define DPM_TABLE_502__DTEAmbientTempBase__SHIFT 0x18
#define DPM_TABLE_503__BootVddci_MASK 0xffff
#define DPM_TABLE_503__BootVddci__SHIFT 0x0
#define DPM_TABLE_503__BootVddc_MASK 0xffff0000
#define DPM_TABLE_503__BootVddc__SHIFT 0x10
#define DPM_TABLE_504__padding_MASK 0xff
#define DPM_TABLE_504__padding__SHIFT 0x0
#define DPM_TABLE_504__PccGpio_MASK 0xff00
#define DPM_TABLE_504__PccGpio__SHIFT 0x8
#define DPM_TABLE_504__BootMVdd_MASK 0xffff0000
#define DPM_TABLE_504__BootMVdd__SHIFT 0x10
#define DPM_TABLE_505__BAPM_TEMP_GRADIENT_MASK 0xffffffff
#define DPM_TABLE_505__BAPM_TEMP_GRADIENT__SHIFT 0x0
#define DPM_TABLE_506__LowSclkInterruptThreshold_MASK 0xffffffff
#define DPM_TABLE_506__LowSclkInterruptThreshold__SHIFT 0x0
#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
#define TDC_STATUS__VDD_Boost_MASK 0xff
#define TDC_STATUS__VDD_Boost__SHIFT 0x0
#define TDC_STATUS__VDD_Throttle_MASK 0xff00
#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
#define TDC_MV_AVERAGE__IDD_MASK 0xffff
#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
#define TDC_VRM_LIMIT__IDD_MASK 0xffff
#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20
#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5
#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40
#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6
#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
#define FEATURE_STATUS__BAPM_ON_MASK 0x100
#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
#define FEATURE_STATUS__LPMX_ON_MASK 0x200
#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
#define FEATURE_STATUS__LHTC_ON_MASK 0x800
#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
#define FEATURE_STATUS__VPC_ON_MASK 0x1000
#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
#define FEATURE_STATUS__AVS_ON_MASK 0x10000
#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
#define FEATURE_STATUS__RESERVED__SHIFT 0x16
#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0_MASK 0xff0000
#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0__SHIFT 0x10
#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime_MASK 0xff000000
#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime__SHIFT 0x18
#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2_MASK 0xffffffff
#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2_MASK 0xff
#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2__SHIFT 0x0
#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1_MASK 0xff00
#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1__SHIFT 0x8
#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0_MASK 0xff0000
#define