| /* |
| * Copyright (C) 2017 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included |
| * in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef _thm_9_0_OFFSET_HEADER |
| #define _thm_9_0_OFFSET_HEADER |
| |
| |
| |
| // addressBlock: thm_thm_SmuThmDec |
| // base address: 0x59800 |
| #define mmTHM_TCON_CUR_TMP 0x0000 |
| #define mmTHM_TCON_CUR_TMP_BASE_IDX 0 |
| #define mmTHM_TCON_HTC 0x0001 |
| #define mmTHM_TCON_HTC_BASE_IDX 0 |
| #define mmTHM_TCON_THERM_TRIP 0x0002 |
| #define mmTHM_TCON_THERM_TRIP_BASE_IDX 0 |
| #define mmTHM_GPIO_PROCHOT_CTRL 0x0004 |
| #define mmTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0 |
| #define mmTHM_GPIO_THERMTRIP_CTRL 0x0005 |
| #define mmTHM_GPIO_THERMTRIP_CTRL_BASE_IDX 0 |
| #define mmTHM_GPIO_PWM_CTRL 0x0006 |
| #define mmTHM_GPIO_PWM_CTRL_BASE_IDX 0 |
| #define mmTHM_GPIO_TACHIN_CTRL 0x0007 |
| #define mmTHM_GPIO_TACHIN_CTRL_BASE_IDX 0 |
| #define mmTHM_GPIO_PUMPOUT_CTRL 0x0008 |
| #define mmTHM_GPIO_PUMPOUT_CTRL_BASE_IDX 0 |
| #define mmTHM_GPIO_PUMPIN_CTRL 0x0009 |
| #define mmTHM_GPIO_PUMPIN_CTRL_BASE_IDX 0 |
| #define mmTHM_THERMAL_INT_ENA 0x000a |
| #define mmTHM_THERMAL_INT_ENA_BASE_IDX 0 |
| #define mmTHM_THERMAL_INT_CTRL 0x000b |
| #define mmTHM_THERMAL_INT_CTRL_BASE_IDX 0 |
| #define mmTHM_THERMAL_INT_STATUS 0x000c |
| #define mmTHM_THERMAL_INT_STATUS_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL0_DATA 0x000d |
| #define mmTHM_TMON0_RDIL0_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL1_DATA 0x000e |
| #define mmTHM_TMON0_RDIL1_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL2_DATA 0x000f |
| #define mmTHM_TMON0_RDIL2_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL3_DATA 0x0010 |
| #define mmTHM_TMON0_RDIL3_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL4_DATA 0x0011 |
| #define mmTHM_TMON0_RDIL4_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL5_DATA 0x0012 |
| #define mmTHM_TMON0_RDIL5_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL6_DATA 0x0013 |
| #define mmTHM_TMON0_RDIL6_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL7_DATA 0x0014 |
| #define mmTHM_TMON0_RDIL7_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL8_DATA 0x0015 |
| #define mmTHM_TMON0_RDIL8_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL9_DATA 0x0016 |
| #define mmTHM_TMON0_RDIL9_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL10_DATA 0x0017 |
| #define mmTHM_TMON0_RDIL10_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL11_DATA 0x0018 |
| #define mmTHM_TMON0_RDIL11_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL12_DATA 0x0019 |
| #define mmTHM_TMON0_RDIL12_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL13_DATA 0x001a |
| #define mmTHM_TMON0_RDIL13_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL14_DATA 0x001b |
| #define mmTHM_TMON0_RDIL14_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIL15_DATA 0x001c |
| #define mmTHM_TMON0_RDIL15_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR0_DATA 0x001d |
| #define mmTHM_TMON0_RDIR0_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR1_DATA 0x001e |
| #define mmTHM_TMON0_RDIR1_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR2_DATA 0x001f |
| #define mmTHM_TMON0_RDIR2_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR3_DATA 0x0020 |
| #define mmTHM_TMON0_RDIR3_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR4_DATA 0x0021 |
| #define mmTHM_TMON0_RDIR4_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR5_DATA 0x0022 |
| #define mmTHM_TMON0_RDIR5_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR6_DATA 0x0023 |
| #define mmTHM_TMON0_RDIR6_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR7_DATA 0x0024 |
| #define mmTHM_TMON0_RDIR7_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR8_DATA 0x0025 |
| #define mmTHM_TMON0_RDIR8_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR9_DATA 0x0026 |
| #define mmTHM_TMON0_RDIR9_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR10_DATA 0x0027 |
| #define mmTHM_TMON0_RDIR10_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR11_DATA 0x0028 |
| #define mmTHM_TMON0_RDIR11_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR12_DATA 0x0029 |
| #define mmTHM_TMON0_RDIR12_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR13_DATA 0x002a |
| #define mmTHM_TMON0_RDIR13_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR14_DATA 0x002b |
| #define mmTHM_TMON0_RDIR14_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_RDIR15_DATA 0x002c |
| #define mmTHM_TMON0_RDIR15_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_INT_DATA 0x002d |
| #define mmTHM_TMON0_INT_DATA_BASE_IDX 0 |
| #define mmTHM_TMON0_DEBUG 0x0030 |
| #define mmTHM_TMON0_DEBUG_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL0_DATA 0x0031 |
| #define mmTHM_TMON1_RDIL0_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL1_DATA 0x0032 |
| #define mmTHM_TMON1_RDIL1_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL2_DATA 0x0033 |
| #define mmTHM_TMON1_RDIL2_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL3_DATA 0x0034 |
| #define mmTHM_TMON1_RDIL3_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL4_DATA 0x0035 |
| #define mmTHM_TMON1_RDIL4_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL5_DATA 0x0036 |
| #define mmTHM_TMON1_RDIL5_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL6_DATA 0x0037 |
| #define mmTHM_TMON1_RDIL6_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL7_DATA 0x0038 |
| #define mmTHM_TMON1_RDIL7_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL8_DATA 0x0039 |
| #define mmTHM_TMON1_RDIL8_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL9_DATA 0x003a |
| #define mmTHM_TMON1_RDIL9_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL10_DATA 0x003b |
| #define mmTHM_TMON1_RDIL10_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL11_DATA 0x003c |
| #define mmTHM_TMON1_RDIL11_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL12_DATA 0x003d |
| #define mmTHM_TMON1_RDIL12_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL13_DATA 0x003e |
| #define mmTHM_TMON1_RDIL13_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL14_DATA 0x003f |
| #define mmTHM_TMON1_RDIL14_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIL15_DATA 0x0040 |
| #define mmTHM_TMON1_RDIL15_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR0_DATA 0x0041 |
| #define mmTHM_TMON1_RDIR0_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR1_DATA 0x0042 |
| #define mmTHM_TMON1_RDIR1_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR2_DATA 0x0043 |
| #define mmTHM_TMON1_RDIR2_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR3_DATA 0x0044 |
| #define mmTHM_TMON1_RDIR3_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR4_DATA 0x0045 |
| #define mmTHM_TMON1_RDIR4_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR5_DATA 0x0046 |
| #define mmTHM_TMON1_RDIR5_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR6_DATA 0x0047 |
| #define mmTHM_TMON1_RDIR6_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR7_DATA 0x0048 |
| #define mmTHM_TMON1_RDIR7_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR8_DATA 0x0049 |
| #define mmTHM_TMON1_RDIR8_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR9_DATA 0x004a |
| #define mmTHM_TMON1_RDIR9_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR10_DATA 0x004b |
| #define mmTHM_TMON1_RDIR10_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR11_DATA 0x004c |
| #define mmTHM_TMON1_RDIR11_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR12_DATA 0x004d |
| #define mmTHM_TMON1_RDIR12_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR13_DATA 0x004e |
| #define mmTHM_TMON1_RDIR13_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR14_DATA 0x004f |
| #define mmTHM_TMON1_RDIR14_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_RDIR15_DATA 0x0050 |
| #define mmTHM_TMON1_RDIR15_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_INT_DATA 0x0051 |
| #define mmTHM_TMON1_INT_DATA_BASE_IDX 0 |
| #define mmTHM_TMON1_DEBUG 0x0054 |
| #define mmTHM_TMON1_DEBUG_BASE_IDX 0 |
| #define mmTHM_DIE1_TEMP 0x0055 |
| #define mmTHM_DIE1_TEMP_BASE_IDX 0 |
| #define mmTHM_DIE2_TEMP 0x0056 |
| #define mmTHM_DIE2_TEMP_BASE_IDX 0 |
| #define mmTHM_DIE3_TEMP 0x0057 |
| #define mmTHM_DIE3_TEMP_BASE_IDX 0 |
| #define mmCG_MULT_THERMAL_CTRL 0x0059 |
| #define mmCG_MULT_THERMAL_CTRL_BASE_IDX 0 |
| #define mmCG_MULT_THERMAL_STATUS 0x005a |
| #define mmCG_MULT_THERMAL_STATUS_BASE_IDX 0 |
| #define mmTHM_TMON0_COEFF 0x005e |
| #define mmTHM_TMON0_COEFF_BASE_IDX 0 |
| #define mmTHM_TMON1_COEFF 0x005f |
| #define mmTHM_TMON1_COEFF_BASE_IDX 0 |
| #define mmCG_FDO_CTRL0 0x0062 |
| #define mmCG_FDO_CTRL0_BASE_IDX 0 |
| #define mmCG_FDO_CTRL1 0x0063 |
| #define mmCG_FDO_CTRL1_BASE_IDX 0 |
| #define mmCG_FDO_CTRL2 0x0064 |
| #define mmCG_FDO_CTRL2_BASE_IDX 0 |
| #define mmCG_TACH_CTRL 0x0065 |
| #define mmCG_TACH_CTRL_BASE_IDX 0 |
| #define mmCG_TACH_STATUS 0x0066 |
| #define mmCG_TACH_STATUS_BASE_IDX 0 |
| #define mmCG_THERMAL_STATUS 0x0067 |
| #define mmCG_THERMAL_STATUS_BASE_IDX 0 |
| #define mmCG_PUMP_CTRL0 0x0068 |
| #define mmCG_PUMP_CTRL0_BASE_IDX 0 |
| #define mmCG_PUMP_CTRL1 0x0069 |
| #define mmCG_PUMP_CTRL1_BASE_IDX 0 |
| #define mmCG_PUMP_CTRL2 0x006a |
| #define mmCG_PUMP_CTRL2_BASE_IDX 0 |
| #define mmCG_PUMP_TACH_CTRL 0x006b |
| #define mmCG_PUMP_TACH_CTRL_BASE_IDX 0 |
| #define mmCG_PUMP_TACH_STATUS 0x006c |
| #define mmCG_PUMP_TACH_STATUS_BASE_IDX 0 |
| #define mmCG_PUMP_STATUS 0x006d |
| #define mmCG_PUMP_STATUS_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL0 0x006e |
| #define mmTHM_TCON_LOCAL0_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL1 0x006f |
| #define mmTHM_TCON_LOCAL1_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL2 0x0070 |
| #define mmTHM_TCON_LOCAL2_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL3 0x0071 |
| #define mmTHM_TCON_LOCAL3_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL4 0x0072 |
| #define mmTHM_TCON_LOCAL4_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL5 0x0073 |
| #define mmTHM_TCON_LOCAL5_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL6 0x0074 |
| #define mmTHM_TCON_LOCAL6_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL7 0x0075 |
| #define mmTHM_TCON_LOCAL7_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL8 0x0076 |
| #define mmTHM_TCON_LOCAL8_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL9 0x0077 |
| #define mmTHM_TCON_LOCAL9_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL10 0x0078 |
| #define mmTHM_TCON_LOCAL10_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL11 0x0079 |
| #define mmTHM_TCON_LOCAL11_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL12 0x007a |
| #define mmTHM_TCON_LOCAL12_BASE_IDX 0 |
| #define mmTHM_TCON_LOCAL13 0x007b |
| #define mmTHM_TCON_LOCAL13_BASE_IDX 0 |
| #define mmTHM_BACO_CNTL 0x007c |
| #define mmTHM_BACO_CNTL_BASE_IDX 0 |
| #define mmTHM_BACO_TIMING0 0x007d |
| #define mmTHM_BACO_TIMING0_BASE_IDX 0 |
| #define mmTHM_BACO_TIMING1 0x007e |
| #define mmTHM_BACO_TIMING1_BASE_IDX 0 |
| #define mmXTAL_CNTL 0x007f |
| #define mmXTAL_CNTL_BASE_IDX 0 |
| #define mmSBTSI_REMOTE_TEMP 0x008a |
| #define mmSBTSI_REMOTE_TEMP_BASE_IDX 0 |
| #define mmSBRMI_CONTROL 0x008b |
| #define mmSBRMI_CONTROL_BASE_IDX 0 |
| #define mmSBRMI_COMMAND 0x008c |
| #define mmSBRMI_COMMAND_BASE_IDX 0 |
| #define mmSBRMI_WRITE_DATA0 0x008d |
| #define mmSBRMI_WRITE_DATA0_BASE_IDX 0 |
| #define mmSBRMI_WRITE_DATA1 0x008e |
| #define mmSBRMI_WRITE_DATA1_BASE_IDX 0 |
| #define mmSBRMI_WRITE_DATA2 0x008f |
| #define mmSBRMI_WRITE_DATA2_BASE_IDX 0 |
| #define mmSBRMI_READ_DATA0 0x0090 |
| #define mmSBRMI_READ_DATA0_BASE_IDX 0 |
| #define mmSBRMI_READ_DATA1 0x0091 |
| #define mmSBRMI_READ_DATA1_BASE_IDX 0 |
| #define mmSBRMI_CORE_EN_NUMBER 0x0092 |
| #define mmSBRMI_CORE_EN_NUMBER_BASE_IDX 0 |
| #define mmSBRMI_CORE_EN_STATUS0 0x0093 |
| #define mmSBRMI_CORE_EN_STATUS0_BASE_IDX 0 |
| #define mmSBRMI_CORE_EN_STATUS1 0x0094 |
| #define mmSBRMI_CORE_EN_STATUS1_BASE_IDX 0 |
| #define mmSBRMI_APIC_STATUS0 0x0095 |
| #define mmSBRMI_APIC_STATUS0_BASE_IDX 0 |
| #define mmSBRMI_APIC_STATUS1 0x0096 |
| #define mmSBRMI_APIC_STATUS1_BASE_IDX 0 |
| #define mmSBRMI_MCE_STATUS0 0x0097 |
| #define mmSBRMI_MCE_STATUS0_BASE_IDX 0 |
| #define mmSBRMI_MCE_STATUS1 0x0098 |
| #define mmSBRMI_MCE_STATUS1_BASE_IDX 0 |
| #define mmSMBUS_CNTL0 0x0099 |
| #define mmSMBUS_CNTL0_BASE_IDX 0 |
| #define mmSMBUS_CNTL1 0x009a |
| #define mmSMBUS_CNTL1_BASE_IDX 0 |
| #define mmSMBUS_BLKWR_CMD_CTRL0 0x009b |
| #define mmSMBUS_BLKWR_CMD_CTRL0_BASE_IDX 0 |
| #define mmSMBUS_BLKWR_CMD_CTRL1 0x009c |
| #define mmSMBUS_BLKWR_CMD_CTRL1_BASE_IDX 0 |
| #define mmSMBUS_BLKRD_CMD_CTRL0 0x009d |
| #define mmSMBUS_BLKRD_CMD_CTRL0_BASE_IDX 0 |
| #define mmSMBUS_BLKRD_CMD_CTRL1 0x009e |
| #define mmSMBUS_BLKRD_CMD_CTRL1_BASE_IDX 0 |
| #define mmSMBUS_TIMING_CNTL0 0x009f |
| #define mmSMBUS_TIMING_CNTL0_BASE_IDX 0 |
| #define mmSMBUS_TIMING_CNTL1 0x00a0 |
| #define mmSMBUS_TIMING_CNTL1_BASE_IDX 0 |
| #define mmSMBUS_TIMING_CNTL2 0x00a1 |
| #define mmSMBUS_TIMING_CNTL2_BASE_IDX 0 |
| #define mmSMBUS_TRIGGER_CNTL 0x00a2 |
| #define mmSMBUS_TRIGGER_CNTL_BASE_IDX 0 |
| #define mmSMBUS_UDID_CNTL0 0x00a3 |
| #define mmSMBUS_UDID_CNTL0_BASE_IDX 0 |
| #define mmSMBUS_UDID_CNTL1 0x00a4 |
| #define mmSMBUS_UDID_CNTL1_BASE_IDX 0 |
| #define mmSMBUS_UDID_CNTL2 0x00a5 |
| #define mmSMBUS_UDID_CNTL2_BASE_IDX 0 |
| #define mmSMBUS_BACO_DUMMY 0x00a8 |
| #define mmSMBUS_BACO_DUMMY_BASE_IDX 0 |
| #define mmSMBUS_BACO_ADDR_RANGE0_LOW 0x00a9 |
| #define mmSMBUS_BACO_ADDR_RANGE0_LOW_BASE_IDX 0 |
| #define mmSMBUS_BACO_ADDR_RANGE0_HIGH 0x00aa |
| #define mmSMBUS_BACO_ADDR_RANGE0_HIGH_BASE_IDX 0 |
| #define mmSMBUS_BACO_ADDR_RANGE1_LOW 0x00ab |
| #define mmSMBUS_BACO_ADDR_RANGE1_LOW_BASE_IDX 0 |
| #define mmSMBUS_BACO_ADDR_RANGE1_HIGH 0x00ac |
| #define mmSMBUS_BACO_ADDR_RANGE1_HIGH_BASE_IDX 0 |
| #define mmSMBUS_BACO_ADDR_RANGE2_LOW 0x00ad |
| #define mmSMBUS_BACO_ADDR_RANGE2_LOW_BASE_IDX 0 |
| #define mmSMBUS_BACO_ADDR_RANGE2_HIGH 0x00ae |
| #define mmSMBUS_BACO_ADDR_RANGE2_HIGH_BASE_IDX 0 |
| #define mmSMBUS_BACO_ADDR_RANGE3_LOW 0x00af |
| #define mmSMBUS_BACO_ADDR_RANGE3_LOW_BASE_IDX 0 |
| #define mmSMBUS_BACO_ADDR_RANGE3_HIGH 0x00b0 |
| #define mmSMBUS_BACO_ADDR_RANGE3_HIGH_BASE_IDX 0 |
| #define mmSMBUS_BACO_ADDR_RANGE4_LOW 0x00b1 |
| #define mmSMBUS_BACO_ADDR_RANGE4_LOW_BASE_IDX 0 |
| #define mmSMBUS_BACO_ADDR_RANGE4_HIGH 0x00b2 |
| #define mmSMBUS_BACO_ADDR_RANGE4_HIGH_BASE_IDX 0 |
| #define mmTHM_GPIO_MACO_EN_CTRL 0x00bd |
| #define mmTHM_GPIO_MACO_EN_CTRL_BASE_IDX 0 |
| #define mmTHM_BACO_TIMING2 0x00bf |
| #define mmTHM_BACO_TIMING2_BASE_IDX 0 |
| #define mmTHM_BACO_TIMING 0x00c0 |
| #define mmTHM_BACO_TIMING_BASE_IDX 0 |
| #define mmTHM_TMON0_REMOTE_START 0x0100 |
| #define mmTHM_TMON0_REMOTE_START_BASE_IDX 0 |
| #define mmTHM_TMON0_REMOTE_END 0x013f |
| #define mmTHM_TMON0_REMOTE_END_BASE_IDX 0 |
| #define mmTHM_TMON1_REMOTE_START 0x0140 |
| #define mmTHM_TMON1_REMOTE_START_BASE_IDX 0 |
| #define mmTHM_TMON1_REMOTE_END 0x017f |
| #define mmTHM_TMON1_REMOTE_END_BASE_IDX 0 |
| #define mmTHM_TMON2_REMOTE_START 0x0180 |
| #define mmTHM_TMON2_REMOTE_START_BASE_IDX 0 |
| #define mmTHM_TMON2_REMOTE_END 0x01bf |
| #define mmTHM_TMON2_REMOTE_END_BASE_IDX 0 |
| #define mmTHM_TMON3_REMOTE_START 0x01c0 |
| #define mmTHM_TMON3_REMOTE_START_BASE_IDX 0 |
| #define mmTHM_TMON3_REMOTE_END 0x01ff |
| #define mmTHM_TMON3_REMOTE_END_BASE_IDX 0 |
| |
| #endif |
