| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* Copyright (c) 2022 Microchip Technology Inc */ |
| |
| /dts-v1/; |
| |
| #include "mpfs.dtsi" |
| #include "mpfs-sev-kit-fabric.dtsi" |
| |
| / { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| model = "Microchip PolarFire-SoC SEV Kit"; |
| compatible = "microchip,mpfs-sev-kit", "microchip,mpfs"; |
| |
| aliases { |
| ethernet0 = &mac1; |
| serial0 = &mmuart0; |
| serial1 = &mmuart1; |
| serial2 = &mmuart2; |
| serial3 = &mmuart3; |
| serial4 = &mmuart4; |
| }; |
| |
| chosen { |
| stdout-path = "serial1:115200n8"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| fabricbuf0ddrc: buffer@80000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x0 0x80000000 0x0 0x2000000>; |
| }; |
| |
| fabricbuf1ddrnc: buffer@c4000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x0 0xc4000000 0x0 0x4000000>; |
| }; |
| |
| fabricbuf2ddrncwcb: buffer@d4000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x0 0xd4000000 0x0 0x4000000>; |
| }; |
| }; |
| |
| ddrc_cache: memory@1000000000 { |
| device_type = "memory"; |
| reg = <0x10 0x0 0x0 0x76000000>; |
| }; |
| }; |
| |
| &i2c0 { |
| status = "okay"; |
| }; |
| |
| &gpio2 { |
| interrupts = <53>, <53>, <53>, <53>, |
| <53>, <53>, <53>, <53>, |
| <53>, <53>, <53>, <53>, |
| <53>, <53>, <53>, <53>, |
| <53>, <53>, <53>, <53>, |
| <53>, <53>, <53>, <53>, |
| <53>, <53>, <53>, <53>, |
| <53>, <53>, <53>, <53>; |
| status = "okay"; |
| }; |
| |
| &mac0 { |
| status = "okay"; |
| phy-mode = "sgmii"; |
| phy-handle = <&phy0>; |
| phy1: ethernet-phy@9 { |
| reg = <9>; |
| }; |
| phy0: ethernet-phy@8 { |
| reg = <8>; |
| }; |
| }; |
| |
| &mac1 { |
| status = "okay"; |
| phy-mode = "sgmii"; |
| phy-handle = <&phy1>; |
| }; |
| |
| &mbox { |
| status = "okay"; |
| }; |
| |
| &mmc { |
| status = "okay"; |
| bus-width = <4>; |
| disable-wp; |
| cap-sd-highspeed; |
| cap-mmc-highspeed; |
| mmc-ddr-1_8v; |
| mmc-hs200-1_8v; |
| sd-uhs-sdr12; |
| sd-uhs-sdr25; |
| sd-uhs-sdr50; |
| sd-uhs-sdr104; |
| }; |
| |
| &mmuart1 { |
| status = "okay"; |
| }; |
| |
| &mmuart2 { |
| status = "okay"; |
| }; |
| |
| &mmuart3 { |
| status = "okay"; |
| }; |
| |
| &mmuart4 { |
| status = "okay"; |
| }; |
| |
| &refclk { |
| clock-frequency = <125000000>; |
| }; |
| |
| &rtc { |
| status = "okay"; |
| }; |
| |
| &syscontroller { |
| status = "okay"; |
| }; |
| |
| &usb { |
| status = "okay"; |
| dr_mode = "otg"; |
| }; |