| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ |
| * |
| * Product Link: https://www.ti.com/tool/J721EXSOMXEVM |
| */ |
| |
| /dts-v1/; |
| |
| #include "k3-j721e.dtsi" |
| |
| / { |
| memory@80000000 { |
| device_type = "memory"; |
| /* 4G RAM */ |
| reg = <0x00000000 0x80000000 0x00000000 0x80000000>, |
| <0x00000008 0x80000000 0x00000000 0x80000000>; |
| }; |
| |
| reserved_memory: reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| secure_ddr: optee@9e800000 { |
| reg = <0x00 0x9e800000 0x00 0x01800000>; |
| alignment = <0x1000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa0000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa0100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa1000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa1100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa2000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core0_memory_region: r5f-memory@a2100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa2100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa3000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core1_memory_region: r5f-memory@a3100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa3100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa4000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core0_memory_region: r5f-memory@a4100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa4100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa5000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core1_memory_region: r5f-memory@a5100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa5100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c66_1_dma_memory_region: c66-dma-memory@a6000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa6000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c66_0_memory_region: c66-memory@a6100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa6100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c66_0_dma_memory_region: c66-dma-memory@a7000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa7000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c66_1_memory_region: c66-memory@a7100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa7100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c71_0_dma_memory_region: c71-dma-memory@a8000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa8000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c71_0_memory_region: c71-memory@a8100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa8100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| rtos_ipc_memory_region: ipc-memories@aa000000 { |
| reg = <0x00 0xaa000000 0x00 0x01c00000>; |
| alignment = <0x1000>; |
| no-map; |
| }; |
| }; |
| }; |
| |
| &wkup_pmx0 { |
| wkup_i2c0_pins_default: wkup-i2c0-default-pins { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ |
| J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ |
| >; |
| }; |
| |
| pmic_irq_pins_default: pmic-irq-default-pins { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0x0d4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */ |
| >; |
| }; |
| |
| mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ |
| J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ |
| J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ |
| J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ |
| J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ |
| J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ |
| J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ |
| J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ |
| J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ |
| J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ |
| J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ |
| >; |
| }; |
| |
| mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */ |
| J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */ |
| J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */ |
| J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */ |
| J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */ |
| J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */ |
| J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */ |
| J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */ |
| J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */ |
| J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */ |
| J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */ |
| J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */ |
| J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ |
| J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ |
| >; |
| }; |
| }; |
| |
| &wkup_i2c0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&wkup_i2c0_pins_default>; |
| clock-frequency = <400000>; |
| |
| eeprom@50 { |
| /* CAV24C256WE-GT3 */ |
| compatible = "atmel,24c256"; |
| reg = <0x50>; |
| }; |
| |
| tps659413: pmic@48 { |
| compatible = "ti,tps6594-q1"; |
| reg = <0x48>; |
| system-power-controller; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pmic_irq_pins_default>; |
| interrupt-parent = <&wkup_gpio0>; |
| interrupts = <9 IRQ_TYPE_EDGE_FALLING>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ti,primary-pmic; |
| buck12-supply = <&vsys_3v3>; |
| buck3-supply = <&vsys_3v3>; |
| buck4-supply = <&vsys_3v3>; |
| buck5-supply = <&vsys_3v3>; |
| ldo1-supply = <&vsys_3v3>; |
| ldo2-supply = <&vsys_3v3>; |
| ldo3-supply = <&vsys_3v3>; |
| ldo4-supply = <&vsys_3v3>; |
| |
| regulators { |
| bucka12: buck12 { |
| regulator-name = "vdd_cpu_avs"; |
| regulator-min-microvolt = <600000>; |
| regulator-max-microvolt = <900000>; |
| regulator-boot-on; |
| regulator-always-on; |
| bootph-pre-ram; |
| }; |
| |
| bucka3: buck3 { |
| regulator-name = "vdd_mcu_0v85"; |
| regulator-min-microvolt = <850000>; |
| regulator-max-microvolt = <850000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| bucka4: buck4 { |
| regulator-name = "vdd_ddr_1v1"; |
| regulator-min-microvolt = <1100000>; |
| regulator-max-microvolt = <1100000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| bucka5: buck5 { |
| regulator-name = "vdd_phyio_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldoa1: ldo1 { |
| regulator-name = "vdd1_lpddr4_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldoa2: ldo2 { |
| regulator-name = "vdd_mcuio_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldoa3: ldo3 { |
| regulator-name = "vdda_dll_0v8"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldoa4: ldo4 { |
| regulator-name = "vda_mcu_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| |
| tps659411: pmic@4c { |
| compatible = "ti,tps6594-q1"; |
| reg = <0x4c>; |
| system-power-controller; |
| interrupt-parent = <&wkup_gpio0>; |
| interrupts = <9 IRQ_TYPE_EDGE_FALLING>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| buck1234-supply = <&vsys_3v3>; |
| buck5-supply = <&vsys_3v3>; |
| ldo1-supply = <&vsys_3v3>; |
| ldo2-supply = <&vsys_3v3>; |
| ldo3-supply = <&vsys_3v3>; |
| ldo4-supply = <&vsys_3v3>; |
| |
| regulators { |
| buckb1234: buck1234 { |
| regulator-name = "vdd_core_0v8"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buckb5: buck5 { |
| regulator-name = "vdd_ram_0v85"; |
| regulator-min-microvolt = <850000>; |
| regulator-max-microvolt = <850000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldob1: ldo1 { |
| regulator-name = "vdd_sd_dv"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldob2: ldo2 { |
| regulator-name = "vdd_usb_3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldob3: ldo3 { |
| regulator-name = "vdd_io_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldob4: ldo4 { |
| regulator-name = "vda_pll_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &ospi0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; |
| |
| flash@0 { |
| compatible = "jedec,spi-nor"; |
| reg = <0x0>; |
| spi-tx-bus-width = <8>; |
| spi-rx-bus-width = <8>; |
| spi-max-frequency = <25000000>; |
| cdns,tshsl-ns = <60>; |
| cdns,tsd2d-ns = <60>; |
| cdns,tchsh-ns = <60>; |
| cdns,tslch-ns = <60>; |
| cdns,read-delay = <0>; |
| |
| partitions { |
| compatible = "fixed-partitions"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| partition@0 { |
| label = "ospi.tiboot3"; |
| reg = <0x0 0x80000>; |
| }; |
| |
| partition@80000 { |
| label = "ospi.tispl"; |
| reg = <0x80000 0x200000>; |
| }; |
| |
| partition@280000 { |
| label = "ospi.u-boot"; |
| reg = <0x280000 0x400000>; |
| }; |
| |
| partition@680000 { |
| label = "ospi.env"; |
| reg = <0x680000 0x20000>; |
| }; |
| |
| partition@6a0000 { |
| label = "ospi.env.backup"; |
| reg = <0x6a0000 0x20000>; |
| }; |
| |
| partition@6c0000 { |
| label = "ospi.sysfw"; |
| reg = <0x6c0000 0x100000>; |
| }; |
| |
| partition@800000 { |
| label = "ospi.rootfs"; |
| reg = <0x800000 0x37c0000>; |
| }; |
| |
| partition@3fe0000 { |
| label = "ospi.phypattern"; |
| reg = <0x3fe0000 0x20000>; |
| }; |
| }; |
| }; |
| }; |
| |
| &hbmc { |
| /* OSPI and HBMC are muxed inside FSS, Bootloader will enable |
| * appropriate node based on board detection |
| */ |
| status = "disabled"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; |
| ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ |
| <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ |
| |
| flash@0,0 { |
| compatible = "cypress,hyperflash", "cfi-flash"; |
| reg = <0x00 0x00 0x4000000>; |
| |
| partitions { |
| compatible = "fixed-partitions"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| partition@0 { |
| label = "hbmc.tiboot3"; |
| reg = <0x0 0x80000>; |
| }; |
| |
| partition@80000 { |
| label = "hbmc.tispl"; |
| reg = <0x80000 0x200000>; |
| }; |
| |
| partition@280000 { |
| label = "hbmc.u-boot"; |
| reg = <0x280000 0x400000>; |
| }; |
| |
| partition@680000 { |
| label = "hbmc.env"; |
| reg = <0x680000 0x40000>; |
| }; |
| |
| partition@6c0000 { |
| label = "hbmc.sysfw"; |
| reg = <0x6c0000 0x100000>; |
| }; |
| |
| partition@800000 { |
| label = "hbmc.rootfs"; |
| reg = <0x800000 0x3800000>; |
| }; |
| }; |
| }; |
| }; |
| |
| &mailbox0_cluster0 { |
| status = "okay"; |
| interrupts = <436>; |
| |
| mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster1 { |
| status = "okay"; |
| interrupts = <432>; |
| |
| mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster2 { |
| status = "okay"; |
| interrupts = <428>; |
| |
| mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster3 { |
| status = "okay"; |
| interrupts = <424>; |
| |
| mbox_c66_0: mbox-c66-0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_c66_1: mbox-c66-1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster4 { |
| status = "okay"; |
| interrupts = <420>; |
| |
| mbox_c71_0: mbox-c71-0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| }; |
| |
| &mcu_r5fss0_core0 { |
| mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; |
| memory-region = <&mcu_r5fss0_core0_dma_memory_region>, |
| <&mcu_r5fss0_core0_memory_region>; |
| }; |
| |
| &mcu_r5fss0_core1 { |
| mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; |
| memory-region = <&mcu_r5fss0_core1_dma_memory_region>, |
| <&mcu_r5fss0_core1_memory_region>; |
| }; |
| |
| &main_r5fss0_core0 { |
| mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; |
| memory-region = <&main_r5fss0_core0_dma_memory_region>, |
| <&main_r5fss0_core0_memory_region>; |
| }; |
| |
| &main_r5fss0_core1 { |
| mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; |
| memory-region = <&main_r5fss0_core1_dma_memory_region>, |
| <&main_r5fss0_core1_memory_region>; |
| }; |
| |
| &main_r5fss1_core0 { |
| mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; |
| memory-region = <&main_r5fss1_core0_dma_memory_region>, |
| <&main_r5fss1_core0_memory_region>; |
| }; |
| |
| &main_r5fss1_core1 { |
| mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; |
| memory-region = <&main_r5fss1_core1_dma_memory_region>, |
| <&main_r5fss1_core1_memory_region>; |
| }; |
| |
| &c66_0 { |
| status = "okay"; |
| mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; |
| memory-region = <&c66_0_dma_memory_region>, |
| <&c66_0_memory_region>; |
| }; |
| |
| &c66_1 { |
| status = "okay"; |
| mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; |
| memory-region = <&c66_1_dma_memory_region>, |
| <&c66_1_memory_region>; |
| }; |
| |
| &c71_0 { |
| status = "okay"; |
| mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; |
| memory-region = <&c71_0_dma_memory_region>, |
| <&c71_0_memory_region>; |
| }; |
