blob: a15aa256d0cfd799dd46178c9e19a45ff01b0df4 [file] [log] [blame]
// SPDX-License-Identifier: ISC
/* Copyright (C) 2020 MediaTek Inc. */
#include "mt7915.h"
#include "eeprom.h"
#include "mcu.h"
/** global debugfs **/
struct hw_queue_map {
const char *name;
u8 index;
u8 pid;
u8 qid;
};
static int
mt7915_implicit_txbf_set(void *data, u64 val)
{
struct mt7915_dev *dev = data;
if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state))
return -EBUSY;
dev->ibf = !!val;
return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
}
static int
mt7915_implicit_txbf_get(void *data, u64 *val)
{
struct mt7915_dev *dev = data;
*val = dev->ibf;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7915_implicit_txbf_get,
mt7915_implicit_txbf_set, "%lld\n");
/* test knob of system layer 1/2 error recovery */
static int mt7915_ser_trigger_set(void *data, u64 val)
{
enum {
SER_SET_RECOVER_L1 = 1,
SER_SET_RECOVER_L2,
SER_ENABLE = 2,
SER_RECOVER
};
struct mt7915_dev *dev = data;
int ret = 0;
switch (val) {
case SER_SET_RECOVER_L1:
case SER_SET_RECOVER_L2:
ret = mt7915_mcu_set_ser(dev, SER_ENABLE, BIT(val), 0);
if (ret)
return ret;
return mt7915_mcu_set_ser(dev, SER_RECOVER, val, 0);
default:
break;
}
return ret;
}
DEFINE_DEBUGFS_ATTRIBUTE(fops_ser_trigger, NULL,
mt7915_ser_trigger_set, "%lld\n");
static int
mt7915_radar_trigger(void *data, u64 val)
{
struct mt7915_dev *dev = data;
return mt7915_mcu_rdd_cmd(dev, RDD_RADAR_EMULATE, 1, 0, 0);
}
DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL,
mt7915_radar_trigger, "%lld\n");
static int
mt7915_fw_debug_wm_set(void *data, u64 val)
{
struct mt7915_dev *dev = data;
enum {
DEBUG_TXCMD = 62,
DEBUG_CMD_RPT_TX,
DEBUG_CMD_RPT_TRIG,
DEBUG_SPL,
DEBUG_RPT_RX,
} debug;
int ret;
dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, dev->fw_debug_wm);
if (ret)
return ret;
for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RX; debug++) {
ret = mt7915_mcu_fw_dbg_ctrl(dev, debug, !!dev->fw_debug_wm);
if (ret)
return ret;
}
/* WM CPU info record control */
mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
mt76_wr(dev, MT_DIC_CMD_REG_CMD, BIT(2) | BIT(13) | !dev->fw_debug_wm);
mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
return 0;
}
static int
mt7915_fw_debug_wm_get(void *data, u64 *val)
{
struct mt7915_dev *dev = data;
*val = dev->fw_debug_wm;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wm, mt7915_fw_debug_wm_get,
mt7915_fw_debug_wm_set, "%lld\n");
static int
mt7915_fw_debug_wa_set(void *data, u64 val)
{
struct mt7915_dev *dev = data;
int ret;
dev->fw_debug_wa = val ? MCU_FW_LOG_TO_HOST : 0;
ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw_debug_wa);
if (ret)
return ret;
return mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), MCU_WA_PARAM_PDMA_RX,
!!dev->fw_debug_wa, 0);
}
static int
mt7915_fw_debug_wa_get(void *data, u64 *val)
{
struct mt7915_dev *dev = data;
*val = dev->fw_debug_wa;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, mt7915_fw_debug_wa_get,
mt7915_fw_debug_wa_set, "%lld\n");
static int
mt7915_fw_util_wm_show(struct seq_file *file, void *data)
{
struct mt7915_dev *dev = file->private;
if (dev->fw_debug_wm) {
seq_printf(file, "Busy: %u%% Peak busy: %u%%\n",
mt76_rr(dev, MT_CPU_UTIL_BUSY_PCT),
mt76_rr(dev, MT_CPU_UTIL_PEAK_BUSY_PCT));
seq_printf(file, "Idle count: %u Peak idle count: %u\n",
mt76_rr(dev, MT_CPU_UTIL_IDLE_CNT),
mt76_rr(dev, MT_CPU_UTIL_PEAK_IDLE_CNT));
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mt7915_fw_util_wm);
static int
mt7915_fw_util_wa_show(struct seq_file *file, void *data)
{
struct mt7915_dev *dev = file->private;
if (dev->fw_debug_wa)
return mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY),
MCU_WA_PARAM_CPU_UTIL, 0, 0);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mt7915_fw_util_wa);
static void
mt7915_ampdu_stat_read_phy(struct mt7915_phy *phy,
struct seq_file *file)
{
struct mt7915_dev *dev = phy->dev;
bool ext_phy = phy != &dev->phy;
int bound[15], range[4], i, n;
/* Tx ampdu stat */
for (i = 0; i < ARRAY_SIZE(range); i++)
range[i] = mt76_rr(dev, MT_MIB_ARNG(ext_phy, i));
for (i = 0; i < ARRAY_SIZE(bound); i++)
bound[i] = MT_MIB_ARNCR_RANGE(range[i / 4], i % 4) + 1;
seq_printf(file, "\nPhy %d\n", ext_phy);
seq_printf(file, "Length: %8d | ", bound[0]);
for (i = 0; i < ARRAY_SIZE(bound) - 1; i++)
seq_printf(file, "%3d -%3d | ",
bound[i] + 1, bound[i + 1]);
seq_puts(file, "\nCount: ");
n = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
for (i = 0; i < ARRAY_SIZE(bound); i++)
seq_printf(file, "%8d | ", dev->mt76.aggr_stats[i + n]);
seq_puts(file, "\n");
seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt);
}
static void
mt7915_txbf_stat_read_phy(struct mt7915_phy *phy, struct seq_file *s)
{
static const char * const bw[] = {
"BW20", "BW40", "BW80", "BW160"
};
struct mib_stats *mib = &phy->mib;
/* Tx Beamformer monitor */
seq_puts(s, "\nTx Beamformer applied PPDU counts: ");
seq_printf(s, "iBF: %d, eBF: %d\n",
mib->tx_bf_ibf_ppdu_cnt,
mib->tx_bf_ebf_ppdu_cnt);
/* Tx Beamformer Rx feedback monitor */
seq_puts(s, "Tx Beamformer Rx feedback statistics: ");
seq_printf(s, "All: %d, HE: %d, VHT: %d, HT: %d, ",
mib->tx_bf_rx_fb_all_cnt,
mib->tx_bf_rx_fb_he_cnt,
mib->tx_bf_rx_fb_vht_cnt,
mib->tx_bf_rx_fb_ht_cnt);
seq_printf(s, "%s, NC: %d, NR: %d\n",
bw[mib->tx_bf_rx_fb_bw],
mib->tx_bf_rx_fb_nc_cnt,
mib->tx_bf_rx_fb_nr_cnt);
/* Tx Beamformee Rx NDPA & Tx feedback report */
seq_printf(s, "Tx Beamformee successful feedback frames: %d\n",
mib->tx_bf_fb_cpl_cnt);
seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n",
mib->tx_bf_fb_trig_cnt);
/* Tx SU & MU counters */
seq_printf(s, "Tx multi-user Beamforming counts: %d\n",
mib->tx_bf_cnt);
seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt);
seq_printf(s, "Tx multi-user successful MPDU counts: %d\n",
mib->tx_mu_acked_mpdu_cnt);
seq_printf(s, "Tx single-user successful MPDU counts: %d\n",
mib->tx_su_acked_mpdu_cnt);
seq_puts(s, "\n");
}
static int
mt7915_tx_stats_show(struct seq_file *file, void *data)
{
struct mt7915_phy *phy = file->private;
struct mt7915_dev *dev = phy->dev;
struct mib_stats *mib = &phy->mib;
int i;
mutex_lock(&dev->mt76.mutex);
mt7915_ampdu_stat_read_phy(phy, file);
mt7915_mac_update_stats(phy);
mt7915_txbf_stat_read_phy(phy, file);
/* Tx amsdu info */
seq_puts(file, "Tx MSDU statistics:\n");
for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) {
seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ",
i + 1, mib->tx_amsdu[i]);
if (mib->tx_amsdu_cnt)
seq_printf(file, "(%3d%%)\n",
mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt);
else
seq_puts(file, "\n");
}
mutex_unlock(&dev->mt76.mutex);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mt7915_tx_stats);
static void
mt7915_hw_queue_read(struct seq_file *s, u32 base, u32 size,
const struct hw_queue_map *map)
{
struct mt7915_phy *phy = s->private;
struct mt7915_dev *dev = phy->dev;
u32 i, val;
val = mt76_rr(dev, base + MT_FL_Q_EMPTY);
for (i = 0; i < size; i++) {
u32 ctrl, head, tail, queued;
if (val & BIT(map[i].index))
continue;
ctrl = BIT(31) | (map[i].pid << 10) | (map[i].qid << 24);
mt76_wr(dev, base + MT_FL_Q0_CTRL, ctrl);
head = mt76_get_field(dev, base + MT_FL_Q2_CTRL,
GENMASK(11, 0));
tail = mt76_get_field(dev, base + MT_FL_Q2_CTRL,
GENMASK(27, 16));
queued = mt76_get_field(dev, base + MT_FL_Q3_CTRL,
GENMASK(11, 0));
seq_printf(s, "\t%s: ", map[i].name);
seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n",
queued, head, tail);
}
}
static void
mt7915_sta_hw_queue_read(void *data, struct ieee80211_sta *sta)
{
struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
struct mt7915_dev *dev = msta->vif->phy->dev;
struct seq_file *s = data;
u8 ac;
for (ac = 0; ac < 4; ac++) {
u32 qlen, ctrl, val;
u32 idx = msta->wcid.idx >> 5;
u8 offs = msta->wcid.idx & GENMASK(4, 0);
ctrl = BIT(31) | BIT(11) | (ac << 24);
val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx));
if (val & BIT(offs))
continue;
mt76_wr(dev, MT_PLE_BASE + MT_FL_Q0_CTRL, ctrl | msta->wcid.idx);
qlen = mt76_get_field(dev, MT_PLE_BASE + MT_FL_Q3_CTRL,
GENMASK(11, 0));
seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n",
sta->addr, msta->wcid.idx, msta->vif->wmm_idx,
ac, qlen);
}
}
static int
mt7915_hw_queues_show(struct seq_file *file, void *data)
{
struct mt7915_phy *phy = file->private;
struct mt7915_dev *dev = phy->dev;
static const struct hw_queue_map ple_queue_map[] = {
{ "CPU_Q0", 0, 1, MT_CTX0 },
{ "CPU_Q1", 1, 1, MT_CTX0 + 1 },
{ "CPU_Q2", 2, 1, MT_CTX0 + 2 },
{ "CPU_Q3", 3, 1, MT_CTX0 + 3 },
{ "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 },
{ "BMC_Q0", 9, 2, MT_LMAC_BMC0 },
{ "BCN_Q0", 10, 2, MT_LMAC_BCN0 },
{ "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 },
{ "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 },
{ "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 },
{ "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 },
{ "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 },
};
static const struct hw_queue_map pse_queue_map[] = {
{ "CPU Q0", 0, 1, MT_CTX0 },
{ "CPU Q1", 1, 1, MT_CTX0 + 1 },
{ "CPU Q2", 2, 1, MT_CTX0 + 2 },
{ "CPU Q3", 3, 1, MT_CTX0 + 3 },
{ "HIF_Q0", 8, 0, MT_HIF0 },
{ "HIF_Q1", 9, 0, MT_HIF0 + 1 },
{ "HIF_Q2", 10, 0, MT_HIF0 + 2 },
{ "HIF_Q3", 11, 0, MT_HIF0 + 3 },
{ "HIF_Q4", 12, 0, MT_HIF0 + 4 },
{ "HIF_Q5", 13, 0, MT_HIF0 + 5 },
{ "LMAC_Q", 16, 2, 0 },
{ "MDP_TXQ", 17, 2, 1 },
{ "MDP_RXQ", 18, 2, 2 },
{ "SEC_TXQ", 19, 2, 3 },
{ "SEC_RXQ", 20, 2, 4 },
};
u32 val, head, tail;
/* ple queue */
val = mt76_rr(dev, MT_PLE_FREEPG_CNT);
head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0));
tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16));
seq_puts(file, "PLE page info:\n");
seq_printf(file,
"\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n",
val, head, tail);
val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP);
head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0));
tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16));
seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n",
val, head, tail);
seq_puts(file, "PLE non-empty queue info:\n");
mt7915_hw_queue_read(file, MT_PLE_BASE, ARRAY_SIZE(ple_queue_map),
&ple_queue_map[0]);
/* iterate per-sta ple queue */
ieee80211_iterate_stations_atomic(phy->mt76->hw,
mt7915_sta_hw_queue_read, file);
/* pse queue */
seq_puts(file, "PSE non-empty queue info:\n");
mt7915_hw_queue_read(file, MT_PSE_BASE, ARRAY_SIZE(pse_queue_map),
&pse_queue_map[0]);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mt7915_hw_queues);
static int
mt7915_xmit_queues_show(struct seq_file *file, void *data)
{
struct mt7915_phy *phy = file->private;
struct mt7915_dev *dev = phy->dev;
struct {
struct mt76_queue *q;
char *queue;
} queue_map[] = {
{ phy->mt76->q_tx[MT_TXQ_BE], " MAIN" },
{ dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" },
{ dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" },
{ dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" },
};
int i;
seq_puts(file, " queue | hw-queued | head | tail |\n");
for (i = 0; i < ARRAY_SIZE(queue_map); i++) {
struct mt76_queue *q = queue_map[i].q;
if (!q)
continue;
seq_printf(file, " %s | %9d | %9d | %9d |\n",
queue_map[i].queue, q->queued, q->head,
q->tail);
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mt7915_xmit_queues);
static int
mt7915_rate_txpower_show(struct seq_file *file, void *data)
{
static const char * const sku_group_name[] = {
"CCK", "OFDM", "HT20", "HT40",
"VHT20", "VHT40", "VHT80", "VHT160",
"RU26", "RU52", "RU106", "RU242/SU20",
"RU484/SU40", "RU996/SU80", "RU2x996/SU160"
};
struct mt7915_phy *phy = file->private;
s8 txpower[MT7915_SKU_RATE_NUM], *buf;
int i;
seq_printf(file, "\nBand %d\n", phy != &phy->dev->phy);
mt7915_mcu_get_txpower_sku(phy, txpower, sizeof(txpower));
for (i = 0, buf = txpower; i < ARRAY_SIZE(mt7915_sku_group_len); i++) {
u8 mcs_num = mt7915_sku_group_len[i];
if (i >= SKU_VHT_BW20 && i <= SKU_VHT_BW160)
mcs_num = 10;
mt76_seq_puts_array(file, sku_group_name[i], buf, mcs_num);
buf += mt7915_sku_group_len[i];
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mt7915_rate_txpower);
static int
mt7915_twt_stats(struct seq_file *s, void *data)
{
struct mt7915_dev *dev = dev_get_drvdata(s->private);
struct mt7915_twt_flow *iter;
rcu_read_lock();
seq_puts(s, " wcid | id | flags | exp | mantissa");
seq_puts(s, " | duration | tsf |\n");
list_for_each_entry_rcu(iter, &dev->twt_list, list)
seq_printf(s,
"%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n",
iter->wcid, iter->id,
iter->sched ? 's' : 'u',
iter->protection ? 'p' : '-',
iter->trigger ? 't' : '-',
iter->flowtype ? '-' : 'a',
iter->exp, iter->mantissa,
iter->duration, iter->tsf);
rcu_read_unlock();
return 0;
}
int mt7915_init_debugfs(struct mt7915_phy *phy)
{
struct mt7915_dev *dev = phy->dev;
bool ext_phy = phy != &dev->phy;
struct dentry *dir;
dir = mt76_register_debugfs_fops(phy->mt76, NULL);
if (!dir)
return -ENOMEM;
debugfs_create_file("hw-queues", 0400, dir, phy,
&mt7915_hw_queues_fops);
debugfs_create_file("xmit-queues", 0400, dir, phy,
&mt7915_xmit_queues_fops);
debugfs_create_file("tx_stats", 0400, dir, phy, &mt7915_tx_stats_fops);
debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm);
debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa);
debugfs_create_file("fw_util_wm", 0400, dir, dev,
&mt7915_fw_util_wm_fops);
debugfs_create_file("fw_util_wa", 0400, dir, dev,
&mt7915_fw_util_wa_fops);
debugfs_create_file("implicit_txbf", 0600, dir, dev,
&fops_implicit_txbf);
debugfs_create_file("txpower_sku", 0400, dir, phy,
&mt7915_rate_txpower_fops);
debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir,
mt7915_twt_stats);
debugfs_create_file("ser_trigger", 0200, dir, dev, &fops_ser_trigger);
if (!dev->dbdc_support || ext_phy) {
debugfs_create_u32("dfs_hw_pattern", 0400, dir,
&dev->hw_pattern);
debugfs_create_file("radar_trigger", 0200, dir, dev,
&fops_radar_trigger);
}
return 0;
}
#ifdef CONFIG_MAC80211_DEBUGFS
/** per-station debugfs **/
static ssize_t mt7915_sta_fixed_rate_set(struct file *file,
const char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ieee80211_sta *sta = file->private_data;
struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
struct mt7915_dev *dev = msta->vif->phy->dev;
struct ieee80211_vif *vif;
struct sta_phy phy = {};
char buf[100];
int ret;
u32 field;
u8 i, gi, he_ltf;
if (count >= sizeof(buf))
return -EINVAL;
if (copy_from_user(buf, user_buf, count))
return -EFAULT;
if (count && buf[count - 1] == '\n')
buf[count - 1] = '\0';
else
buf[count] = '\0';
/* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9
* bw - bw20: 0, bw40: 1, bw80: 2, bw160: 3
* nss - vht: 1~4, he: 1~4, others: ignore
* mcs - cck: 0~4, ofdm: 0~7, ht: 0~32, vht: 0~9, he_su: 0~11, he_er: 0~2
* gi - (ht/vht) lgi: 0, sgi: 1; (he) 0.8us: 0, 1.6us: 1, 3.2us: 2
* ldpc - off: 0, on: 1
* stbc - off: 0, on: 1
* he_ltf - 1xltf: 0, 2xltf: 1, 4xltf: 2
*/
if (sscanf(buf, "%hhu %hhu %hhu %hhu %hhu %hhu %hhu %hhu",
&phy.type, &phy.bw, &phy.nss, &phy.mcs, &gi,
&phy.ldpc, &phy.stbc, &he_ltf) != 8) {
dev_warn(dev->mt76.dev,
"format: Mode BW NSS MCS (HE)GI LDPC STBC HE_LTF\n");
field = RATE_PARAM_AUTO;
goto out;
}
phy.ldpc = (phy.bw || phy.ldpc) * GENMASK(2, 0);
for (i = 0; i <= phy.bw; i++) {
phy.sgi |= gi << (i << sta->he_cap.has_he);
phy.he_ltf |= he_ltf << (i << sta->he_cap.has_he);
}
field = RATE_PARAM_FIXED;
out:
vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
ret = mt7915_mcu_set_fixed_rate_ctrl(dev, vif, sta, &phy, field);
if (ret)
return -EFAULT;
return count;
}
static const struct file_operations fops_fixed_rate = {
.write = mt7915_sta_fixed_rate_set,
.open = simple_open,
.owner = THIS_MODULE,
.llseek = default_llseek,
};
static int
mt7915_queues_show(struct seq_file *s, void *data)
{
struct ieee80211_sta *sta = s->private;
mt7915_sta_hw_queue_read(s, sta);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mt7915_queues);
void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, struct dentry *dir)
{
debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate);
debugfs_create_file("hw-queues", 0400, dir, sta, &mt7915_queues_fops);
}
#endif