| /* SPDX-License-Identifier: GPL-2.0-only */ |
| /* |
| * Copyright 2008 Cisco Systems, Inc. All rights reserved. |
| * Copyright 2007 Nuova Systems, Inc. All rights reserved. |
| */ |
| #ifndef _CQ_DESC_H_ |
| #define _CQ_DESC_H_ |
| |
| /* |
| * Completion queue descriptor types |
| */ |
| enum cq_desc_types { |
| CQ_DESC_TYPE_WQ_ENET = 0, |
| CQ_DESC_TYPE_DESC_COPY = 1, |
| CQ_DESC_TYPE_WQ_EXCH = 2, |
| CQ_DESC_TYPE_RQ_ENET = 3, |
| CQ_DESC_TYPE_RQ_FCP = 4, |
| }; |
| |
| /* Completion queue descriptor: 16B |
| * |
| * All completion queues have this basic layout. The |
| * type_specfic area is unique for each completion |
| * queue type. |
| */ |
| struct cq_desc { |
| __le16 completed_index; |
| __le16 q_number; |
| u8 type_specfic[11]; |
| u8 type_color; |
| }; |
| |
| #define CQ_DESC_TYPE_BITS 4 |
| #define CQ_DESC_TYPE_MASK ((1 << CQ_DESC_TYPE_BITS) - 1) |
| #define CQ_DESC_COLOR_MASK 1 |
| #define CQ_DESC_COLOR_SHIFT 7 |
| #define CQ_DESC_Q_NUM_BITS 10 |
| #define CQ_DESC_Q_NUM_MASK ((1 << CQ_DESC_Q_NUM_BITS) - 1) |
| #define CQ_DESC_COMP_NDX_BITS 12 |
| #define CQ_DESC_COMP_NDX_MASK ((1 << CQ_DESC_COMP_NDX_BITS) - 1) |
| |
| static inline void cq_desc_dec(const struct cq_desc *desc_arg, |
| u8 *type, u8 *color, u16 *q_number, u16 *completed_index) |
| { |
| const struct cq_desc *desc = desc_arg; |
| const u8 type_color = desc->type_color; |
| |
| *color = (type_color >> CQ_DESC_COLOR_SHIFT) & CQ_DESC_COLOR_MASK; |
| |
| /* |
| * Make sure color bit is read from desc *before* other fields |
| * are read from desc. Hardware guarantees color bit is last |
| * bit (byte) written. Adding the rmb() prevents the compiler |
| * and/or CPU from reordering the reads which would potentially |
| * result in reading stale values. |
| */ |
| |
| rmb(); |
| |
| *type = type_color & CQ_DESC_TYPE_MASK; |
| *q_number = le16_to_cpu(desc->q_number) & CQ_DESC_Q_NUM_MASK; |
| *completed_index = le16_to_cpu(desc->completed_index) & |
| CQ_DESC_COMP_NDX_MASK; |
| } |
| |
| #endif /* _CQ_DESC_H_ */ |