if (BF54x) | |
source "arch/blackfin/mach-bf548/boards/Kconfig" | |
menu "BF548 Specific Configuration" | |
config DEB_DMA_URGENT | |
bool "DMA has priority over core for ext. accesses" | |
depends on BF54x | |
default y | |
help | |
Treat any DEB1, DEB2 and DEB3 request as Urgent | |
comment "Interrupt Priority Assignment" | |
menu "Priority" | |
config IRQ_PLL_WAKEUP | |
int "IRQ_PLL_WAKEUP" | |
default 7 | |
config IRQ_DMAC0_ERR | |
int "IRQ_DMAC0_ERR" | |
default 7 | |
config IRQ_EPPI0_ERR | |
int "IRQ_EPPI0_ERR" | |
default 7 | |
config IRQ_SPORT0_ERR | |
int "IRQ_SPORT0_ERR" | |
default 7 | |
config IRQ_SPORT1_ERR | |
int "IRQ_SPORT1_ERR" | |
default 7 | |
config IRQ_SPI0_ERR | |
int "IRQ_SPI0_ERR" | |
default 7 | |
config IRQ_UART0_ERR | |
int "IRQ_UART0_ERR" | |
default 7 | |
config IRQ_RTC | |
int "IRQ_RTC" | |
default 8 | |
config IRQ_EPPI0 | |
int "IRQ_EPPI0" | |
default 8 | |
config IRQ_SPORT0_RX | |
int "IRQ_SPORT0_RX" | |
default 9 | |
config IRQ_SPORT0_TX | |
int "IRQ_SPORT0_TX" | |
default 9 | |
config IRQ_SPORT1_RX | |
int "IRQ_SPORT1_RX" | |
default 9 | |
config IRQ_SPORT1_TX | |
int "IRQ_SPORT1_TX" | |
default 9 | |
config IRQ_SPI0 | |
int "IRQ_SPI0" | |
default 10 | |
config IRQ_UART0_RX | |
int "IRQ_UART0_RX" | |
default 10 | |
config IRQ_UART0_TX | |
int "IRQ_UART0_TX" | |
default 10 | |
config IRQ_TIMER8 | |
int "IRQ_TIMER8" | |
default 11 | |
config IRQ_TIMER9 | |
int "IRQ_TIMER9" | |
default 11 | |
config IRQ_TIMER10 | |
int "IRQ_TIMER10" | |
default 11 | |
config IRQ_PINT0 | |
int "IRQ_PINT0" | |
default 12 | |
config IRQ_PINT1 | |
int "IRQ_PINT0" | |
default 12 | |
config IRQ_MDMAS0 | |
int "IRQ_MDMAS0" | |
default 13 | |
config IRQ_MDMAS1 | |
int "IRQ_DMDMAS1" | |
default 13 | |
config IRQ_WATCHDOG | |
int "IRQ_WATCHDOG" | |
default 13 | |
config IRQ_DMAC1_ERR | |
int "IRQ_DMAC1_ERR" | |
default 7 | |
config IRQ_SPORT2_ERR | |
int "IRQ_SPORT2_ERR" | |
default 7 | |
config IRQ_SPORT3_ERR | |
int "IRQ_SPORT3_ERR" | |
default 7 | |
config IRQ_MXVR_DATA | |
int "IRQ MXVR Data" | |
default 7 | |
config IRQ_SPI1_ERR | |
int "IRQ_SPI1_ERR" | |
default 7 | |
config IRQ_SPI2_ERR | |
int "IRQ_SPI2_ERR" | |
default 7 | |
config IRQ_UART1_ERR | |
int "IRQ_UART1_ERR" | |
default 7 | |
config IRQ_UART2_ERR | |
int "IRQ_UART2_ERR" | |
default 7 | |
config IRQ_CAN0_ERR | |
int "IRQ_CAN0_ERR" | |
default 7 | |
config IRQ_SPORT2_RX | |
int "IRQ_SPORT2_RX" | |
default 9 | |
config IRQ_SPORT2_TX | |
int "IRQ_SPORT2_TX" | |
default 9 | |
config IRQ_SPORT3_RX | |
int "IRQ_SPORT3_RX" | |
default 9 | |
config IRQ_SPORT3_TX | |
int "IRQ_SPORT3_TX" | |
default 9 | |
config IRQ_EPPI1 | |
int "IRQ_EPPI1" | |
default 9 | |
config IRQ_EPPI2 | |
int "IRQ_EPPI2" | |
default 9 | |
config IRQ_SPI1 | |
int "IRQ_SPI1" | |
default 10 | |
config IRQ_SPI2 | |
int "IRQ_SPI2" | |
default 10 | |
config IRQ_UART1_RX | |
int "IRQ_UART1_RX" | |
default 10 | |
config IRQ_UART1_TX | |
int "IRQ_UART1_TX" | |
default 10 | |
config IRQ_ATAPI_RX | |
int "IRQ_ATAPI_RX" | |
default 10 | |
config IRQ_ATAPI_TX | |
int "IRQ_ATAPI_TX" | |
default 10 | |
config IRQ_TWI0 | |
int "IRQ_TWI0" | |
default 11 | |
config IRQ_TWI1 | |
int "IRQ_TWI1" | |
default 11 | |
config IRQ_CAN0_RX | |
int "IRQ_CAN_RX" | |
default 11 | |
config IRQ_CAN0_TX | |
int "IRQ_CAN_TX" | |
default 11 | |
config IRQ_MDMAS2 | |
int "IRQ_MDMAS2" | |
default 13 | |
config IRQ_MDMAS3 | |
int "IRQ_DMMAS3" | |
default 13 | |
config IRQ_MXVR_ERR | |
int "IRQ_MXVR_ERR" | |
default 11 | |
config IRQ_MXVR_MSG | |
int "IRQ_MXVR_MSG" | |
default 11 | |
config IRQ_MXVR_PKT | |
int "IRQ_MXVR_PKT" | |
default 11 | |
config IRQ_EPPI1_ERR | |
int "IRQ_EPPI1_ERR" | |
default 7 | |
config IRQ_EPPI2_ERR | |
int "IRQ_EPPI2_ERR" | |
default 7 | |
config IRQ_UART3_ERR | |
int "IRQ_UART3_ERR" | |
default 7 | |
config IRQ_HOST_ERR | |
int "IRQ_HOST_ERR" | |
default 7 | |
config IRQ_PIXC_ERR | |
int "IRQ_PIXC_ERR" | |
default 7 | |
config IRQ_NFC_ERR | |
int "IRQ_NFC_ERR" | |
default 7 | |
config IRQ_ATAPI_ERR | |
int "IRQ_ATAPI_ERR" | |
default 7 | |
config IRQ_CAN1_ERR | |
int "IRQ_CAN1_ERR" | |
default 7 | |
config IRQ_HS_DMA_ERR | |
int "IRQ Handshake DMA Status" | |
default 7 | |
config IRQ_PIXC_IN0 | |
int "IRQ PIXC IN0" | |
default 8 | |
config IRQ_PIXC_IN1 | |
int "IRQ PIXC IN1" | |
default 8 | |
config IRQ_PIXC_OUT | |
int "IRQ PIXC OUT" | |
default 8 | |
config IRQ_SDH | |
int "IRQ SDH" | |
default 8 | |
config IRQ_CNT | |
int "IRQ CNT" | |
default 8 | |
config IRQ_KEY | |
int "IRQ KEY" | |
default 8 | |
config IRQ_CAN1_RX | |
int "IRQ CAN1 RX" | |
default 11 | |
config IRQ_CAN1_TX | |
int "IRQ_CAN1_TX" | |
default 11 | |
config IRQ_SDH_MASK0 | |
int "IRQ_SDH_MASK0" | |
default 11 | |
config IRQ_SDH_MASK1 | |
int "IRQ_SDH_MASK1" | |
default 11 | |
config IRQ_USB_INT0 | |
int "IRQ USB INT0" | |
default 11 | |
config IRQ_USB_INT1 | |
int "IRQ USB INT1" | |
default 11 | |
config IRQ_USB_INT2 | |
int "IRQ USB INT2" | |
default 11 | |
config IRQ_USB_DMA | |
int "IRQ USB DMA" | |
default 11 | |
config IRQ_OTPSEC | |
int "IRQ OPTSEC" | |
default 11 | |
config IRQ_TIMER0 | |
int "IRQ_TIMER0" | |
default 11 | |
config IRQ_TIMER1 | |
int "IRQ_TIMER1" | |
default 11 | |
config IRQ_TIMER2 | |
int "IRQ_TIMER2" | |
default 11 | |
config IRQ_TIMER3 | |
int "IRQ_TIMER3" | |
default 11 | |
config IRQ_TIMER4 | |
int "IRQ_TIMER4" | |
default 11 | |
config IRQ_TIMER5 | |
int "IRQ_TIMER5" | |
default 11 | |
config IRQ_TIMER6 | |
int "IRQ_TIMER6" | |
default 11 | |
config IRQ_TIMER7 | |
int "IRQ_TIMER7" | |
default 11 | |
config IRQ_PINT2 | |
int "IRQ_PIN2" | |
default 11 | |
config IRQ_PINT3 | |
int "IRQ_PIN3" | |
default 11 | |
help | |
Enter the priority numbers between 7-13 ONLY. Others are Reserved. | |
This applies to all the above. It is not recommended to assign the | |
highest priority number 7 to UART or any other device. | |
endmenu | |
comment "Pin Interrupt to Port Assignment" | |
menu "Assignment" | |
config PINTx_REASSIGN | |
bool "Reprogram PINT Assignment" | |
default y | |
help | |
The interrupt assignment registers controls the pin-to-interrupt | |
assignment in a byte-wide manner. Each option allows you to select | |
a set of pins (High/Low Byte) of an specific Port being mapped | |
to one of the four PIN Interrupts IRQ_PINTx. | |
You shouldn't change any of these unless you know exactly what you're doing. | |
Please consult the Blackfin BF54x Processor Hardware Reference Manual. | |
config PINT0_ASSIGN | |
hex "PINT0_ASSIGN" | |
depends on PINTx_REASSIGN | |
default 0x00000101 | |
config PINT1_ASSIGN | |
hex "PINT1_ASSIGN" | |
depends on PINTx_REASSIGN | |
default 0x01010000 | |
config PINT2_ASSIGN | |
hex "PINT2_ASSIGN" | |
depends on PINTx_REASSIGN | |
default 0x07000101 | |
config PINT3_ASSIGN | |
hex "PINT3_ASSIGN" | |
depends on PINTx_REASSIGN | |
default 0x02020303 | |
endmenu | |
endmenu | |
endif |