| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Device Tree Include file for NXP Layerscape-1028A family SoC. |
| * |
| * Copyright 2018-2020 NXP |
| * |
| * Harninder Rai <harninder.rai@nxp.com> |
| * |
| */ |
| |
| #include <dt-bindings/clock/fsl,qoriq-clockgen.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| compatible = "fsl,ls1028a"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a72"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| clocks = <&clockgen QORIQ_CLK_CMUX 0>; |
| i-cache-size = <0xc000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2>; |
| cpu-idle-states = <&CPU_PW20>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a72"; |
| reg = <0x1>; |
| enable-method = "psci"; |
| clocks = <&clockgen QORIQ_CLK_CMUX 0>; |
| i-cache-size = <0xc000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2>; |
| cpu-idle-states = <&CPU_PW20>; |
| #cooling-cells = <2>; |
| }; |
| |
| l2: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| cache-size = <0x100000>; |
| cache-line-size = <64>; |
| cache-sets = <1024>; |
| }; |
| }; |
| |
| idle-states { |
| /* |
| * PSCI node is not added default, U-boot will add missing |
| * parts if it determines to use PSCI. |
| */ |
| entry-method = "psci"; |
| |
| CPU_PW20: cpu-pw20 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "PW20"; |
| arm,psci-suspend-param = <0x0>; |
| entry-latency-us = <2000>; |
| exit-latency-us = <2000>; |
| min-residency-us = <6000>; |
| }; |
| }; |
| |
| rtc_clk: rtc-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| clock-output-names = "rtc_clk"; |
| }; |
| |
| sysclk: sysclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <100000000>; |
| clock-output-names = "sysclk"; |
| }; |
| |
| osc_27m: clock-osc-27m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <27000000>; |
| clock-output-names = "phy_27m"; |
| }; |
| |
| firmware { |
| optee: optee { |
| compatible = "linaro,optee-tz"; |
| method = "smc"; |
| status = "disabled"; |
| }; |
| }; |
| |
| reboot { |
| compatible = "syscon-reboot"; |
| regmap = <&rst>; |
| offset = <0>; |
| mask = <0x02>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a72-pmu"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| gic: interrupt-controller@6000000 { |
| compatible = "arm,gic-v3"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ |
| <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | |
| IRQ_TYPE_LEVEL_LOW)>; |
| its: msi-controller@6020000 { |
| compatible = "arm,gic-v3-its"; |
| msi-controller; |
| reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ |
| }; |
| }; |
| |
| thermal-zones { |
| ddr-controller { |
| polling-delay-passive = <1000>; |
| polling-delay = <5000>; |
| thermal-sensors = <&tmu 0>; |
| |
| trips { |
| ddr-ctrler-alert { |
| temperature = <85000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| ddr-ctrler-crit { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| core-cluster { |
| polling-delay-passive = <1000>; |
| polling-delay = <5000>; |
| thermal-sensors = <&tmu 1>; |
| |
| trips { |
| core_cluster_alert: core-cluster-alert { |
| temperature = <85000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| core_cluster_crit: core-cluster-crit { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&core_cluster_alert>; |
| cooling-device = |
| <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| }; |
| |
| soc: soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| ddr: memory-controller@1080000 { |
| compatible = "fsl,qoriq-memory-controller"; |
| reg = <0x0 0x1080000 0x0 0x1000>; |
| interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| little-endian; |
| }; |
| |
| dcfg: syscon@1e00000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; |
| reg = <0x0 0x1e00000 0x0 0x10000>; |
| ranges = <0x0 0x0 0x1e00000 0x10000>; |
| little-endian; |
| |
| fspi_clk: clock-controller@900 { |
| compatible = "fsl,ls1028a-flexspi-clk"; |
| reg = <0x900 0x4>; |
| #clock-cells = <0>; |
| clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; |
| clock-output-names = "fspi_clk"; |
| }; |
| }; |
| |
| rst: syscon@1e60000 { |
| compatible = "syscon"; |
| reg = <0x0 0x1e60000 0x0 0x10000>; |
| little-endian; |
| }; |
| |
| sfp: efuse@1e80000 { |
| compatible = "fsl,ls1028a-sfp"; |
| reg = <0x0 0x1e80000 0x0 0x10000>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| clock-names = "sfp"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| ls1028a_uid: unique-id@1c { |
| reg = <0x1c 0x8>; |
| }; |
| }; |
| |
| scfg: syscon@1fc0000 { |
| compatible = "fsl,ls1028a-scfg", "syscon"; |
| reg = <0x0 0x1fc0000 0x0 0x10000>; |
| big-endian; |
| }; |
| |
| clockgen: clock-controller@1300000 { |
| compatible = "fsl,ls1028a-clockgen"; |
| reg = <0x0 0x1300000 0x0 0xa0000>; |
| #clock-cells = <2>; |
| clocks = <&sysclk>; |
| }; |
| |
| i2c0: i2c@2000000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2000000 0x0 0x10000>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@2010000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2010000 0x0 0x10000>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@2020000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2020000 0x0 0x10000>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@2030000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2030000 0x0 0x10000>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@2040000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2040000 0x0 0x10000>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@2050000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2050000 0x0 0x10000>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@2060000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2060000 0x0 0x10000>; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| status = "disabled"; |
| }; |
| |
| i2c7: i2c@2070000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2070000 0x0 0x10000>; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| status = "disabled"; |
| }; |
| |
| fspi: spi@20c0000 { |
| compatible = "nxp,lx2160a-fspi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x20c0000 0x0 0x10000>, |
| <0x0 0x20000000 0x0 0x10000000>; |
| reg-names = "fspi_base", "fspi_mmap"; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&fspi_clk>, <&fspi_clk>; |
| clock-names = "fspi_en", "fspi"; |
| status = "disabled"; |
| }; |
| |
| dspi0: spi@2100000 { |
| compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2100000 0x0 0x10000>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "dspi"; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| dmas = <&edma0 0 62>, <&edma0 0 60>; |
| dma-names = "tx", "rx"; |
| spi-num-chipselects = <4>; |
| little-endian; |
| status = "disabled"; |
| }; |
| |
| dspi1: spi@2110000 { |
| compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2110000 0x0 0x10000>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "dspi"; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| dmas = <&edma0 0 58>, <&edma0 0 56>; |
| dma-names = "tx", "rx"; |
| spi-num-chipselects = <4>; |
| little-endian; |
| status = "disabled"; |
| }; |
| |
| dspi2: spi@2120000 { |
| compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2120000 0x0 0x10000>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "dspi"; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| dmas = <&edma0 0 54>, <&edma0 0 2>; |
| dma-names = "tx", "rx"; |
| spi-num-chipselects = <3>; |
| little-endian; |
| status = "disabled"; |
| }; |
| |
| esdhc: mmc@2140000 { |
| compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; |
| reg = <0x0 0x2140000 0x0 0x10000>; |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <0>; /* fixed up by bootloader */ |
| clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; |
| voltage-ranges = <1800 1800 3300 3300>; |
| sdhci,auto-cmd12; |
| little-endian; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| esdhc1: mmc@2150000 { |
| compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; |
| reg = <0x0 0x2150000 0x0 0x10000>; |
| interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <0>; /* fixed up by bootloader */ |
| clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; |
| voltage-ranges = <1800 1800>; |
| sdhci,auto-cmd12; |
| non-removable; |
| little-endian; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| can0: can@2180000 { |
| compatible = "fsl,lx2160ar1-flexcan"; |
| reg = <0x0 0x2180000 0x0 0x10000>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| can1: can@2190000 { |
| compatible = "fsl,lx2160ar1-flexcan"; |
| reg = <0x0 0x2190000 0x0 0x10000>; |
| interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| duart0: serial@21c0500 { |
| compatible = "fsl,ns16550", "ns16550a"; |
| reg = <0x00 0x21c0500 0x0 0x100>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| status = "disabled"; |
| }; |
| |
| duart1: serial@21c0600 { |
| compatible = "fsl,ns16550", "ns16550a"; |
| reg = <0x00 0x21c0600 0x0 0x100>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| status = "disabled"; |
| }; |
| |
| |
| lpuart0: serial@2260000 { |
| compatible = "fsl,ls1028a-lpuart"; |
| reg = <0x0 0x2260000 0x0 0x1000>; |
| interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "ipg"; |
| dma-names = "rx","tx"; |
| dmas = <&edma0 1 32>, |
| <&edma0 1 33>; |
| status = "disabled"; |
| }; |
| |
| lpuart1: serial@2270000 { |
| compatible = "fsl,ls1028a-lpuart"; |
| reg = <0x0 0x2270000 0x0 0x1000>; |
| interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "ipg"; |
| dma-names = "rx","tx"; |
| dmas = <&edma0 1 30>, |
| <&edma0 1 31>; |
| status = "disabled"; |
| }; |
| |
| lpuart2: serial@2280000 { |
| compatible = "fsl,ls1028a-lpuart"; |
| reg = <0x0 0x2280000 0x0 0x1000>; |
| interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "ipg"; |
| dma-names = "rx","tx"; |
| dmas = <&edma0 1 28>, |
| <&edma0 1 29>; |
| status = "disabled"; |
| }; |
| |
| lpuart3: serial@2290000 { |
| compatible = "fsl,ls1028a-lpuart"; |
| reg = <0x0 0x2290000 0x0 0x1000>; |
| interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "ipg"; |
| dma-names = "rx","tx"; |
| dmas = <&edma0 1 26>, |
| <&edma0 1 27>; |
| status = "disabled"; |
| }; |
| |
| lpuart4: serial@22a0000 { |
| compatible = "fsl,ls1028a-lpuart"; |
| reg = <0x0 0x22a0000 0x0 0x1000>; |
| interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "ipg"; |
| dma-names = "rx","tx"; |
| dmas = <&edma0 1 24>, |
| <&edma0 1 25>; |
| status = "disabled"; |
| }; |
| |
| lpuart5: serial@22b0000 { |
| compatible = "fsl,ls1028a-lpuart"; |
| reg = <0x0 0x22b0000 0x0 0x1000>; |
| interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "ipg"; |
| dma-names = "rx","tx"; |
| dmas = <&edma0 1 22>, |
| <&edma0 1 23>; |
| status = "disabled"; |
| }; |
| |
| edma0: dma-controller@22c0000 { |
| #dma-cells = <2>; |
| compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; |
| reg = <0x0 0x22c0000 0x0 0x10000>, |
| <0x0 0x22d0000 0x0 0x10000>, |
| <0x0 0x22e0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma-tx", "edma-err"; |
| dma-channels = <32>; |
| clock-names = "dmamux0", "dmamux1"; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| }; |
| |
| gpio1: gpio@2300000 { |
| compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; |
| reg = <0x0 0x2300000 0x0 0x10000>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| little-endian; |
| }; |
| |
| gpio2: gpio@2310000 { |
| compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; |
| reg = <0x0 0x2310000 0x0 0x10000>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| little-endian; |
| }; |
| |
| gpio3: gpio@2320000 { |
| compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; |
| reg = <0x0 0x2320000 0x0 0x10000>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| little-endian; |
| }; |
| |
| usb0: usb@3100000 { |
| compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; |
| reg = <0x0 0x3100000 0x0 0x10000>; |
| interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| snps,dis_rxdet_inp3_quirk; |
| snps,quirk-frame-length-adjustment = <0x20>; |
| snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; |
| status = "disabled"; |
| }; |
| |
| usb1: usb@3110000 { |
| compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; |
| reg = <0x0 0x3110000 0x0 0x10000>; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| snps,dis_rxdet_inp3_quirk; |
| snps,quirk-frame-length-adjustment = <0x20>; |
| snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; |
| status = "disabled"; |
| }; |
| |
| sata: sata@3200000 { |
| compatible = "fsl,ls1028a-ahci"; |
| reg = <0x0 0x3200000 0x0 0x10000>, |
| <0x7 0x100520 0x0 0x4>; |
| reg-names = "ahci", "sata-ecc"; |
| interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| status = "disabled"; |
| }; |
| |
| pcie1: pcie@3400000 { |
| compatible = "fsl,ls1028a-pcie"; |
| reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ |
| <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ |
| reg-names = "regs", "config"; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ |
| <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ |
| interrupt-names = "pme", "aer"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| dma-coherent; |
| num-viewport = <8>; |
| bus-range = <0x0 0xff>; |
| ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ |
| 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
| msi-parent = <&its>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ |
| status = "disabled"; |
| }; |
| |
| pcie_ep1: pcie-ep@3400000 { |
| compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; |
| reg = <0x00 0x03400000 0x0 0x00100000 |
| 0x80 0x00000000 0x8 0x00000000>; |
| reg-names = "regs", "addr_space"; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ |
| interrupt-names = "pme"; |
| num-ib-windows = <6>; |
| num-ob-windows = <8>; |
| status = "disabled"; |
| }; |
| |
| pcie2: pcie@3500000 { |
| compatible = "fsl,ls1028a-pcie"; |
| reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ |
| <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ |
| reg-names = "regs", "config"; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "pme", "aer"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| dma-coherent; |
| num-viewport = <8>; |
| bus-range = <0x0 0xff>; |
| ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ |
| 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
| msi-parent = <&its>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; |
| iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ |
| status = "disabled"; |
| }; |
| |
| pcie_ep2: pcie-ep@3500000 { |
| compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; |
| reg = <0x00 0x03500000 0x0 0x00100000 |
| 0x88 0x00000000 0x8 0x00000000>; |
| reg-names = "regs", "addr_space"; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ |
| interrupt-names = "pme"; |
| num-ib-windows = <6>; |
| num-ob-windows = <8>; |
| status = "disabled"; |
| }; |
| |
| smmu: iommu@5000000 { |
| compatible = "arm,mmu-500"; |
| reg = <0 0x5000000 0 0x800000>; |
| #global-interrupts = <8>; |
| #iommu-cells = <1>; |
| dma-coherent; |
| stream-match-mask = <0x7c00>; |
| /* global secure fault */ |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| /* combined secure interrupt */ |
| <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| /* global non-secure fault */ |
| <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| /* combined non-secure interrupt */ |
| <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
| /* performance counter interrupts 0-7 */ |
| <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| /* per context interrupt, 64 interrupts */ |
| <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| crypto: crypto@8000000 { |
| compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; |
| fsl,sec-era = <10>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x00 0x8000000 0x100000>; |
| reg = <0x00 0x8000000 0x0 0x100000>; |
| interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| dma-coherent; |
| |
| sec_jr0: jr@10000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x10000 0x10000>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr1: jr@20000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x20000 0x10000>; |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr2: jr@30000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x30000 0x10000>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr3: jr@40000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x40000 0x10000>; |
| interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| qdma: dma-controller@8380000 { |
| compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; |
| reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ |
| <0x0 0x8390000 0x0 0x10000>, /* Status regs */ |
| <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ |
| interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "qdma-error", "qdma-queue0", |
| "qdma-queue1", "qdma-queue2", "qdma-queue3"; |
| dma-channels = <8>; |
| block-number = <1>; |
| block-offset = <0x10000>; |
| fsl,dma-queues = <2>; |
| status-sizes = <64>; |
| queue-sizes = <64 64>; |
| }; |
| |
| cluster1_core0_watchdog: watchdog@c000000 { |
| compatible = "arm,sp805", "arm,primecell"; |
| reg = <0x0 0xc000000 0x0 0x1000>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(16)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(16)>; |
| clock-names = "wdog_clk", "apb_pclk"; |
| }; |
| |
| cluster1_core1_watchdog: watchdog@c010000 { |
| compatible = "arm,sp805", "arm,primecell"; |
| reg = <0x0 0xc010000 0x0 0x1000>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(16)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(16)>; |
| clock-names = "wdog_clk", "apb_pclk"; |
| }; |
| |
| malidp0: display@f080000 { |
| compatible = "arm,mali-dp500"; |
| reg = <0x0 0xf080000 0x0 0x10000>; |
| interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, |
| <0 223 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "DE", "SE"; |
| clocks = <&dpclk>, |
| <&clockgen QORIQ_CLK_HWACCEL 2>, |
| <&clockgen QORIQ_CLK_HWACCEL 2>, |
| <&clockgen QORIQ_CLK_HWACCEL 2>; |
| clock-names = "pxlclk", "mclk", "aclk", "pclk"; |
| arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; |
| arm,malidp-arqos-value = <0xd000d000>; |
| |
| port { |
| dpi0_out: endpoint { |
| |
| }; |
| }; |
| }; |
| |
| gpu: gpu@f0c0000 { |
| compatible = "vivante,gc"; |
| reg = <0x0 0xf0c0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_HWACCEL 2>, |
| <&clockgen QORIQ_CLK_HWACCEL 2>, |
| <&clockgen QORIQ_CLK_HWACCEL 2>; |
| clock-names = "core", "shader", "bus"; |
| #cooling-cells = <2>; |
| }; |
| |
| sai1: audio-controller@f100000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,vf610-sai"; |
| reg = <0x0 0xf100000 0x0 0x10000>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 4>, |
| <&edma0 1 3>; |
| fsl,sai-asynchronous; |
| status = "disabled"; |
| }; |
| |
| sai2: audio-controller@f110000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,vf610-sai"; |
| reg = <0x0 0xf110000 0x0 0x10000>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 6>, |
| <&edma0 1 5>; |
| fsl,sai-asynchronous; |
| status = "disabled"; |
| }; |
| |
| sai3: audio-controller@f120000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,vf610-sai"; |
| reg = <0x0 0xf120000 0x0 0x10000>; |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 8>, |
| <&edma0 1 7>; |
| fsl,sai-asynchronous; |
| status = "disabled"; |
| }; |
| |
| sai4: audio-controller@f130000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,vf610-sai"; |
| reg = <0x0 0xf130000 0x0 0x10000>; |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 10>, |
| <&edma0 1 9>; |
| fsl,sai-asynchronous; |
| status = "disabled"; |
| }; |
| |
| sai5: audio-controller@f140000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,vf610-sai"; |
| reg = <0x0 0xf140000 0x0 0x10000>; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 12>, |
| <&edma0 1 11>; |
| fsl,sai-asynchronous; |
| status = "disabled"; |
| }; |
| |
| sai6: audio-controller@f150000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,vf610-sai"; |
| reg = <0x0 0xf150000 0x0 0x10000>; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(2)>; |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 14>, |
| <&edma0 1 13>; |
| fsl,sai-asynchronous; |
| status = "disabled"; |
| }; |
| |
| dpclk: clock-controller@f1f0000 { |
| compatible = "fsl,ls1028a-plldig"; |
| reg = <0x0 0xf1f0000 0x0 0x10000>; |
| #clock-cells = <0>; |
| clocks = <&osc_27m>; |
| }; |
| |
| tmu: tmu@1f80000 { |
| compatible = "fsl,qoriq-tmu"; |
| reg = <0x0 0x1f80000 0x0 0x10000>; |
| interrupts = <0 23 0x4>; |
| fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; |
| fsl,tmu-calibration = |
| <0x00000000 0x00000024>, |
| <0x00000001 0x0000002b>, |
| <0x00000002 0x00000031>, |
| <0x00000003 0x00000038>, |
| <0x00000004 0x0000003f>, |
| <0x00000005 0x00000045>, |
| <0x00000006 0x0000004c>, |
| <0x00000007 0x00000053>, |
| <0x00000008 0x00000059>, |
| <0x00000009 0x00000060>, |
| <0x0000000a 0x00000066>, |
| <0x0000000b 0x0000006d>, |
| |
| <0x00010000 0x0000001c>, |
| <0x00010001 0x00000024>, |
| <0x00010002 0x0000002c>, |
| <0x00010003 0x00000035>, |
| <0x00010004 0x0000003d>, |
| <0x00010005 0x00000045>, |
| <0x00010006 0x0000004d>, |
| <0x00010007 0x00000055>, |
| <0x00010008 0x0000005e>, |
| <0x00010009 0x00000066>, |
| <0x0001000a 0x0000006e>, |
| |
| <0x00020000 0x00000018>, |
| <0x00020001 0x00000022>, |
| <0x00020002 0x0000002d>, |
| <0x00020003 0x00000038>, |
| <0x00020004 0x00000043>, |
| <0x00020005 0x0000004d>, |
| <0x00020006 0x00000058>, |
| <0x00020007 0x00000063>, |
| <0x00020008 0x0000006e>, |
| |
| <0x00030000 0x00000010>, |
| <0x00030001 0x0000001c>, |
| <0x00030002 0x00000029>, |
| <0x00030003 0x00000036>, |
| <0x00030004 0x00000042>, |
| <0x00030005 0x0000004f>, |
| <0x00030006 0x0000005b>, |
| <0x00030007 0x00000068>; |
| little-endian; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| pcie@1f0000000 { /* Integrated Endpoint Root Complex */ |
| compatible = "pci-host-ecam-generic"; |
| reg = <0x01 0xf0000000 0x0 0x100000>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| msi-parent = <&its>; |
| device_type = "pci"; |
| bus-range = <0x0 0x0>; |
| dma-coherent; |
| msi-map = <0 &its 0x17 0xe>; |
| iommu-map = <0 &smmu 0x17 0xe>; |
| /* PF0-6 BAR0 - non-prefetchable memory */ |
| ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 |
| /* PF0-6 BAR2 - prefetchable memory */ |
| 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 |
| /* PF0: VF0-1 BAR0 - non-prefetchable memory */ |
| 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 |
| /* PF0: VF0-1 BAR2 - prefetchable memory */ |
| 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 |
| /* PF1: VF0-1 BAR0 - non-prefetchable memory */ |
| 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 |
| /* PF1: VF0-1 BAR2 - prefetchable memory */ |
| 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 |
| /* BAR4 (PF5) - non-prefetchable memory */ |
| 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; |
| |
| enetc_port0: ethernet@0,0 { |
| compatible = "fsl,enetc"; |
| reg = <0x000000 0 0 0 0>; |
| status = "disabled"; |
| }; |
| |
| enetc_port1: ethernet@0,1 { |
| compatible = "fsl,enetc"; |
| reg = <0x000100 0 0 0 0>; |
| status = "disabled"; |
| }; |
| |
| enetc_port2: ethernet@0,2 { |
| compatible = "fsl,enetc"; |
| reg = <0x000200 0 0 0 0>; |
| phy-mode = "internal"; |
| status = "disabled"; |
| |
| fixed-link { |
| speed = <2500>; |
| full-duplex; |
| pause; |
| }; |
| }; |
| |
| enetc_mdio_pf3: mdio@0,3 { |
| compatible = "fsl,enetc-mdio"; |
| reg = <0x000300 0 0 0 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| ethernet@0,4 { |
| compatible = "fsl,enetc-ptp"; |
| reg = <0x000400 0 0 0 0>; |
| clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; |
| little-endian; |
| fsl,extts-fifo; |
| }; |
| |
| mscc_felix: ethernet-switch@0,5 { |
| reg = <0x000500 0 0 0 0>; |
| /* IEP INT_B */ |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| |
| mscc_felix_ports: ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| /* External ports */ |
| mscc_felix_port0: port@0 { |
| reg = <0>; |
| status = "disabled"; |
| }; |
| |
| mscc_felix_port1: port@1 { |
| reg = <1>; |
| status = "disabled"; |
| }; |
| |
| mscc_felix_port2: port@2 { |
| reg = <2>; |
| status = "disabled"; |
| }; |
| |
| mscc_felix_port3: port@3 { |
| reg = <3>; |
| status = "disabled"; |
| }; |
| |
| /* Internal ports */ |
| mscc_felix_port4: port@4 { |
| reg = <4>; |
| phy-mode = "internal"; |
| ethernet = <&enetc_port2>; |
| status = "disabled"; |
| |
| fixed-link { |
| speed = <2500>; |
| full-duplex; |
| pause; |
| }; |
| }; |
| |
| mscc_felix_port5: port@5 { |
| reg = <5>; |
| phy-mode = "internal"; |
| ethernet = <&enetc_port3>; |
| status = "disabled"; |
| |
| fixed-link { |
| speed = <1000>; |
| full-duplex; |
| pause; |
| }; |
| }; |
| }; |
| }; |
| |
| enetc_port3: ethernet@0,6 { |
| compatible = "fsl,enetc"; |
| reg = <0x000600 0 0 0 0>; |
| phy-mode = "internal"; |
| status = "disabled"; |
| |
| fixed-link { |
| speed = <1000>; |
| full-duplex; |
| pause; |
| }; |
| }; |
| |
| rcec@1f,0 { |
| reg = <0x00f800 0 0 0 0>; |
| /* IEP INT_A */ |
| interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| /* Integrated Endpoint Register Block */ |
| ierb@1f0800000 { |
| compatible = "fsl,ls1028a-enetc-ierb"; |
| reg = <0x01 0xf0800000 0x0 0x10000>; |
| }; |
| |
| pwm0: pwm@2800000 { |
| compatible = "fsl,vf610-ftm-pwm"; |
| #pwm-cells = <3>; |
| reg = <0x0 0x2800000 0x0 0x10000>; |
| clock-names = "ftm_sys", "ftm_ext", |
| "ftm_fix", "ftm_cnt_clk_en"; |
| clocks = <&clockgen 4 1>, <&clockgen 4 1>, |
| <&rtc_clk>, <&clockgen 4 1>; |
| status = "disabled"; |
| }; |
| |
| pwm1: pwm@2810000 { |
| compatible = "fsl,vf610-ftm-pwm"; |
| #pwm-cells = <3>; |
| reg = <0x0 0x2810000 0x0 0x10000>; |
| clock-names = "ftm_sys", "ftm_ext", |
| "ftm_fix", "ftm_cnt_clk_en"; |
| clocks = <&clockgen 4 1>, <&clockgen 4 1>, |
| <&rtc_clk>, <&clockgen 4 1>; |
| status = "disabled"; |
| }; |
| |
| pwm2: pwm@2820000 { |
| compatible = "fsl,vf610-ftm-pwm"; |
| #pwm-cells = <3>; |
| reg = <0x0 0x2820000 0x0 0x10000>; |
| clock-names = "ftm_sys", "ftm_ext", |
| "ftm_fix", "ftm_cnt_clk_en"; |
| clocks = <&clockgen 4 1>, <&clockgen 4 1>, |
| <&rtc_clk>, <&clockgen 4 1>; |
| status = "disabled"; |
| }; |
| |
| pwm3: pwm@2830000 { |
| compatible = "fsl,vf610-ftm-pwm"; |
| #pwm-cells = <3>; |
| reg = <0x0 0x2830000 0x0 0x10000>; |
| clock-names = "ftm_sys", "ftm_ext", |
| "ftm_fix", "ftm_cnt_clk_en"; |
| clocks = <&clockgen 4 1>, <&clockgen 4 1>, |
| <&rtc_clk>, <&clockgen 4 1>; |
| status = "disabled"; |
| }; |
| |
| pwm4: pwm@2840000 { |
| compatible = "fsl,vf610-ftm-pwm"; |
| #pwm-cells = <3>; |
| reg = <0x0 0x2840000 0x0 0x10000>; |
| clock-names = "ftm_sys", "ftm_ext", |
| "ftm_fix", "ftm_cnt_clk_en"; |
| clocks = <&clockgen 4 1>, <&clockgen 4 1>, |
| <&rtc_clk>, <&clockgen 4 1>; |
| status = "disabled"; |
| }; |
| |
| pwm5: pwm@2850000 { |
| compatible = "fsl,vf610-ftm-pwm"; |
| #pwm-cells = <3>; |
| reg = <0x0 0x2850000 0x0 0x10000>; |
| clock-names = "ftm_sys", "ftm_ext", |
| "ftm_fix", "ftm_cnt_clk_en"; |
| clocks = <&clockgen 4 1>, <&clockgen 4 1>, |
| <&rtc_clk>, <&clockgen 4 1>; |
| status = "disabled"; |
| }; |
| |
| pwm6: pwm@2860000 { |
| compatible = "fsl,vf610-ftm-pwm"; |
| #pwm-cells = <3>; |
| reg = <0x0 0x2860000 0x0 0x10000>; |
| clock-names = "ftm_sys", "ftm_ext", |
| "ftm_fix", "ftm_cnt_clk_en"; |
| clocks = <&clockgen 4 1>, <&clockgen 4 1>, |
| <&rtc_clk>, <&clockgen 4 1>; |
| status = "disabled"; |
| }; |
| |
| pwm7: pwm@2870000 { |
| compatible = "fsl,vf610-ftm-pwm"; |
| #pwm-cells = <3>; |
| reg = <0x0 0x2870000 0x0 0x10000>; |
| clock-names = "ftm_sys", "ftm_ext", |
| "ftm_fix", "ftm_cnt_clk_en"; |
| clocks = <&clockgen 4 1>, <&clockgen 4 1>, |
| <&rtc_clk>, <&clockgen 4 1>; |
| status = "disabled"; |
| }; |
| |
| rcpm: power-controller@1e34040 { |
| compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; |
| reg = <0x0 0x1e34040 0x0 0x1c>; |
| #fsl,rcpm-wakeup-cells = <7>; |
| little-endian; |
| }; |
| |
| ftm_alarm0: timer@2800000 { |
| compatible = "fsl,ls1028a-ftm-alarm"; |
| reg = <0x0 0x2800000 0x0 0x10000>; |
| fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; |
| interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| ftm_alarm1: timer@2810000 { |
| compatible = "fsl,ls1028a-ftm-alarm"; |
| reg = <0x0 0x2810000 0x0 0x10000>; |
| fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| }; |
