| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2022 NXP |
| * Copyright 2023 Variscite Ltd. |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx93.dtsi" |
| |
| /{ |
| model = "Variscite VAR-SOM-MX93 module"; |
| compatible = "variscite,var-som-mx93", "fsl,imx93"; |
| |
| mmc_pwrseq: mmc-pwrseq { |
| compatible = "mmc-pwrseq-simple"; |
| post-power-on-delay-ms = <100>; |
| power-off-delay-us = <10000>; |
| reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ |
| <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ |
| }; |
| |
| reg_eqos_phy: regulator-eqos-phy { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_eqos_phy>; |
| regulator-name = "eth_phy_pwr"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| startup-delay-us = <100000>; |
| regulator-always-on; |
| }; |
| }; |
| |
| &eqos { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_eqos>; |
| phy-mode = "rgmii"; |
| phy-handle = <ðphy0>; |
| status = "okay"; |
| |
| mdio { |
| compatible = "snps,dwmac-mdio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-frequency = <1000000>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| eee-broken-1000t; |
| }; |
| }; |
| }; |
| |
| /* eMMC */ |
| &usdhc1 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1>; |
| pinctrl-2 = <&pinctrl_usdhc1>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_eqos: eqosgrp { |
| fsl,pins = < |
| MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e |
| MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e |
| MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e |
| MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e |
| MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e |
| MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e |
| MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe |
| MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e |
| MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e |
| MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e |
| MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e |
| MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e |
| MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe |
| MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e |
| >; |
| }; |
| |
| pinctrl_reg_eqos_phy: regeqosgrp { |
| fsl,pins = < |
| MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe |
| MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe |
| MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe |
| MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe |
| MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe |
| MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe |
| MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe |
| MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe |
| MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe |
| MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe |
| MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe |
| >; |
| }; |
| }; |
