| // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| /* |
| * Device Tree Source for the R-Car V4M (R8A779H0) SoC |
| * |
| * Copyright (C) 2023 Renesas Electronics Corp. |
| */ |
| |
| #include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/renesas,r8a779h0-sysc.h> |
| |
| / { |
| compatible = "renesas,r8a779h0"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cluster0_opp: opp-table-0 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp-500000000 { |
| opp-hz = /bits/ 64 <500000000>; |
| opp-microvolt = <825000>; |
| clock-latency-ns = <500000>; |
| }; |
| opp-1000000000 { |
| opp-hz = /bits/ 64 <1000000000>; |
| opp-microvolt = <825000>; |
| clock-latency-ns = <500000>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&a76_0>; |
| }; |
| core1 { |
| cpu = <&a76_1>; |
| }; |
| core2 { |
| cpu = <&a76_2>; |
| }; |
| core3 { |
| cpu = <&a76_3>; |
| }; |
| }; |
| }; |
| |
| a76_0: cpu@0 { |
| compatible = "arm,cortex-a76"; |
| reg = <0>; |
| device_type = "cpu"; |
| power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; |
| next-level-cache = <&L3_CA76>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0>; |
| clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| a76_1: cpu@100 { |
| compatible = "arm,cortex-a76"; |
| reg = <0x100>; |
| device_type = "cpu"; |
| power-domains = <&sysc R8A779H0_PD_A1E0D0C1>; |
| next-level-cache = <&L3_CA76>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0>; |
| clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| a76_2: cpu@200 { |
| compatible = "arm,cortex-a76"; |
| reg = <0x200>; |
| device_type = "cpu"; |
| power-domains = <&sysc R8A779H0_PD_A1E0D0C2>; |
| next-level-cache = <&L3_CA76>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0>; |
| clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| a76_3: cpu@300 { |
| compatible = "arm,cortex-a76"; |
| reg = <0x300>; |
| device_type = "cpu"; |
| power-domains = <&sysc R8A779H0_PD_A1E0D0C3>; |
| next-level-cache = <&L3_CA76>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CPU_SLEEP_0>; |
| clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| CPU_SLEEP_0: cpu-sleep-0 { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x0010000>; |
| local-timer-stop; |
| entry-latency-us = <400>; |
| exit-latency-us = <500>; |
| min-residency-us = <4000>; |
| }; |
| }; |
| |
| L3_CA76: cache-controller { |
| compatible = "cache"; |
| power-domains = <&sysc R8A779H0_PD_A2E0D0>; |
| cache-unified; |
| cache-level = <3>; |
| }; |
| }; |
| |
| extal_clk: extal-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| extalr_clk: extalr-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| pmu-a76 { |
| compatible = "arm,cortex-a76-pmu"; |
| interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0", "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| /* External SCIF clock - to be overridden by boards that provide it */ |
| scif_clk: scif-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| soc: soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| rwdt: watchdog@e6020000 { |
| compatible = "renesas,r8a779h0-wdt", |
| "renesas,rcar-gen4-wdt"; |
| reg = <0 0xe6020000 0 0x0c>; |
| interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 907>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 907>; |
| status = "disabled"; |
| }; |
| |
| pfc: pinctrl@e6050000 { |
| compatible = "renesas,pfc-r8a779h0"; |
| reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, |
| <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, |
| <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, |
| <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; |
| }; |
| |
| gpio0: gpio@e6050180 { |
| compatible = "renesas,gpio-r8a779h0", |
| "renesas,rcar-gen4-gpio"; |
| reg = <0 0xe6050180 0 0x54>; |
| interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 0 19>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 915>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 915>; |
| }; |
| |
| gpio1: gpio@e6050980 { |
| compatible = "renesas,gpio-r8a779h0", |
| "renesas,rcar-gen4-gpio"; |
| reg = <0 0xe6050980 0 0x54>; |
| interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 32 30>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 915>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 915>; |
| }; |
| |
| gpio2: gpio@e6058180 { |
| compatible = "renesas,gpio-r8a779h0", |
| "renesas,rcar-gen4-gpio"; |
| reg = <0 0xe6058180 0 0x54>; |
| interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 64 20>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 916>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 916>; |
| }; |
| |
| gpio3: gpio@e6058980 { |
| compatible = "renesas,gpio-r8a779h0", |
| "renesas,rcar-gen4-gpio"; |
| reg = <0 0xe6058980 0 0x54>; |
| interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 96 32>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 916>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 916>; |
| }; |
| |
| gpio4: gpio@e6060180 { |
| compatible = "renesas,gpio-r8a779h0", |
| "renesas,rcar-gen4-gpio"; |
| reg = <0 0xe6060180 0 0x54>; |
| interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 128 25>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 917>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 917>; |
| }; |
| |
| gpio5: gpio@e6060980 { |
| compatible = "renesas,gpio-r8a779h0", |
| "renesas,rcar-gen4-gpio"; |
| reg = <0 0xe6060980 0 0x54>; |
| interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 160 21>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 917>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 917>; |
| }; |
| |
| gpio6: gpio@e6061180 { |
| compatible = "renesas,gpio-r8a779h0", |
| "renesas,rcar-gen4-gpio"; |
| reg = <0 0xe6061180 0 0x54>; |
| interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 192 21>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 917>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 917>; |
| }; |
| |
| gpio7: gpio@e6061980 { |
| compatible = "renesas,gpio-r8a779h0", |
| "renesas,rcar-gen4-gpio"; |
| reg = <0 0xe6061980 0 0x54>; |
| interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 224 21>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 917>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 917>; |
| }; |
| |
| cpg: clock-controller@e6150000 { |
| compatible = "renesas,r8a779h0-cpg-mssr"; |
| reg = <0 0xe6150000 0 0x4000>; |
| clocks = <&extal_clk>, <&extalr_clk>; |
| clock-names = "extal", "extalr"; |
| #clock-cells = <2>; |
| #power-domain-cells = <0>; |
| #reset-cells = <1>; |
| }; |
| |
| rst: reset-controller@e6160000 { |
| compatible = "renesas,r8a779h0-rst"; |
| reg = <0 0xe6160000 0 0x4000>; |
| }; |
| |
| sysc: system-controller@e6180000 { |
| compatible = "renesas,r8a779h0-sysc"; |
| reg = <0 0xe6180000 0 0x4000>; |
| #power-domain-cells = <1>; |
| }; |
| |
| i2c0: i2c@e6500000 { |
| compatible = "renesas,i2c-r8a779h0", |
| "renesas,rcar-gen4-i2c"; |
| reg = <0 0xe6500000 0 0x40>; |
| interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 518>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 518>; |
| dmas = <&dmac1 0x91>, <&dmac1 0x90>, |
| <&dmac2 0x91>, <&dmac2 0x90>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| i2c-scl-internal-delay-ns = <110>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@e6508000 { |
| compatible = "renesas,i2c-r8a779h0", |
| "renesas,rcar-gen4-i2c"; |
| reg = <0 0xe6508000 0 0x40>; |
| interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 519>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 519>; |
| dmas = <&dmac1 0x93>, <&dmac1 0x92>, |
| <&dmac2 0x93>, <&dmac2 0x92>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| i2c-scl-internal-delay-ns = <110>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@e6510000 { |
| compatible = "renesas,i2c-r8a779h0", |
| "renesas,rcar-gen4-i2c"; |
| reg = <0 0xe6510000 0 0x40>; |
| interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 520>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 520>; |
| dmas = <&dmac1 0x95>, <&dmac1 0x94>, |
| <&dmac2 0x95>, <&dmac2 0x94>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| i2c-scl-internal-delay-ns = <110>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@e66d0000 { |
| compatible = "renesas,i2c-r8a779h0", |
| "renesas,rcar-gen4-i2c"; |
| reg = <0 0xe66d0000 0 0x40>; |
| interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 521>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 521>; |
| dmas = <&dmac1 0x97>, <&dmac1 0x96>, |
| <&dmac2 0x97>, <&dmac2 0x96>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| i2c-scl-internal-delay-ns = <110>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| hscif0: serial@e6540000 { |
| compatible = "renesas,hscif-r8a779h0", |
| "renesas,rcar-gen4-hscif", "renesas,hscif"; |
| reg = <0 0xe6540000 0 0x60>; |
| interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 514>, |
| <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 514>; |
| dmas = <&dmac1 0x31>, <&dmac1 0x30>, |
| <&dmac2 0x31>, <&dmac2 0x30>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| avb0: ethernet@e6800000 { |
| compatible = "renesas,etheravb-r8a779h0", |
| "renesas,etheravb-rcar-gen4"; |
| reg = <0 0xe6800000 0 0x1000>; |
| interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15", |
| "ch16", "ch17", "ch18", "ch19", |
| "ch20", "ch21", "ch22", "ch23", |
| "ch24"; |
| clocks = <&cpg CPG_MOD 211>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A779H0_PD_C4>; |
| resets = <&cpg 211>; |
| phy-mode = "rgmii"; |
| rx-internal-delay-ps = <0>; |
| tx-internal-delay-ps = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| avb1: ethernet@e6810000 { |
| compatible = "renesas,etheravb-r8a779h0", |
| "renesas,etheravb-rcar-gen4"; |
| reg = <0 0xe6810000 0 0x1000>; |
| interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15", |
| "ch16", "ch17", "ch18", "ch19", |
| "ch20", "ch21", "ch22", "ch23", |
| "ch24"; |
| clocks = <&cpg CPG_MOD 212>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A779H0_PD_C4>; |
| resets = <&cpg 212>; |
| phy-mode = "rgmii"; |
| rx-internal-delay-ps = <0>; |
| tx-internal-delay-ps = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| avb2: ethernet@e6820000 { |
| compatible = "renesas,etheravb-r8a779h0", |
| "renesas,etheravb-rcar-gen4"; |
| reg = <0 0xe6820000 0 0x1000>; |
| interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15", |
| "ch16", "ch17", "ch18", "ch19", |
| "ch20", "ch21", "ch22", "ch23", |
| "ch24"; |
| clocks = <&cpg CPG_MOD 213>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A779H0_PD_C4>; |
| resets = <&cpg 213>; |
| phy-mode = "rgmii"; |
| rx-internal-delay-ps = <0>; |
| tx-internal-delay-ps = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| dmac1: dma-controller@e7350000 { |
| compatible = "renesas,dmac-r8a779h0", |
| "renesas,rcar-gen4-dmac"; |
| reg = <0 0xe7350000 0 0x1000>, |
| <0 0xe7300000 0 0x10000>; |
| interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", "ch4", |
| "ch5", "ch6", "ch7", "ch8", "ch9", |
| "ch10", "ch11", "ch12", "ch13", |
| "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 709>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 709>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| }; |
| |
| dmac2: dma-controller@e7351000 { |
| compatible = "renesas,dmac-r8a779h0", |
| "renesas,rcar-gen4-dmac"; |
| reg = <0 0xe7351000 0 0x1000>, |
| <0 0xe7310000 0 0x10000>; |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", "ch4", |
| "ch5", "ch6", "ch7"; |
| clocks = <&cpg CPG_MOD 710>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 710>; |
| #dma-cells = <1>; |
| dma-channels = <8>; |
| }; |
| |
| mmc0: mmc@ee140000 { |
| compatible = "renesas,sdhi-r8a779h0", |
| "renesas,rcar-gen4-sdhi"; |
| reg = <0 0xee140000 0 0x2000>; |
| interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 706>, |
| <&cpg CPG_CORE R8A779H0_CLK_SD0H>; |
| clock-names = "core", "clkh"; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 706>; |
| max-frequency = <200000000>; |
| status = "disabled"; |
| }; |
| |
| rpc: spi@ee200000 { |
| compatible = "renesas,r8a779h0-rpc-if", |
| "renesas,rcar-gen4-rpc-if"; |
| reg = <0 0xee200000 0 0x200>, |
| <0 0x08000000 0 0x04000000>, |
| <0 0xee208000 0 0x100>; |
| reg-names = "regs", "dirmap", "wbuf"; |
| interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 629>; |
| power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; |
| resets = <&cpg 629>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@f1000000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x0 0xf1000000 0 0x20000>, |
| <0x0 0xf1060000 0 0x110000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| prr: chipid@fff00044 { |
| compatible = "renesas,prr"; |
| reg = <0 0xfff00044 0 4>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, |
| <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| }; |