tools/perf/pmu-events/arch/riscv/thead/c900-legacy/cache.json

[
  {
    "EventName": "L1_ICACHE_ACCESS",
    "EventCode": "0x00000001",
    "BriefDescription": "L1 instruction cache access"
  },
  {
    "EventName": "L1_ICACHE_MISS",
    "EventCode": "0x00000002",
    "BriefDescription": "L1 instruction cache miss"
  },
  {
    "EventName": "ITLB_MISS",
    "EventCode": "0x00000003",
    "BriefDescription": "I-UTLB miss"
  },
  {
    "EventName": "DTLB_MISS",
    "EventCode": "0x00000004",
    "BriefDescription": "D-UTLB miss"
  },
  {
    "EventName": "JTLB_MISS",
    "EventCode": "0x00000005",
    "BriefDescription": "JTLB miss"
  },
  {
    "EventName": "L1_DCACHE_READ_ACCESS",
    "EventCode": "0x0000000c",
    "BriefDescription": "L1 data cache read access"
  },
  {
    "EventName": "L1_DCACHE_READ_MISS",
    "EventCode": "0x0000000d",
    "BriefDescription": "L1 data cache read miss"
  },
  {
    "EventName": "L1_DCACHE_WRITE_ACCESS",
    "EventCode": "0x0000000e",
    "BriefDescription": "L1 data cache write access"
  },
  {
    "EventName": "L1_DCACHE_WRITE_MISS",
    "EventCode": "0x0000000f",
    "BriefDescription": "L1 data cache write miss"
  },
  {
    "EventName": "LL_CACHE_READ_ACCESS",
    "EventCode": "0x00000010",
    "BriefDescription": "LL Cache read access"
  },
  {
    "EventName": "LL_CACHE_READ_MISS",
    "EventCode": "0x00000011",
    "BriefDescription": "LL Cache read miss"
  },
  {
    "EventName": "LL_CACHE_WRITE_ACCESS",
    "EventCode": "0x00000012",
    "BriefDescription": "LL Cache write access"
  },
  {
    "EventName": "LL_CACHE_WRITE_MISS",
    "EventCode": "0x00000013",
    "BriefDescription": "LL Cache write miss"
  }
]