| [ |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x80", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "1009", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x10", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "20011", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x100", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "503", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x20", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "100007", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x4", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x200", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "101", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x40", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "2003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x8", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "50021", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", |
| "PEBS": "2", |
| "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", |
| "EventCode": "0x2A,0x2B", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x3FBFC00001", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", |
| "EventCode": "0x2A,0x2B", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x3F3FC00002", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Number of times an RTM execution aborted.", |
| "EventCode": "0xc9", |
| "EventName": "RTM_RETIRED.ABORTED", |
| "PublicDescription": "Counts the number of times RTM abort was triggered.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Number of times an RTM execution successfully committed", |
| "EventCode": "0xc9", |
| "EventName": "RTM_RETIRED.COMMIT", |
| "PublicDescription": "Counts the number of times RTM commit succeeded.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Number of times an RTM execution started.", |
| "EventCode": "0xc9", |
| "EventName": "RTM_RETIRED.START", |
| "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", |
| "EventCode": "0x54", |
| "EventName": "TX_MEM.ABORT_CAPACITY_READ", |
| "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", |
| "SampleAfterValue": "100003", |
| "UMask": "0x80" |
| }, |
| { |
| "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", |
| "EventCode": "0x54", |
| "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", |
| "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", |
| "EventCode": "0x54", |
| "EventName": "TX_MEM.ABORT_CONFLICT", |
| "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| } |
| ] |
