| * Renesas R-Car Display Unit (DU) |
| |
| Required Properties: |
| |
| - compatible: must be one of the following. |
| - "renesas,du-r8a7742" for R8A7742 (RZ/G1H) compatible DU |
| - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU |
| - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU |
| - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU |
| - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU |
| - "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU |
| - "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU |
| - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU |
| - "renesas,du-r8a774e1" for R8A774E1 (RZ/G2H) compatible DU |
| - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU |
| - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU |
| - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU |
| - "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU |
| - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU |
| - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU |
| - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU |
| - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU |
| - "renesas,du-r8a77961" for R8A77961 (R-Car M3-W+) compatible DU |
| - "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU |
| - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU |
| - "renesas,du-r8a77980" for R8A77980 (R-Car V3H) compatible DU |
| - "renesas,du-r8a77990" for R8A77990 (R-Car E3) compatible DU |
| - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU |
| |
| - reg: the memory-mapped I/O registers base address and length |
| |
| - interrupts: Interrupt specifiers for the DU interrupts. |
| |
| - clocks: A list of phandles + clock-specifier pairs, one for each entry in |
| the clock-names property. |
| - clock-names: Name of the clocks. This property is model-dependent. |
| - R8A7779 uses a single functional clock. The clock doesn't need to be |
| named. |
| - All other DU instances use one functional clock per channel The |
| functional clocks must be named "du.x" with "x" being the channel |
| numerical index. |
| - In addition to the functional clocks, all DU versions also support |
| externally supplied pixel clocks. Those clocks are optional. When |
| supplied they must be named "dclkin.x" with "x" being the input clock |
| numerical index. |
| |
| - renesas,cmms: A list of phandles to the CMM instances present in the SoC, |
| one for each available DU channel. The property shall not be specified for |
| SoCs that do not provide any CMM (such as V3M and V3H). |
| |
| - renesas,vsps: A list of phandle and channel index tuples to the VSPs that |
| handle the memory interfaces for the DU channels. The phandle identifies the |
| VSP instance that serves the DU channel, and the channel index identifies |
| the LIF instance in that VSP. |
| |
| Optional properties: |
| - resets: A list of phandle + reset-specifier pairs, one for each entry in |
| the reset-names property. |
| - reset-names: Names of the resets. This property is model-dependent. |
| - All but R8A7779 use one reset for a group of one or more successive |
| channels. The resets must be named "du.x" with "x" being the numerical |
| index of the lowest channel in the group. |
| |
| Required nodes: |
| |
| The connections to the DU output video ports are modeled using the OF graph |
| bindings specified in Documentation/devicetree/bindings/graph.txt. |
| |
| The following table lists for each supported model the port number |
| corresponding to each DU output. |
| |
| Port0 Port1 Port2 Port3 |
| ----------------------------------------------------------------------------- |
| R8A7742 (RZ/G1H) DPAD 0 LVDS 0 LVDS 1 - |
| R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - - |
| R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - - |
| R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - - |
| R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 - |
| R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 - |
| R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 - |
| R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 - |
| R8A774E1 (RZ/G2H) DPAD 0 HDMI 0 LVDS 0 - |
| R8A7779 (R-Car H1) DPAD 0 DPAD 1 - - |
| R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 - |
| R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - - |
| R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - - |
| R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - - |
| R8A7794 (R-Car E2) DPAD 0 DPAD 1 - - |
| R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0 |
| R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 - |
| R8A77961 (R-Car M3-W+) DPAD 0 HDMI 0 LVDS 0 - |
| R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 - |
| R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - - |
| R8A77980 (R-Car V3H) DPAD 0 LVDS 0 - - |
| R8A77990 (R-Car E3) DPAD 0 LVDS 0 LVDS 1 - |
| R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 - |
| |
| |
| Example: R8A7795 (R-Car H3) ES2.0 DU |
| |
| du: display@feb00000 { |
| compatible = "renesas,du-r8a7795"; |
| reg = <0 0xfeb00000 0 0x80000>; |
| interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 724>, |
| <&cpg CPG_MOD 723>, |
| <&cpg CPG_MOD 722>, |
| <&cpg CPG_MOD 721>; |
| clock-names = "du.0", "du.1", "du.2", "du.3"; |
| resets = <&cpg 724>, <&cpg 722>; |
| reset-names = "du.0", "du.2"; |
| renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; |
| renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| du_out_rgb: endpoint { |
| }; |
| }; |
| port@1 { |
| reg = <1>; |
| du_out_hdmi0: endpoint { |
| remote-endpoint = <&dw_hdmi0_in>; |
| }; |
| }; |
| port@2 { |
| reg = <2>; |
| du_out_hdmi1: endpoint { |
| remote-endpoint = <&dw_hdmi1_in>; |
| }; |
| }; |
| port@3 { |
| reg = <3>; |
| du_out_lvds0: endpoint { |
| }; |
| }; |
| }; |
| }; |
