| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (C) 2015 - ARM Ltd |
| * Author: Marc Zyngier <marc.zyngier@arm.com> |
| */ |
| |
| #include <hyp/percpu.h> |
| #include <hyp/switch.h> |
| |
| #include <linux/arm-smccc.h> |
| #include <linux/kvm_host.h> |
| #include <linux/types.h> |
| #include <linux/jump_label.h> |
| #include <uapi/linux/psci.h> |
| |
| #include <kvm/arm_psci.h> |
| |
| #include <asm/barrier.h> |
| #include <asm/cpufeature.h> |
| #include <asm/kprobes.h> |
| #include <asm/kvm_asm.h> |
| #include <asm/kvm_emulate.h> |
| #include <asm/kvm_hyp.h> |
| #include <asm/kvm_mmu.h> |
| #include <asm/fpsimd.h> |
| #include <asm/debug-monitors.h> |
| #include <asm/processor.h> |
| #include <asm/thread_info.h> |
| |
| const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n"; |
| |
| /* kvm_host_data used by VHE */ |
| DEFINE_PER_CPU(kvm_host_data_t, kvm_host_data); |
| |
| static void __activate_traps(struct kvm_vcpu *vcpu) |
| { |
| u64 val; |
| |
| ___activate_traps(vcpu); |
| |
| val = read_sysreg(cpacr_el1); |
| val |= CPACR_EL1_TTA; |
| val &= ~CPACR_EL1_ZEN; |
| |
| /* |
| * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to |
| * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, |
| * except for some missing controls, such as TAM. |
| * In this case, CPTR_EL2.TAM has the same position with or without |
| * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM |
| * shift value for trapping the AMU accesses. |
| */ |
| |
| val |= CPTR_EL2_TAM; |
| |
| if (update_fp_enabled(vcpu)) { |
| if (vcpu_has_sve(vcpu)) |
| val |= CPACR_EL1_ZEN; |
| } else { |
| val &= ~CPACR_EL1_FPEN; |
| __activate_traps_fpsimd32(vcpu); |
| } |
| |
| write_sysreg(val, cpacr_el1); |
| |
| write_sysreg(kvm_get_hyp_vector(), vbar_el1); |
| } |
| NOKPROBE_SYMBOL(__activate_traps); |
| |
| static void __deactivate_traps(struct kvm_vcpu *vcpu) |
| { |
| extern char vectors[]; /* kernel exception vectors */ |
| |
| ___deactivate_traps(vcpu); |
| |
| write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); |
| |
| /* |
| * ARM errata 1165522 and 1530923 require the actual execution of the |
| * above before we can switch to the EL2/EL0 translation regime used by |
| * the host. |
| */ |
| asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); |
| |
| write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1); |
| write_sysreg(vectors, vbar_el1); |
| } |
| NOKPROBE_SYMBOL(__deactivate_traps); |
| |
| void activate_traps_vhe_load(struct kvm_vcpu *vcpu) |
| { |
| __activate_traps_common(vcpu); |
| } |
| |
| void deactivate_traps_vhe_put(void) |
| { |
| u64 mdcr_el2 = read_sysreg(mdcr_el2); |
| |
| mdcr_el2 &= MDCR_EL2_HPMN_MASK | |
| MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT | |
| MDCR_EL2_TPMS; |
| |
| write_sysreg(mdcr_el2, mdcr_el2); |
| |
| __deactivate_traps_common(); |
| } |
| |
| /* Switch to the guest for VHE systems running in EL2 */ |
| static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) |
| { |
| struct kvm_cpu_context *host_ctxt; |
| struct kvm_cpu_context *guest_ctxt; |
| u64 exit_code; |
| |
| host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; |
| host_ctxt->__hyp_running_vcpu = vcpu; |
| guest_ctxt = &vcpu->arch.ctxt; |
| |
| sysreg_save_host_state_vhe(host_ctxt); |
| |
| /* |
| * ARM erratum 1165522 requires us to configure both stage 1 and |
| * stage 2 translation for the guest context before we clear |
| * HCR_EL2.TGE. |
| * |
| * We have already configured the guest's stage 1 translation in |
| * kvm_vcpu_load_sysregs_vhe above. We must now call __activate_vm |
| * before __activate_traps, because __activate_vm configures |
| * stage 2 translation, and __activate_traps clear HCR_EL2.TGE |
| * (among other things). |
| */ |
| __activate_vm(vcpu->kvm); |
| __activate_traps(vcpu); |
| |
| sysreg_restore_guest_state_vhe(guest_ctxt); |
| __debug_switch_to_guest(vcpu); |
| |
| __set_guest_arch_workaround_state(vcpu); |
| |
| do { |
| /* Jump in the fire! */ |
| exit_code = __guest_enter(vcpu, host_ctxt); |
| |
| /* And we're baaack! */ |
| } while (fixup_guest_exit(vcpu, &exit_code)); |
| |
| __set_host_arch_workaround_state(vcpu); |
| |
| sysreg_save_guest_state_vhe(guest_ctxt); |
| |
| __deactivate_traps(vcpu); |
| |
| sysreg_restore_host_state_vhe(host_ctxt); |
| |
| if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) |
| __fpsimd_save_fpexc32(vcpu); |
| |
| __debug_switch_to_host(vcpu); |
| |
| return exit_code; |
| } |
| NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe); |
| |
| int __kvm_vcpu_run(struct kvm_vcpu *vcpu) |
| { |
| int ret; |
| |
| local_daif_mask(); |
| |
| /* |
| * Having IRQs masked via PMR when entering the guest means the GIC |
| * will not signal the CPU of interrupts of lower priority, and the |
| * only way to get out will be via guest exceptions. |
| * Naturally, we want to avoid this. |
| * |
| * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a |
| * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU. |
| */ |
| pmr_sync(); |
| |
| ret = __kvm_vcpu_run_vhe(vcpu); |
| |
| /* |
| * local_daif_restore() takes care to properly restore PSTATE.DAIF |
| * and the GIC PMR if the host is using IRQ priorities. |
| */ |
| local_daif_restore(DAIF_PROCCTX_NOIRQ); |
| |
| /* |
| * When we exit from the guest we change a number of CPU configuration |
| * parameters, such as traps. Make sure these changes take effect |
| * before running the host or additional guests. |
| */ |
| isb(); |
| |
| return ret; |
| } |
| |
| static void __hyp_call_panic(u64 spsr, u64 elr, u64 par, |
| struct kvm_cpu_context *host_ctxt) |
| { |
| struct kvm_vcpu *vcpu; |
| vcpu = host_ctxt->__hyp_running_vcpu; |
| |
| __deactivate_traps(vcpu); |
| sysreg_restore_host_state_vhe(host_ctxt); |
| |
| panic(__hyp_panic_string, |
| spsr, elr, |
| read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR), |
| read_sysreg(hpfar_el2), par, vcpu); |
| } |
| NOKPROBE_SYMBOL(__hyp_call_panic); |
| |
| void __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt) |
| { |
| u64 spsr = read_sysreg_el2(SYS_SPSR); |
| u64 elr = read_sysreg_el2(SYS_ELR); |
| u64 par = read_sysreg(par_el1); |
| |
| __hyp_call_panic(spsr, elr, par, host_ctxt); |
| unreachable(); |
| } |