| Marvell Prestera Switch Chip bindings |
| ------------------------------------- |
| |
| Required properties: |
| - compatible: must be "marvell,prestera" and one of the following |
| "marvell,prestera-98dx3236", |
| "marvell,prestera-98dx3336", |
| "marvell,prestera-98dx4251", |
| - reg: address and length of the register set for the device. |
| - interrupts: interrupt for the device |
| |
| Optional properties: |
| - dfx: phandle reference to the "DFX Server" node |
| |
| Example: |
| |
| switch { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; |
| |
| packet-processor@0 { |
| compatible = "marvell,prestera-98dx3236", "marvell,prestera"; |
| reg = <0 0x4000000>; |
| interrupts = <33>, <34>, <35>; |
| dfx = <&dfx>; |
| }; |
| }; |
| |
| DFX Server bindings |
| ------------------- |
| |
| Required properties: |
| - compatible: must be "marvell,dfx-server", "simple-bus" |
| - ranges: describes the address mapping of a memory-mapped bus. |
| - reg: address and length of the register set for the device. |
| |
| Example: |
| |
| dfx-server { |
| compatible = "marvell,dfx-server", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; |
| reg = <MBUS_ID(0x08, 0x00) 0 0x100000>; |
| }; |
| |
| Marvell Prestera SwitchDev bindings |
| ----------------------------------- |
| Optional properties: |
| - compatible: must be "marvell,prestera" |
| - base-mac-provider: describes handle to node which provides base mac address, |
| might be a static base mac address or nvme cell provider. |
| |
| Example: |
| |
| eeprom_mac_addr: eeprom-mac-addr { |
| compatible = "eeprom,mac-addr-cell"; |
| status = "okay"; |
| |
| nvmem = <&eeprom_at24>; |
| }; |
| |
| prestera { |
| compatible = "marvell,prestera"; |
| status = "okay"; |
| |
| base-mac-provider = <&eeprom_mac_addr>; |
| }; |
| |
| The current implementation of Prestera Switchdev PCI interface driver requires |
| that BAR2 is assigned to 0xf6000000 as base address from the PCI IO range: |
| |
| &cp0_pcie0 { |
| ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000 |
| 0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000 |
| 0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>; |
| phys = <&cp0_comphy0 0>; |
| status = "okay"; |
| }; |
