| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * This header provides constants for J721E WIZ. |
| */ |
| |
| #ifndef _DT_BINDINGS_J721E_WIZ |
| #define _DT_BINDINGS_J721E_WIZ |
| |
| #define SERDES0_LANE0_QSGMII_LANE1 0x0 |
| #define SERDES0_LANE0_PCIE0_LANE0 0x1 |
| #define SERDES0_LANE0_USB3_0_SWAP 0x2 |
| |
| #define SERDES0_LANE1_QSGMII_LANE2 0x0 |
| #define SERDES0_LANE1_PCIE0_LANE1 0x1 |
| #define SERDES0_LANE1_USB3_0 0x2 |
| |
| #define SERDES1_LANE0_QSGMII_LANE3 0x0 |
| #define SERDES1_LANE0_PCIE1_LANE0 0x1 |
| #define SERDES1_LANE0_USB3_1_SWAP 0x2 |
| #define SERDES1_LANE0_SGMII_LANE0 0x3 |
| |
| #define SERDES1_LANE1_QSGMII_LANE4 0x0 |
| #define SERDES1_LANE1_PCIE1_LANE1 0x1 |
| #define SERDES1_LANE1_USB3_1 0x2 |
| #define SERDES1_LANE1_SGMII_LANE1 0x3 |
| |
| #define SERDES2_LANE0_PCIE2_LANE0 0x1 |
| #define SERDES2_LANE0_SGMII_LANE0 0x3 |
| #define SERDES2_LANE0_USB3_1_SWAP 0x2 |
| |
| #define SERDES2_LANE1_PCIE2_LANE1 0x1 |
| #define SERDES2_LANE1_USB3_1 0x2 |
| #define SERDES2_LANE1_SGMII_LANE1 0x3 |
| |
| #define SERDES3_LANE0_PCIE3_LANE0 0x1 |
| #define SERDES3_LANE0_USB3_0_SWAP 0x2 |
| |
| #define SERDES3_LANE1_PCIE3_LANE1 0x1 |
| #define SERDES3_LANE1_USB3_0 0x2 |
| |
| #define SERDES4_LANE0_EDP_LANE0 0x0 |
| #define SERDES4_LANE0_QSGMII_LANE5 0x2 |
| |
| #define SERDES4_LANE1_EDP_LANE1 0x0 |
| #define SERDES4_LANE1_QSGMII_LANE6 0x2 |
| |
| #define SERDES4_LANE2_EDP_LANE2 0x0 |
| #define SERDES4_LANE2_QSGMII_LANE7 0x2 |
| |
| #define SERDES4_LANE3_EDP_LANE3 0x0 |
| #define SERDES4_LANE3_QSGMII_LANE8 0x2 |
| |
| #endif /* _DT_BINDINGS_J721E_WIZ */ |
