| [ |
| { |
| "PublicDescription": "Conditional branch", |
| "EventCode": "0x102", |
| "EventName": "cond_br", |
| "BriefDescription": "V3 Conditional branch" |
| }, |
| { |
| "PublicDescription": "Taken conditional branches", |
| "EventCode": "0x103", |
| "EventName": "taken_cond_br", |
| "BriefDescription": "V3 Taken Conditional branch" |
| }, |
| { |
| "PublicDescription": "Prefetch Instruction", |
| "EventCode": "0x104", |
| "EventName": "prefetch_inst", |
| "BriefDescription": "V3 Prefetch Instruction" |
| }, |
| { |
| "PublicDescription": "RET Inst", |
| "EventCode": "0x105", |
| "EventName": "ret_inst", |
| "BriefDescription": "V3 RET Inst" |
| }, |
| { |
| "PublicDescription": "JR(non-RET) instructions", |
| "EventCode": "0x106", |
| "EventName": "jr_inst", |
| "BriefDescription": "V3 JR(non-RET) instructions" |
| }, |
| { |
| "PublicDescription": "JAL/JRAL instructions", |
| "EventCode": "0x107", |
| "EventName": "jal_jral_inst", |
| "BriefDescription": "V3 JAL/JRAL instructions" |
| }, |
| { |
| "PublicDescription": "NOP instructions", |
| "EventCode": "0x108", |
| "EventName": "nop_inst", |
| "BriefDescription": "V3 NOP instructions" |
| }, |
| { |
| "PublicDescription": "SCW instructions", |
| "EventCode": "0x109", |
| "EventName": "scw_inst", |
| "BriefDescription": "V3 SCW instructions" |
| }, |
| { |
| "PublicDescription": "ISB/DSB instructions", |
| "EventCode": "0x10a", |
| "EventName": "isb_dsb_inst", |
| "BriefDescription": "V3 ISB/DSB instructions" |
| }, |
| { |
| "PublicDescription": "CCTL instructions", |
| "EventCode": "0x10b", |
| "EventName": "cctl_inst", |
| "BriefDescription": "V3 CCTL instructions" |
| }, |
| { |
| "PublicDescription": "Taken Interrupts", |
| "EventCode": "0x10c", |
| "EventName": "taken_interrupts", |
| "BriefDescription": "V3 Taken Interrupts" |
| }, |
| { |
| "PublicDescription": "Loads Completed", |
| "EventCode": "0x10d", |
| "EventName": "load_completed", |
| "BriefDescription": "V3 Loads Completed" |
| }, |
| { |
| "PublicDescription": "uITLB accesses", |
| "EventCode": "0x10e", |
| "EventName": "uitlb_access", |
| "BriefDescription": "V3 uITLB accesses" |
| }, |
| { |
| "PublicDescription": "uDTLB accesses", |
| "EventCode": "0x10f", |
| "EventName": "udtlb_access", |
| "BriefDescription": "V3 uDTLB accesses" |
| }, |
| { |
| "PublicDescription": "MTLB accesses", |
| "EventCode": "0x110", |
| "EventName": "mtlb_access", |
| "BriefDescription": "V3 MTLB accesses" |
| }, |
| { |
| "PublicDescription": "DATA_DEPENDENCY_STALL_CYCLES", |
| "EventCode": "0x112", |
| "EventName": "data_dependency_stall", |
| "BriefDescription": "V3 DATA_DEPENDENCY_STALL_CYCLES" |
| }, |
| { |
| "PublicDescription": "DATA_CACHE_MISS_STALL_CYCLES", |
| "EventCode": "0x113", |
| "EventName": "dcache_miss_stall", |
| "BriefDescription": "V3 DATA_CACHE_MISS_STALL_CYCLES" |
| }, |
| { |
| "PublicDescription": "ILM access", |
| "EventCode": "0x118", |
| "EventName": "ilm_access", |
| "BriefDescription": "V3 ILM accesses" |
| }, |
| { |
| "PublicDescription": "LSU BIU CYCLES", |
| "EventCode": "0x119", |
| "EventName": "lsu_biu_cycles", |
| "BriefDescription": "V3 LSU BIU CYCLES" |
| }, |
| { |
| "PublicDescription": "HPTWK BIU CYCLES", |
| "EventCode": "0x11a", |
| "EventName": "hptwk_biu_cycles", |
| "BriefDescription": "V3 HPTWK BIU CYCLES" |
| }, |
| { |
| "PublicDescription": "DMA BIU CYCLES", |
| "EventCode": "0x11b", |
| "EventName": "dma_biu_cycles", |
| "BriefDescription": "V3 DMA BIU CYCLES" |
| }, |
| { |
| "PublicDescription": "CODE CACHE FILL BIU CYCLES", |
| "EventCode": "0x11c", |
| "EventName": "icache_fill_biu_cycles", |
| "BriefDescription": "V3 CODE CACHE FILL BIU CYCLES" |
| }, |
| { |
| "PublicDescription": "LEAGAL UNALIGN DCACHE ACCESS", |
| "EventCode": "0x11d", |
| "EventName": "legal_unalined_dcache_access", |
| "BriefDescription": "V3 LEAGAL UNALIGN DCACHE ACCESS" |
| }, |
| { |
| "PublicDescription": "PUSH25 instructions", |
| "EventCode": "0x11e", |
| "EventName": "push25_inst", |
| "BriefDescription": "V3 PUSH25 instructions" |
| }, |
| { |
| "PublicDescription": "SYSCALL instructions", |
| "EventCode": "0x11f", |
| "EventName": "syscall_inst", |
| "BriefDescription": "V3 SYSCALL instructions" |
| }, |
| { |
| "PublicDescription": "conditional branch miss", |
| "EventCode": "0x202", |
| "EventName": "cond_br_miss", |
| "BriefDescription": "V3 conditional branch miss" |
| }, |
| { |
| "PublicDescription": "taken conditional branch miss", |
| "EventCode": "0x203", |
| "EventName": "taken_cond_br_miss", |
| "BriefDescription": "V3 taken conditional branch miss" |
| }, |
| { |
| "PublicDescription": "Prefetch Instructions with cache hit", |
| "EventCode": "0x204", |
| "EventName": "prefetch_icache_hit", |
| "BriefDescription": "V3 Prefetch Instructions with cache hit" |
| }, |
| { |
| "PublicDescription": "RET mispredict", |
| "EventCode": "0x205", |
| "EventName": "ret_mispredict", |
| "BriefDescription": "V3 RET mispredict" |
| }, |
| { |
| "PublicDescription": "Immediate J instructions", |
| "EventCode": "0x206", |
| "EventName": "imm_j_inst", |
| "BriefDescription": "V3 Immediate J instructions" |
| }, |
| { |
| "PublicDescription": "Multiply instructions", |
| "EventCode": "0x207", |
| "EventName": "mul_inst", |
| "BriefDescription": "V3 Multiply instructions" |
| }, |
| { |
| "PublicDescription": "16 bits instructions", |
| "EventCode": "0x208", |
| "EventName": "sixteen_bits_inst", |
| "BriefDescription": "V3 16 bits instructions" |
| }, |
| { |
| "PublicDescription": "Failed SCW instructions", |
| "EventCode": "0x209", |
| "EventName": "fail_scw_inst", |
| "BriefDescription": "V3 Failed SCW instructions" |
| }, |
| { |
| "PublicDescription": "ld-after-st conflict replays", |
| "EventCode": "0x20a", |
| "EventName": "ld_af_st_conflict", |
| "BriefDescription": "V3 ld-after-st conflict replays" |
| }, |
| { |
| "PublicDescription": "Exception taken", |
| "EventCode": "0x20c", |
| "EventName": "exception_taken", |
| "BriefDescription": "V3 Exception taken" |
| }, |
| { |
| "PublicDescription": "Stores completed", |
| "EventCode": "0x20d", |
| "EventName": "store_completed", |
| "BriefDescription": "V3 Stores completed" |
| }, |
| { |
| "PublicDescription": "uITLB miss", |
| "EventCode": "0x20e", |
| "EventName": "uitlb_miss", |
| "BriefDescription": "V3 uITLB miss" |
| }, |
| { |
| "PublicDescription": "uDTLB miss", |
| "EventCode": "0x20f", |
| "EventName": "udtlb_miss", |
| "BriefDescription": "V3 uDTLB miss" |
| }, |
| { |
| "PublicDescription": "MTLB miss", |
| "EventCode": "0x210", |
| "EventName": "mtlb_miss", |
| "BriefDescription": "V3 MTLB miss" |
| }, |
| { |
| "PublicDescription": "Empty instructions queue stall cycles", |
| "EventCode": "0x212", |
| "EventName": "empty_inst_q_stall", |
| "BriefDescription": "V3 Empty instructions queue stall cycles" |
| }, |
| { |
| "PublicDescription": "Data write back", |
| "EventCode": "0x213", |
| "EventName": "data_wb", |
| "BriefDescription": "V3 Data write back" |
| }, |
| { |
| "PublicDescription": "DLM access", |
| "EventCode": "0x218", |
| "EventName": "dlm_access", |
| "BriefDescription": "V3 DLM access" |
| }, |
| { |
| "PublicDescription": "LSU BIU request", |
| "EventCode": "0x219", |
| "EventName": "lsu_biu_req", |
| "BriefDescription": "V3 LSU BIU request" |
| }, |
| { |
| "PublicDescription": "HPTWK BIU request", |
| "EventCode": "0x21a", |
| "EventName": "hptwk_biu_req", |
| "BriefDescription": "V3 HPTWK BIU request" |
| }, |
| { |
| "PublicDescription": "DMA BIU request", |
| "EventCode": "0x21b", |
| "EventName": "dma_biu_req", |
| "BriefDescription": "V3 DMA BIU request" |
| }, |
| { |
| "PublicDescription": "Icache fill BIU request", |
| "EventCode": "0x21c", |
| "EventName": "icache_fill_biu_req", |
| "BriefDescription": "V3 Icache fill BIU request" |
| }, |
| { |
| "PublicDescription": "External events", |
| "EventCode": "0x21d", |
| "EventName": "external_events", |
| "BriefDescription": "V3 External events" |
| }, |
| { |
| "PublicDescription": "POP25 instructions", |
| "EventCode": "0x21e", |
| "EventName": "pop25_inst", |
| "BriefDescription": "V3 POP25 instructions" |
| }, |
| ] |
