| # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: CoreSight CPU Debug Component |
| |
| maintainers: |
| - Mathieu Poirier <mathieu.poirier@linaro.org> |
| - Mike Leach <mike.leach@linaro.org> |
| - Leo Yan <leo.yan@linaro.org> |
| - Suzuki K Poulose <suzuki.poulose@arm.com> |
| |
| description: | |
| CoreSight CPU debug component are compliant with the ARMv8 architecture |
| reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The |
| external debug module is mainly used for two modes: self-hosted debug and |
| external debug, and it can be accessed from mmio region from Coresight and |
| eventually the debug module connects with CPU for debugging. And the debug |
| module provides sample-based profiling extension, which can be used to sample |
| CPU program counter, secure state and exception level, etc; usually every CPU |
| has one dedicated debug module to be connected. |
| |
| select: |
| properties: |
| compatible: |
| contains: |
| const: arm,coresight-cpu-debug |
| required: |
| - compatible |
| |
| allOf: |
| - $ref: /schemas/arm/primecell.yaml# |
| |
| properties: |
| compatible: |
| items: |
| - const: arm,coresight-cpu-debug |
| - const: arm,primecell |
| |
| reg: |
| maxItems: 1 |
| |
| clocks: |
| maxItems: 1 |
| |
| clock-names: |
| maxItems: 1 |
| |
| cpu: |
| description: |
| A phandle to the cpu this debug component is bound to. |
| $ref: /schemas/types.yaml#/definitions/phandle |
| |
| power-domains: |
| maxItems: 1 |
| description: |
| A phandle to the debug power domain if the debug logic has its own |
| dedicated power domain. CPU idle states may also need to be separately |
| constrained to keep CPU cores powered. |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - clock-names |
| - cpu |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| debug@f6590000 { |
| compatible = "arm,coresight-cpu-debug", "arm,primecell"; |
| reg = <0xf6590000 0x1000>; |
| clocks = <&sys_ctrl 1>; |
| clock-names = "apb_pclk"; |
| cpu = <&cpu0>; |
| }; |
| ... |