| # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Arm CoreSight Trace Port Interface Unit |
| |
| maintainers: |
| - Mathieu Poirier <mathieu.poirier@linaro.org> |
| - Mike Leach <mike.leach@linaro.org> |
| - Leo Yan <leo.yan@linaro.org> |
| - Suzuki K Poulose <suzuki.poulose@arm.com> |
| |
| description: | |
| CoreSight components are compliant with the ARM CoreSight architecture |
| specification and can be connected in various topologies to suit a particular |
| SoCs tracing needs. These trace components can generally be classified as |
| sinks, links and sources. Trace data produced by one or more sources flows |
| through the intermediate links connecting the source to the currently selected |
| sink. |
| |
| The CoreSight Trace Port Interface Unit captures trace data from the trace bus |
| and outputs it to an external trace port. |
| |
| # Need a custom select here or 'arm,primecell' will match on lots of nodes |
| select: |
| properties: |
| compatible: |
| contains: |
| const: arm,coresight-tpiu |
| required: |
| - compatible |
| |
| allOf: |
| - $ref: /schemas/arm/primecell.yaml# |
| |
| properties: |
| compatible: |
| items: |
| - const: arm,coresight-tpiu |
| - const: arm,primecell |
| |
| reg: |
| maxItems: 1 |
| |
| clocks: |
| minItems: 1 |
| maxItems: 2 |
| |
| clock-names: |
| minItems: 1 |
| items: |
| - const: apb_pclk |
| - const: atclk |
| |
| power-domains: |
| maxItems: 1 |
| |
| in-ports: |
| $ref: /schemas/graph.yaml#/properties/ports |
| additionalProperties: false |
| |
| properties: |
| port: |
| description: Input connection from the CoreSight Trace bus. |
| $ref: /schemas/graph.yaml#/properties/port |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - clock-names |
| - in-ports |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| tpiu@e3c05000 { |
| compatible = "arm,coresight-tpiu", "arm,primecell"; |
| reg = <0xe3c05000 0x1000>; |
| |
| clocks = <&clk_375m>; |
| clock-names = "apb_pclk"; |
| in-ports { |
| port { |
| tpiu_in_port: endpoint { |
| remote-endpoint = <&funnel4_out_port0>; |
| }; |
| }; |
| }; |
| }; |
| ... |