Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MIPS CPU Interrupt Controller

description: >
   On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
   IRQs from a devicetree file and create a irq_domain for IRQ controller.

   With the irq_domain in place we can describe how the 8 IRQs are wired to the
   platforms internal interrupt controller cascade.

maintainers:
  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>

properties:
  compatible:
    const: mti,cpu-interrupt-controller

  '#interrupt-cells':
    const: 1

  '#address-cells':
    const: 0

  interrupt-controller: true

additionalProperties: false

required:
  - compatible
  - '#interrupt-cells'
  - '#address-cells'
  - interrupt-controller

examples:
  - |
    interrupt-controller {
      compatible = "mti,cpu-interrupt-controller";
      #address-cells = <0>;
      #interrupt-cells = <1>;
      interrupt-controller;
    };