| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_MME6_RTR_REGS_H_ |
| #define ASIC_REG_MME6_RTR_REGS_H_ |
| |
| /* |
| ***************************************** |
| * MME6_RTR (Prototype: MME_RTR) |
| ***************************************** |
| */ |
| |
| #define mmMME6_RTR_HBW_RD_RQ_E_ARB 0x180100 |
| |
| #define mmMME6_RTR_HBW_RD_RQ_W_ARB 0x180104 |
| |
| #define mmMME6_RTR_HBW_RD_RQ_N_ARB 0x180108 |
| |
| #define mmMME6_RTR_HBW_RD_RQ_S_ARB 0x18010C |
| |
| #define mmMME6_RTR_HBW_RD_RQ_L_ARB 0x180110 |
| |
| #define mmMME6_RTR_HBW_E_ARB_MAX 0x180120 |
| |
| #define mmMME6_RTR_HBW_W_ARB_MAX 0x180124 |
| |
| #define mmMME6_RTR_HBW_N_ARB_MAX 0x180128 |
| |
| #define mmMME6_RTR_HBW_S_ARB_MAX 0x18012C |
| |
| #define mmMME6_RTR_HBW_L_ARB_MAX 0x180130 |
| |
| #define mmMME6_RTR_HBW_RD_RS_MAX_CREDIT 0x180140 |
| |
| #define mmMME6_RTR_HBW_WR_RQ_MAX_CREDIT 0x180144 |
| |
| #define mmMME6_RTR_HBW_RD_RQ_MAX_CREDIT 0x180148 |
| |
| #define mmMME6_RTR_HBW_RD_RS_E_ARB 0x180150 |
| |
| #define mmMME6_RTR_HBW_RD_RS_W_ARB 0x180154 |
| |
| #define mmMME6_RTR_HBW_RD_RS_N_ARB 0x180158 |
| |
| #define mmMME6_RTR_HBW_RD_RS_S_ARB 0x18015C |
| |
| #define mmMME6_RTR_HBW_RD_RS_L_ARB 0x180160 |
| |
| #define mmMME6_RTR_HBW_WR_RQ_E_ARB 0x180170 |
| |
| #define mmMME6_RTR_HBW_WR_RQ_W_ARB 0x180174 |
| |
| #define mmMME6_RTR_HBW_WR_RQ_N_ARB 0x180178 |
| |
| #define mmMME6_RTR_HBW_WR_RQ_S_ARB 0x18017C |
| |
| #define mmMME6_RTR_HBW_WR_RQ_L_ARB 0x180180 |
| |
| #define mmMME6_RTR_HBW_WR_RS_E_ARB 0x180190 |
| |
| #define mmMME6_RTR_HBW_WR_RS_W_ARB 0x180194 |
| |
| #define mmMME6_RTR_HBW_WR_RS_N_ARB 0x180198 |
| |
| #define mmMME6_RTR_HBW_WR_RS_S_ARB 0x18019C |
| |
| #define mmMME6_RTR_HBW_WR_RS_L_ARB 0x1801A0 |
| |
| #define mmMME6_RTR_LBW_RD_RQ_E_ARB 0x180200 |
| |
| #define mmMME6_RTR_LBW_RD_RQ_W_ARB 0x180204 |
| |
| #define mmMME6_RTR_LBW_RD_RQ_N_ARB 0x180208 |
| |
| #define mmMME6_RTR_LBW_RD_RQ_S_ARB 0x18020C |
| |
| #define mmMME6_RTR_LBW_RD_RQ_L_ARB 0x180210 |
| |
| #define mmMME6_RTR_LBW_E_ARB_MAX 0x180220 |
| |
| #define mmMME6_RTR_LBW_W_ARB_MAX 0x180224 |
| |
| #define mmMME6_RTR_LBW_N_ARB_MAX 0x180228 |
| |
| #define mmMME6_RTR_LBW_S_ARB_MAX 0x18022C |
| |
| #define mmMME6_RTR_LBW_L_ARB_MAX 0x180230 |
| |
| #define mmMME6_RTR_LBW_SRAM_MAX_CREDIT 0x180240 |
| |
| #define mmMME6_RTR_LBW_RD_RS_E_ARB 0x180250 |
| |
| #define mmMME6_RTR_LBW_RD_RS_W_ARB 0x180254 |
| |
| #define mmMME6_RTR_LBW_RD_RS_N_ARB 0x180258 |
| |
| #define mmMME6_RTR_LBW_RD_RS_S_ARB 0x18025C |
| |
| #define mmMME6_RTR_LBW_RD_RS_L_ARB 0x180260 |
| |
| #define mmMME6_RTR_LBW_WR_RQ_E_ARB 0x180270 |
| |
| #define mmMME6_RTR_LBW_WR_RQ_W_ARB 0x180274 |
| |
| #define mmMME6_RTR_LBW_WR_RQ_N_ARB 0x180278 |
| |
| #define mmMME6_RTR_LBW_WR_RQ_S_ARB 0x18027C |
| |
| #define mmMME6_RTR_LBW_WR_RQ_L_ARB 0x180280 |
| |
| #define mmMME6_RTR_LBW_WR_RS_E_ARB 0x180290 |
| |
| #define mmMME6_RTR_LBW_WR_RS_W_ARB 0x180294 |
| |
| #define mmMME6_RTR_LBW_WR_RS_N_ARB 0x180298 |
| |
| #define mmMME6_RTR_LBW_WR_RS_S_ARB 0x18029C |
| |
| #define mmMME6_RTR_LBW_WR_RS_L_ARB 0x1802A0 |
| |
| #define mmMME6_RTR_DBG_E_ARB 0x180300 |
| |
| #define mmMME6_RTR_DBG_W_ARB 0x180304 |
| |
| #define mmMME6_RTR_DBG_N_ARB 0x180308 |
| |
| #define mmMME6_RTR_DBG_S_ARB 0x18030C |
| |
| #define mmMME6_RTR_DBG_L_ARB 0x180310 |
| |
| #define mmMME6_RTR_DBG_E_ARB_MAX 0x180320 |
| |
| #define mmMME6_RTR_DBG_W_ARB_MAX 0x180324 |
| |
| #define mmMME6_RTR_DBG_N_ARB_MAX 0x180328 |
| |
| #define mmMME6_RTR_DBG_S_ARB_MAX 0x18032C |
| |
| #define mmMME6_RTR_DBG_L_ARB_MAX 0x180330 |
| |
| #define mmMME6_RTR_SPLIT_COEF_0 0x180400 |
| |
| #define mmMME6_RTR_SPLIT_COEF_1 0x180404 |
| |
| #define mmMME6_RTR_SPLIT_COEF_2 0x180408 |
| |
| #define mmMME6_RTR_SPLIT_COEF_3 0x18040C |
| |
| #define mmMME6_RTR_SPLIT_COEF_4 0x180410 |
| |
| #define mmMME6_RTR_SPLIT_COEF_5 0x180414 |
| |
| #define mmMME6_RTR_SPLIT_COEF_6 0x180418 |
| |
| #define mmMME6_RTR_SPLIT_COEF_7 0x18041C |
| |
| #define mmMME6_RTR_SPLIT_COEF_8 0x180420 |
| |
| #define mmMME6_RTR_SPLIT_COEF_9 0x180424 |
| |
| #define mmMME6_RTR_SPLIT_CFG 0x180440 |
| |
| #define mmMME6_RTR_SPLIT_RD_SAT 0x180444 |
| |
| #define mmMME6_RTR_SPLIT_RD_RST_TOKEN 0x180448 |
| |
| #define mmMME6_RTR_SPLIT_RD_TIMEOUT_0 0x18044C |
| |
| #define mmMME6_RTR_SPLIT_RD_TIMEOUT_1 0x180450 |
| |
| #define mmMME6_RTR_SPLIT_WR_SAT 0x180454 |
| |
| #define mmMME6_RTR_WPLIT_WR_TST_TOLEN 0x180458 |
| |
| #define mmMME6_RTR_SPLIT_WR_TIMEOUT_0 0x18045C |
| |
| #define mmMME6_RTR_SPLIT_WR_TIMEOUT_1 0x180460 |
| |
| #define mmMME6_RTR_HBW_RANGE_HIT 0x180470 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_L_0 0x180480 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_L_1 0x180484 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_L_2 0x180488 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_L_3 0x18048C |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_L_4 0x180490 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_L_5 0x180494 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_L_6 0x180498 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_L_7 0x18049C |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_H_0 0x1804A0 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_H_1 0x1804A4 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_H_2 0x1804A8 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_H_3 0x1804AC |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_H_4 0x1804B0 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_H_5 0x1804B4 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_H_6 0x1804B8 |
| |
| #define mmMME6_RTR_HBW_RANGE_MASK_H_7 0x1804BC |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_L_0 0x1804C0 |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_L_1 0x1804C4 |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_L_2 0x1804C8 |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_L_3 0x1804CC |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_L_4 0x1804D0 |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_L_5 0x1804D4 |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_L_6 0x1804D8 |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_L_7 0x1804DC |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_H_0 0x1804E0 |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_H_1 0x1804E4 |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_H_2 0x1804E8 |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_H_3 0x1804EC |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_H_4 0x1804F0 |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_H_5 0x1804F4 |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_H_6 0x1804F8 |
| |
| #define mmMME6_RTR_HBW_RANGE_BASE_H_7 0x1804FC |
| |
| #define mmMME6_RTR_LBW_RANGE_HIT 0x180500 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_0 0x180510 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_1 0x180514 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_2 0x180518 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_3 0x18051C |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_4 0x180520 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_5 0x180524 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_6 0x180528 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_7 0x18052C |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_8 0x180530 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_9 0x180534 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_10 0x180538 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_11 0x18053C |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_12 0x180540 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_13 0x180544 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_14 0x180548 |
| |
| #define mmMME6_RTR_LBW_RANGE_MASK_15 0x18054C |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_0 0x180550 |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_1 0x180554 |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_2 0x180558 |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_3 0x18055C |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_4 0x180560 |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_5 0x180564 |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_6 0x180568 |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_7 0x18056C |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_8 0x180570 |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_9 0x180574 |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_10 0x180578 |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_11 0x18057C |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_12 0x180580 |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_13 0x180584 |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_14 0x180588 |
| |
| #define mmMME6_RTR_LBW_RANGE_BASE_15 0x18058C |
| |
| #define mmMME6_RTR_RGLTR 0x180590 |
| |
| #define mmMME6_RTR_RGLTR_WR_RESULT 0x180594 |
| |
| #define mmMME6_RTR_RGLTR_RD_RESULT 0x180598 |
| |
| #define mmMME6_RTR_SCRAMB_EN 0x180600 |
| |
| #define mmMME6_RTR_NON_LIN_SCRAMB 0x180604 |
| |
| #endif /* ASIC_REG_MME6_RTR_REGS_H_ */ |
