| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/timer/cdns,ttc.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Cadence TTC - Triple Timer Counter |
| |
| maintainers: |
| - Michal Simek <michal.simek@amd.com> |
| |
| properties: |
| compatible: |
| const: cdns,ttc |
| |
| reg: |
| maxItems: 1 |
| |
| interrupts: |
| maxItems: 3 |
| description: | |
| A list of 3 interrupts; one per timer channel. |
| |
| clocks: |
| maxItems: 1 |
| |
| power-domains: |
| maxItems: 1 |
| |
| timer-width: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Bit width of the timer, necessary if not 16. |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - clocks |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| ttc0: ttc0@f8001000 { |
| interrupt-parent = <&intc>; |
| interrupts = <0 10 4>, <0 11 4>, <0 12 4>; |
| compatible = "cdns,ttc"; |
| reg = <0xF8001000 0x1000>; |
| clocks = <&cpu_clk 3>; |
| timer-width = <32>; |
| }; |