arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada AP806.
 */

#include "armada-ap806.dtsi"

/ {
	model = "Marvell Armada AP806 Dual";
	compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x000>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 0>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x001>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 0>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2>;
		};

		l2: l2-cache {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-level = <2>;
			cache-unified;
		};
	};

	thermal-zones {
		/delete-node/ ap-thermal-cpu2;
		/delete-node/ ap-thermal-cpu3;
	};
};