| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Device Tree file for Marvell Armada 375 evaluation board |
| * (DB-88F6720) |
| * |
| * Copyright (C) 2014 Marvell |
| * |
| * Gregory CLEMENT <gregory.clement@free-electrons.com> |
| * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| */ |
| |
| /dts-v1/; |
| #include <dt-bindings/gpio/gpio.h> |
| #include "armada-375.dtsi" |
| |
| / { |
| model = "Marvell Armada 375 Development Board"; |
| compatible = "marvell,a375-db", "marvell,armada375"; |
| |
| chosen { |
| stdout-path = "serial0:115200n8"; |
| }; |
| |
| memory@0 { |
| device_type = "memory"; |
| reg = <0x00000000 0x40000000>; /* 1 GB */ |
| }; |
| |
| soc { |
| ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 |
| MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 |
| MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000 |
| MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>; |
| |
| }; |
| }; |
| &pciec { |
| status = "okay"; |
| }; |
| |
| /* |
| * The two PCIe units are accessible through |
| * standard PCIe slots on the board. |
| */ |
| &pcie0 { |
| /* Port 0, Lane 0 */ |
| status = "okay"; |
| }; |
| |
| &pcie1 { |
| /* Port 1, Lane 0 */ |
| status = "okay"; |
| }; |
| |
| |
| &spi0 { |
| pinctrl-0 = <&spi0_pins>; |
| pinctrl-names = "default"; |
| |
| /* |
| * SPI conflicts with NAND, so we disable it here, and |
| * select NAND as the enabled device by default. |
| */ |
| |
| status = "disabled"; |
| |
| flash@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "n25q128a13", "jedec,spi-nor"; |
| reg = <0>; /* Chip select 0 */ |
| spi-max-frequency = <108000000>; |
| }; |
| }; |
| |
| &i2c0 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| pinctrl-0 = <&i2c0_pins>; |
| pinctrl-names = "default"; |
| }; |
| |
| &i2c1 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| pinctrl-0 = <&i2c1_pins>; |
| pinctrl-names = "default"; |
| }; |
| |
| &uart0 { |
| status = "okay"; |
| }; |
| |
| &pinctrl { |
| sdio_st_pins: sdio-st-pins { |
| marvell,pins = "mpp44", "mpp45"; |
| marvell,function = "gpio"; |
| }; |
| }; |
| |
| &sata { |
| status = "okay"; |
| nr-ports = <2>; |
| }; |
| |
| &nand_controller { |
| status = "okay"; |
| pinctrl-0 = <&nand_pins>; |
| pinctrl-names = "default"; |
| |
| nand@0 { |
| reg = <0>; |
| label = "pxa3xx_nand-0"; |
| nand-rb = <0>; |
| marvell,nand-keep-config; |
| nand-on-flash-bbt; |
| nand-ecc-strength = <4>; |
| nand-ecc-step-size = <512>; |
| |
| partitions { |
| compatible = "fixed-partitions"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| partition@0 { |
| label = "U-Boot"; |
| reg = <0 0x800000>; |
| }; |
| partition@800000 { |
| label = "Linux"; |
| reg = <0x800000 0x800000>; |
| }; |
| partition@1000000 { |
| label = "Filesystem"; |
| reg = <0x1000000 0x3f000000>; |
| }; |
| }; |
| }; |
| }; |
| |
| &usb1 { |
| status = "okay"; |
| }; |
| |
| &usb2 { |
| status = "okay"; |
| }; |
| |
| &sdio { |
| pinctrl-0 = <&sdio_pins &sdio_st_pins>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; |
| wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| &mdio { |
| phy0: ethernet-phy@0 { |
| reg = <0>; |
| }; |
| |
| phy3: ethernet-phy@3 { |
| reg = <3>; |
| }; |
| }; |
| |
| ðernet { |
| status = "okay"; |
| }; |
| |
| |
| ð0 { |
| status = "okay"; |
| phy = <&phy0>; |
| phy-mode = "rgmii-id"; |
| }; |
| |
| ð1 { |
| status = "okay"; |
| phy = <&phy3>; |
| phy-mode = "gmii"; |
| }; |