| /* |
| * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| */ |
| |
| |
| #ifndef _cl907d_h_ |
| #define _cl907d_h_ |
| |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 |
| #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:27 |
| |
| |
| // class methods |
| #define NV907D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) |
| #define NV907D_DAC_SET_CONTROL_OWNER_MASK 3:0 |
| #define NV907D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) |
| #define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) |
| #define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) |
| #define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) |
| #define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) |
| #define NV907D_DAC_SET_CONTROL_PROTOCOL 12:8 |
| #define NV907D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) |
| #define NV907D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) |
| |
| #define NV907D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) |
| #define NV907D_SOR_SET_CONTROL_OWNER_MASK 3:0 |
| #define NV907D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) |
| #define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) |
| #define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) |
| #define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) |
| #define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) |
| #define NV907D_SOR_SET_CONTROL_PROTOCOL 11:8 |
| #define NV907D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) |
| #define NV907D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) |
| #define NV907D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) |
| #define NV907D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) |
| #define NV907D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) |
| #define NV907D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) |
| #define NV907D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) |
| #define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 |
| #define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) |
| #define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) |
| #define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 |
| #define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) |
| #define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) |
| #define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) |
| |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) |
| #define NV907D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_CONTROL_STRUCTURE 0:0 |
| #define NV907D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) |
| #define NV907D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) |
| #define NV907D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 |
| #define NV907D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 |
| #define NV907D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 |
| #define NV907D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 |
| #define NV907D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 |
| #define NV907D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_RASTER_SYNC_END_X 14:0 |
| #define NV907D_HEAD_SET_RASTER_SYNC_END_Y 30:16 |
| #define NV907D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) |
| #define NV907D_HEAD_SET_RASTER_BLANK_END_X 14:0 |
| #define NV907D_HEAD_SET_RASTER_BLANK_END_Y 30:16 |
| #define NV907D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_RASTER_BLANK_START_X 14:0 |
| #define NV907D_HEAD_SET_RASTER_BLANK_START_Y 30:16 |
| #define NV907D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 |
| #define NV907D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 |
| #define NV907D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) |
| #define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 |
| #define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 |
| #define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 |
| #define NV907D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 |
| #define NV907D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) |
| #define NV907D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) |
| #define NV907D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) |
| #define NV907D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 |
| #define NV907D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) |
| #define NV907D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) |
| #define NV907D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 |
| #define NV907D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) |
| #define NV907D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) |
| #define NV907D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 |
| #define NV907D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) |
| #define NV907D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) |
| #define NV907D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) |
| #define NV907D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) |
| #define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) |
| #define NV907D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) |
| #define NV907D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 |
| #define NV907D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_OFFSET_ORIGIN 31:0 |
| #define NV907D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_SIZE_WIDTH 15:0 |
| #define NV907D_HEAD_SET_SIZE_HEIGHT 31:16 |
| #define NV907D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) |
| #define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 |
| #define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) |
| #define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) |
| #define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) |
| #define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) |
| #define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) |
| #define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) |
| #define NV907D_HEAD_SET_STORAGE_PITCH 20:8 |
| #define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 |
| #define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) |
| #define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) |
| #define NV907D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_PARAMS_FORMAT 15:8 |
| #define NV907D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) |
| #define NV907D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) |
| #define NV907D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) |
| #define NV907D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) |
| #define NV907D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) |
| #define NV907D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) |
| #define NV907D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) |
| #define NV907D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) |
| #define NV907D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) |
| #define NV907D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) |
| #define NV907D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) |
| #define NV907D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) |
| #define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 |
| #define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) |
| #define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) |
| #define NV907D_HEAD_SET_PARAMS_GAMMA 2:2 |
| #define NV907D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) |
| #define NV907D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) |
| #define NV907D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 |
| #define NV907D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26 |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8 |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16 |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) |
| #define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) |
| #define NV907D_HEAD_SET_OFFSET_CURSOR(a) (0x00000484 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 |
| #define NV907D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000048C + (a)*0x00000300) |
| #define NV907D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 |
| #define NV907D_HEAD_SET_DITHER_CONTROL(a) (0x00000490 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 |
| #define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) |
| #define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) |
| #define NV907D_HEAD_SET_DITHER_CONTROL_BITS 2:1 |
| #define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) |
| #define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) |
| #define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) |
| #define NV907D_HEAD_SET_DITHER_CONTROL_MODE 6:3 |
| #define NV907D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) |
| #define NV907D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) |
| #define NV907D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) |
| #define NV907D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) |
| #define NV907D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) |
| #define NV907D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 |
| #define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 |
| #define NV907D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 |
| #define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) |
| #define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) |
| #define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) |
| #define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 |
| #define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) |
| #define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) |
| #define NV907D_HEAD_SET_PROCAMP_SAT_COS 19:8 |
| #define NV907D_HEAD_SET_PROCAMP_SAT_SINE 31:20 |
| #define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 |
| #define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) |
| #define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) |
| #define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 |
| #define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) |
| #define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) |
| #define NV907D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 |
| #define NV907D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 |
| #define NV907D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 |
| #define NV907D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 |
| #define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 |
| #define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 |
| #define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 |
| #define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 |
| #define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 |
| #define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 |
| #define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 |
| #define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) |
| #define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) |
| #define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 |
| #define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) |
| #define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) |
| #define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) |
| #define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) |
| #define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 |
| #define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) |
| #define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) |
| #define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) |
| #define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 |
| #define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) |
| #define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) |
| #define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 |
| #define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) |
| #define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) |
| #define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) |
| #endif // _cl907d_h |
