| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_TPC0_CFG_REGS_H_ |
| #define ASIC_REG_TPC0_CFG_REGS_H_ |
| |
| /* |
| ***************************************** |
| * TPC0_CFG (Prototype: TPC) |
| ***************************************** |
| */ |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE06400 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE06404 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE06408 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE0640C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE06410 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE06414 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE06418 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE0641C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE06420 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE06424 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE06428 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE0642C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE06430 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE06434 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE06438 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE0643C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE06440 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE06444 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE06448 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE0644C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE06450 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE06454 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE06458 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE0645C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE06460 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE06464 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE06468 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE0646C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE06470 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE06474 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE06478 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE0647C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE06480 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE06484 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE06488 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE0648C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE06490 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE06494 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE06498 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE0649C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE064A0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE064A4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE064A8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE064AC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE064B0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE064B4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE064B8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE064BC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE064C0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE064C4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE064C8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE064CC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE064D0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE064D4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE064D8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE064DC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE064E0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE064E4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE064E8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE064EC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE064F0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE064F4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE064F8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE064FC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE06500 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE06504 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE06508 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE0650C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE06510 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE06514 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE06518 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE0651C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE06520 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE06524 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE06528 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE0652C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE06530 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE06534 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE06538 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE0653C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE06540 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE06544 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE06548 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE0654C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE06550 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE06554 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE06558 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE0655C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE06560 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE06564 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE06568 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE0656C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE06570 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE06574 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE06578 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE0657C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE06580 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE06584 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE06588 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE0658C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE06590 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE06594 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE06598 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE0659C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE065A0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE065A4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE065A8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE065AC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE065B0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE065B4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE065B8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE065BC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE065C0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE065C4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE065C8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE065CC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE065D0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE065D4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE065D8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE065DC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE065E0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE065E4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE065E8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE065EC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE065F0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE065F4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE065F8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE065FC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE06600 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE06604 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE06608 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE0660C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE06610 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE06614 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE06618 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE0661C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE06620 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE06624 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE06628 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE0662C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE06630 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE06634 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE06638 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE0663C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE06640 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE06644 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE06648 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE0664C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE06650 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE06654 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE06658 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE0665C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE06660 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE06664 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE06668 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE0666C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE06670 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE06674 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE06678 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE0667C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE06680 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE06684 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE06688 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE0668C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE06690 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE06694 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE06698 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE0669C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE066A0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE066A4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE066A8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE066AC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE066B0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE066B4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE066B8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE066BC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE066C0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE066C4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE066C8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE066CC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE066D0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE066D4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE066D8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE066DC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE066E0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE066E4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE066E8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE066EC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE066F0 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE066F4 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE066F8 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE066FC |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE06700 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE06704 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE06708 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE0670C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE06710 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE06714 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE06718 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE0671C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE06720 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE06724 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE06728 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE0672C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE06730 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE06734 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE06738 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE0673C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE06740 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE06744 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE06748 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE0674C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE06750 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE06754 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE06758 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE0675C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE06760 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE06764 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE06768 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE0676C |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE06770 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE06774 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE06778 |
| |
| #define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE0677C |
| |
| #define mmTPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE06780 |
| |
| #define mmTPC0_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE06784 |
| |
| #define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE06788 |
| |
| #define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE0678C |
| |
| #define mmTPC0_CFG_KERNEL_TID_BASE_DIM_0 0xE06790 |
| |
| #define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_0 0xE06794 |
| |
| #define mmTPC0_CFG_KERNEL_TID_BASE_DIM_1 0xE06798 |
| |
| #define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_1 0xE0679C |
| |
| #define mmTPC0_CFG_KERNEL_TID_BASE_DIM_2 0xE067A0 |
| |
| #define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_2 0xE067A4 |
| |
| #define mmTPC0_CFG_KERNEL_TID_BASE_DIM_3 0xE067A8 |
| |
| #define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_3 0xE067AC |
| |
| #define mmTPC0_CFG_KERNEL_TID_BASE_DIM_4 0xE067B0 |
| |
| #define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_4 0xE067B4 |
| |
| #define mmTPC0_CFG_KERNEL_KERNEL_CONFIG 0xE067B8 |
| |
| #define mmTPC0_CFG_KERNEL_KERNEL_ID 0xE067BC |
| |
| #define mmTPC0_CFG_KERNEL_SRF_0 0xE067C0 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_1 0xE067C4 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_2 0xE067C8 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_3 0xE067CC |
| |
| #define mmTPC0_CFG_KERNEL_SRF_4 0xE067D0 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_5 0xE067D4 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_6 0xE067D8 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_7 0xE067DC |
| |
| #define mmTPC0_CFG_KERNEL_SRF_8 0xE067E0 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_9 0xE067E4 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_10 0xE067E8 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_11 0xE067EC |
| |
| #define mmTPC0_CFG_KERNEL_SRF_12 0xE067F0 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_13 0xE067F4 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_14 0xE067F8 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_15 0xE067FC |
| |
| #define mmTPC0_CFG_KERNEL_SRF_16 0xE06800 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_17 0xE06804 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_18 0xE06808 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_19 0xE0680C |
| |
| #define mmTPC0_CFG_KERNEL_SRF_20 0xE06810 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_21 0xE06814 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_22 0xE06818 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_23 0xE0681C |
| |
| #define mmTPC0_CFG_KERNEL_SRF_24 0xE06820 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_25 0xE06824 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_26 0xE06828 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_27 0xE0682C |
| |
| #define mmTPC0_CFG_KERNEL_SRF_28 0xE06830 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_29 0xE06834 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_30 0xE06838 |
| |
| #define mmTPC0_CFG_KERNEL_SRF_31 0xE0683C |
| |
| #define mmTPC0_CFG_ROUND_CSR 0xE068FC |
| |
| #define mmTPC0_CFG_PROT 0xE06900 |
| |
| #define mmTPC0_CFG_SEMAPHORE 0xE06908 |
| |
| #define mmTPC0_CFG_VFLAGS 0xE0690C |
| |
| #define mmTPC0_CFG_SFLAGS 0xE06910 |
| |
| #define mmTPC0_CFG_LFSR_POLYNOM 0xE06918 |
| |
| #define mmTPC0_CFG_STATUS 0xE0691C |
| |
| #define mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH 0xE06920 |
| |
| #define mmTPC0_CFG_CFG_SUBTRACT_VALUE 0xE06924 |
| |
| #define mmTPC0_CFG_SM_BASE_ADDRESS_HIGH 0xE0692C |
| |
| #define mmTPC0_CFG_TPC_CMD 0xE06930 |
| |
| #define mmTPC0_CFG_TPC_EXECUTE 0xE06938 |
| |
| #define mmTPC0_CFG_TPC_STALL 0xE0693C |
| |
| #define mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0xE06940 |
| |
| #define mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE06944 |
| |
| #define mmTPC0_CFG_RD_RATE_LIMIT 0xE06948 |
| |
| #define mmTPC0_CFG_WR_RATE_LIMIT 0xE06950 |
| |
| #define mmTPC0_CFG_MSS_CONFIG 0xE06954 |
| |
| #define mmTPC0_CFG_TPC_INTR_CAUSE 0xE06958 |
| |
| #define mmTPC0_CFG_TPC_INTR_MASK 0xE0695C |
| |
| #define mmTPC0_CFG_WQ_CREDITS 0xE06960 |
| |
| #define mmTPC0_CFG_ARUSER_LO 0xE06964 |
| |
| #define mmTPC0_CFG_ARUSER_HI 0xE06968 |
| |
| #define mmTPC0_CFG_AWUSER_LO 0xE0696C |
| |
| #define mmTPC0_CFG_AWUSER_HI 0xE06970 |
| |
| #define mmTPC0_CFG_OPCODE_EXEC 0xE06974 |
| |
| #define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE06978 |
| |
| #define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE0697C |
| |
| #define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE06980 |
| |
| #define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE06984 |
| |
| #define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE06988 |
| |
| #define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE0698C |
| |
| #define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE06990 |
| |
| #define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE06994 |
| |
| #define mmTPC0_CFG_TSB_CFG_MAX_SIZE 0xE06998 |
| |
| #define mmTPC0_CFG_TSB_CFG 0xE0699C |
| |
| #define mmTPC0_CFG_DBGMEM_ADD 0xE069A0 |
| |
| #define mmTPC0_CFG_DBGMEM_DATA_WR 0xE069A4 |
| |
| #define mmTPC0_CFG_DBGMEM_DATA_RD 0xE069A8 |
| |
| #define mmTPC0_CFG_DBGMEM_CTRL 0xE069AC |
| |
| #define mmTPC0_CFG_DBGMEM_RC 0xE069B0 |
| |
| #define mmTPC0_CFG_TSB_INFLIGHT_CNTR 0xE069B4 |
| |
| #define mmTPC0_CFG_WQ_INFLIGHT_CNTR 0xE069B8 |
| |
| #define mmTPC0_CFG_WQ_LBW_TOTAL_CNTR 0xE069BC |
| |
| #define mmTPC0_CFG_WQ_HBW_TOTAL_CNTR 0xE069C0 |
| |
| #define mmTPC0_CFG_IRQ_OCCOUPY_CNTR 0xE069C4 |
| |
| #define mmTPC0_CFG_FUNC_MBIST_CNTRL 0xE069D0 |
| |
| #define mmTPC0_CFG_FUNC_MBIST_PAT 0xE069D4 |
| |
| #define mmTPC0_CFG_FUNC_MBIST_MEM_0 0xE069D8 |
| |
| #define mmTPC0_CFG_FUNC_MBIST_MEM_1 0xE069DC |
| |
| #define mmTPC0_CFG_FUNC_MBIST_MEM_2 0xE069E0 |
| |
| #define mmTPC0_CFG_FUNC_MBIST_MEM_3 0xE069E4 |
| |
| #define mmTPC0_CFG_FUNC_MBIST_MEM_4 0xE069E8 |
| |
| #define mmTPC0_CFG_FUNC_MBIST_MEM_5 0xE069EC |
| |
| #define mmTPC0_CFG_FUNC_MBIST_MEM_6 0xE069F0 |
| |
| #define mmTPC0_CFG_FUNC_MBIST_MEM_7 0xE069F4 |
| |
| #define mmTPC0_CFG_FUNC_MBIST_MEM_8 0xE069F8 |
| |
| #define mmTPC0_CFG_FUNC_MBIST_MEM_9 0xE069FC |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE06A00 |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE06A04 |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0xE06A08 |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE06A0C |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE06A10 |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE06A14 |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE06A18 |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE06A1C |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE06A20 |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE06A24 |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE06A28 |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE06A2C |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE06A30 |
| |
| #define mmTPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE06A34 |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE06A38 |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE06A3C |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_PADDING_VALUE 0xE06A40 |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE06A44 |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE06A48 |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE06A4C |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE06A50 |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE06A54 |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE06A58 |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE06A5C |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE06A60 |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE06A64 |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE06A68 |
| |
| #define mmTPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE06A6C |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE06A70 |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE06A74 |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_PADDING_VALUE 0xE06A78 |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE06A7C |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE06A80 |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE06A84 |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE06A88 |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE06A8C |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE06A90 |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE06A94 |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE06A98 |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE06A9C |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE06AA0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE06AA4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE06AA8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE06AAC |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_PADDING_VALUE 0xE06AB0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE06AB4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE06AB8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE06ABC |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE06AC0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE06AC4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE06AC8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE06ACC |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE06AD0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE06AD4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE06AD8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE06ADC |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE06AE0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE06AE4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_PADDING_VALUE 0xE06AE8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE06AEC |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE06AF0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE06AF4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE06AF8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE06AFC |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE06B00 |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE06B04 |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE06B08 |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE06B0C |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE06B10 |
| |
| #define mmTPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE06B14 |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE06B18 |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE06B1C |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_PADDING_VALUE 0xE06B20 |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE06B24 |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE06B28 |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE06B2C |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE06B30 |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE06B34 |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE06B38 |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE06B3C |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE06B40 |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE06B44 |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE06B48 |
| |
| #define mmTPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE06B4C |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE06B50 |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE06B54 |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_PADDING_VALUE 0xE06B58 |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE06B5C |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE06B60 |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE06B64 |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE06B68 |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE06B6C |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE06B70 |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE06B74 |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE06B78 |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE06B7C |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE06B80 |
| |
| #define mmTPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE06B84 |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE06B88 |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE06B8C |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_PADDING_VALUE 0xE06B90 |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE06B94 |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE06B98 |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE06B9C |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE06BA0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE06BA4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE06BA8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE06BAC |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE06BB0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE06BB4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE06BB8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE06BBC |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE06BC0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE06BC4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_PADDING_VALUE 0xE06BC8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE06BCC |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE06BD0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE06BD4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE06BD8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE06BDC |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE06BE0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE06BE4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE06BE8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE06BEC |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE06BF0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE06BF4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE06BF8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE06BFC |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_PADDING_VALUE 0xE06C00 |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE06C04 |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE06C08 |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE06C0C |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE06C10 |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE06C14 |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE06C18 |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE06C1C |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE06C20 |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE06C24 |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE06C28 |
| |
| #define mmTPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE06C2C |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE06C30 |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE06C34 |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_PADDING_VALUE 0xE06C38 |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE06C3C |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE06C40 |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE06C44 |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE06C48 |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE06C4C |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE06C50 |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE06C54 |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE06C58 |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE06C5C |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE06C60 |
| |
| #define mmTPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE06C64 |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE06C68 |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE06C6C |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_PADDING_VALUE 0xE06C70 |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE06C74 |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE06C78 |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE06C7C |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE06C80 |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE06C84 |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE06C88 |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE06C8C |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE06C90 |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE06C94 |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE06C98 |
| |
| #define mmTPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE06C9C |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE06CA0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE06CA4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_PADDING_VALUE 0xE06CA8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE06CAC |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE06CB0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE06CB4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE06CB8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE06CBC |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE06CC0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE06CC4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE06CC8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE06CCC |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE06CD0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE06CD4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE06CD8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE06CDC |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_PADDING_VALUE 0xE06CE0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE06CE4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE06CE8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE06CEC |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE06CF0 |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE06CF4 |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE06CF8 |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE06CFC |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE06D00 |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE06D04 |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE06D08 |
| |
| #define mmTPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE06D0C |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE06D10 |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE06D14 |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_PADDING_VALUE 0xE06D18 |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE06D1C |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE06D20 |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE06D24 |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE06D28 |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE06D2C |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE06D30 |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE06D34 |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE06D38 |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE06D3C |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE06D40 |
| |
| #define mmTPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE06D44 |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE06D48 |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE06D4C |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_PADDING_VALUE 0xE06D50 |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE06D54 |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE06D58 |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE06D5C |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE06D60 |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE06D64 |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE06D68 |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE06D6C |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE06D70 |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE06D74 |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE06D78 |
| |
| #define mmTPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE06D7C |
| |
| #define mmTPC0_CFG_QM_SYNC_OBJECT_MESSAGE 0xE06D80 |
| |
| #define mmTPC0_CFG_QM_SYNC_OBJECT_ADDR 0xE06D84 |
| |
| #define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE06D88 |
| |
| #define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE06D8C |
| |
| #define mmTPC0_CFG_QM_TID_BASE_DIM_0 0xE06D90 |
| |
| #define mmTPC0_CFG_QM_TID_SIZE_DIM_0 0xE06D94 |
| |
| #define mmTPC0_CFG_QM_TID_BASE_DIM_1 0xE06D98 |
| |
| #define mmTPC0_CFG_QM_TID_SIZE_DIM_1 0xE06D9C |
| |
| #define mmTPC0_CFG_QM_TID_BASE_DIM_2 0xE06DA0 |
| |
| #define mmTPC0_CFG_QM_TID_SIZE_DIM_2 0xE06DA4 |
| |
| #define mmTPC0_CFG_QM_TID_BASE_DIM_3 0xE06DA8 |
| |
| #define mmTPC0_CFG_QM_TID_SIZE_DIM_3 0xE06DAC |
| |
| #define mmTPC0_CFG_QM_TID_BASE_DIM_4 0xE06DB0 |
| |
| #define mmTPC0_CFG_QM_TID_SIZE_DIM_4 0xE06DB4 |
| |
| #define mmTPC0_CFG_QM_KERNEL_CONFIG 0xE06DB8 |
| |
| #define mmTPC0_CFG_QM_KERNEL_ID 0xE06DBC |
| |
| #define mmTPC0_CFG_QM_SRF_0 0xE06DC0 |
| |
| #define mmTPC0_CFG_QM_SRF_1 0xE06DC4 |
| |
| #define mmTPC0_CFG_QM_SRF_2 0xE06DC8 |
| |
| #define mmTPC0_CFG_QM_SRF_3 0xE06DCC |
| |
| #define mmTPC0_CFG_QM_SRF_4 0xE06DD0 |
| |
| #define mmTPC0_CFG_QM_SRF_5 0xE06DD4 |
| |
| #define mmTPC0_CFG_QM_SRF_6 0xE06DD8 |
| |
| #define mmTPC0_CFG_QM_SRF_7 0xE06DDC |
| |
| #define mmTPC0_CFG_QM_SRF_8 0xE06DE0 |
| |
| #define mmTPC0_CFG_QM_SRF_9 0xE06DE4 |
| |
| #define mmTPC0_CFG_QM_SRF_10 0xE06DE8 |
| |
| #define mmTPC0_CFG_QM_SRF_11 0xE06DEC |
| |
| #define mmTPC0_CFG_QM_SRF_12 0xE06DF0 |
| |
| #define mmTPC0_CFG_QM_SRF_13 0xE06DF4 |
| |
| #define mmTPC0_CFG_QM_SRF_14 0xE06DF8 |
| |
| #define mmTPC0_CFG_QM_SRF_15 0xE06DFC |
| |
| #define mmTPC0_CFG_QM_SRF_16 0xE06E00 |
| |
| #define mmTPC0_CFG_QM_SRF_17 0xE06E04 |
| |
| #define mmTPC0_CFG_QM_SRF_18 0xE06E08 |
| |
| #define mmTPC0_CFG_QM_SRF_19 0xE06E0C |
| |
| #define mmTPC0_CFG_QM_SRF_20 0xE06E10 |
| |
| #define mmTPC0_CFG_QM_SRF_21 0xE06E14 |
| |
| #define mmTPC0_CFG_QM_SRF_22 0xE06E18 |
| |
| #define mmTPC0_CFG_QM_SRF_23 0xE06E1C |
| |
| #define mmTPC0_CFG_QM_SRF_24 0xE06E20 |
| |
| #define mmTPC0_CFG_QM_SRF_25 0xE06E24 |
| |
| #define mmTPC0_CFG_QM_SRF_26 0xE06E28 |
| |
| #define mmTPC0_CFG_QM_SRF_27 0xE06E2C |
| |
| #define mmTPC0_CFG_QM_SRF_28 0xE06E30 |
| |
| #define mmTPC0_CFG_QM_SRF_29 0xE06E34 |
| |
| #define mmTPC0_CFG_QM_SRF_30 0xE06E38 |
| |
| #define mmTPC0_CFG_QM_SRF_31 0xE06E3C |
| |
| #endif /* ASIC_REG_TPC0_CFG_REGS_H_ */ |
