| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_TPC5_QM_REGS_H_ |
| #define ASIC_REG_TPC5_QM_REGS_H_ |
| |
| /* |
| ***************************************** |
| * TPC5_QM (Prototype: QMAN) |
| ***************************************** |
| */ |
| |
| #define mmTPC5_QM_GLBL_CFG0 0xF48000 |
| |
| #define mmTPC5_QM_GLBL_CFG1 0xF48004 |
| |
| #define mmTPC5_QM_GLBL_PROT 0xF48008 |
| |
| #define mmTPC5_QM_GLBL_ERR_CFG 0xF4800C |
| |
| #define mmTPC5_QM_GLBL_SECURE_PROPS_0 0xF48010 |
| |
| #define mmTPC5_QM_GLBL_SECURE_PROPS_1 0xF48014 |
| |
| #define mmTPC5_QM_GLBL_SECURE_PROPS_2 0xF48018 |
| |
| #define mmTPC5_QM_GLBL_SECURE_PROPS_3 0xF4801C |
| |
| #define mmTPC5_QM_GLBL_SECURE_PROPS_4 0xF48020 |
| |
| #define mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 0xF48024 |
| |
| #define mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 0xF48028 |
| |
| #define mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 0xF4802C |
| |
| #define mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 0xF48030 |
| |
| #define mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 0xF48034 |
| |
| #define mmTPC5_QM_GLBL_STS0 0xF48038 |
| |
| #define mmTPC5_QM_GLBL_STS1_0 0xF48040 |
| |
| #define mmTPC5_QM_GLBL_STS1_1 0xF48044 |
| |
| #define mmTPC5_QM_GLBL_STS1_2 0xF48048 |
| |
| #define mmTPC5_QM_GLBL_STS1_3 0xF4804C |
| |
| #define mmTPC5_QM_GLBL_STS1_4 0xF48050 |
| |
| #define mmTPC5_QM_GLBL_MSG_EN_0 0xF48054 |
| |
| #define mmTPC5_QM_GLBL_MSG_EN_1 0xF48058 |
| |
| #define mmTPC5_QM_GLBL_MSG_EN_2 0xF4805C |
| |
| #define mmTPC5_QM_GLBL_MSG_EN_3 0xF48060 |
| |
| #define mmTPC5_QM_GLBL_MSG_EN_4 0xF48068 |
| |
| #define mmTPC5_QM_PQ_BASE_LO_0 0xF48070 |
| |
| #define mmTPC5_QM_PQ_BASE_LO_1 0xF48074 |
| |
| #define mmTPC5_QM_PQ_BASE_LO_2 0xF48078 |
| |
| #define mmTPC5_QM_PQ_BASE_LO_3 0xF4807C |
| |
| #define mmTPC5_QM_PQ_BASE_HI_0 0xF48080 |
| |
| #define mmTPC5_QM_PQ_BASE_HI_1 0xF48084 |
| |
| #define mmTPC5_QM_PQ_BASE_HI_2 0xF48088 |
| |
| #define mmTPC5_QM_PQ_BASE_HI_3 0xF4808C |
| |
| #define mmTPC5_QM_PQ_SIZE_0 0xF48090 |
| |
| #define mmTPC5_QM_PQ_SIZE_1 0xF48094 |
| |
| #define mmTPC5_QM_PQ_SIZE_2 0xF48098 |
| |
| #define mmTPC5_QM_PQ_SIZE_3 0xF4809C |
| |
| #define mmTPC5_QM_PQ_PI_0 0xF480A0 |
| |
| #define mmTPC5_QM_PQ_PI_1 0xF480A4 |
| |
| #define mmTPC5_QM_PQ_PI_2 0xF480A8 |
| |
| #define mmTPC5_QM_PQ_PI_3 0xF480AC |
| |
| #define mmTPC5_QM_PQ_CI_0 0xF480B0 |
| |
| #define mmTPC5_QM_PQ_CI_1 0xF480B4 |
| |
| #define mmTPC5_QM_PQ_CI_2 0xF480B8 |
| |
| #define mmTPC5_QM_PQ_CI_3 0xF480BC |
| |
| #define mmTPC5_QM_PQ_CFG0_0 0xF480C0 |
| |
| #define mmTPC5_QM_PQ_CFG0_1 0xF480C4 |
| |
| #define mmTPC5_QM_PQ_CFG0_2 0xF480C8 |
| |
| #define mmTPC5_QM_PQ_CFG0_3 0xF480CC |
| |
| #define mmTPC5_QM_PQ_CFG1_0 0xF480D0 |
| |
| #define mmTPC5_QM_PQ_CFG1_1 0xF480D4 |
| |
| #define mmTPC5_QM_PQ_CFG1_2 0xF480D8 |
| |
| #define mmTPC5_QM_PQ_CFG1_3 0xF480DC |
| |
| #define mmTPC5_QM_PQ_ARUSER_31_11_0 0xF480E0 |
| |
| #define mmTPC5_QM_PQ_ARUSER_31_11_1 0xF480E4 |
| |
| #define mmTPC5_QM_PQ_ARUSER_31_11_2 0xF480E8 |
| |
| #define mmTPC5_QM_PQ_ARUSER_31_11_3 0xF480EC |
| |
| #define mmTPC5_QM_PQ_STS0_0 0xF480F0 |
| |
| #define mmTPC5_QM_PQ_STS0_1 0xF480F4 |
| |
| #define mmTPC5_QM_PQ_STS0_2 0xF480F8 |
| |
| #define mmTPC5_QM_PQ_STS0_3 0xF480FC |
| |
| #define mmTPC5_QM_PQ_STS1_0 0xF48100 |
| |
| #define mmTPC5_QM_PQ_STS1_1 0xF48104 |
| |
| #define mmTPC5_QM_PQ_STS1_2 0xF48108 |
| |
| #define mmTPC5_QM_PQ_STS1_3 0xF4810C |
| |
| #define mmTPC5_QM_CQ_CFG0_0 0xF48110 |
| |
| #define mmTPC5_QM_CQ_CFG0_1 0xF48114 |
| |
| #define mmTPC5_QM_CQ_CFG0_2 0xF48118 |
| |
| #define mmTPC5_QM_CQ_CFG0_3 0xF4811C |
| |
| #define mmTPC5_QM_CQ_CFG0_4 0xF48120 |
| |
| #define mmTPC5_QM_CQ_CFG1_0 0xF48124 |
| |
| #define mmTPC5_QM_CQ_CFG1_1 0xF48128 |
| |
| #define mmTPC5_QM_CQ_CFG1_2 0xF4812C |
| |
| #define mmTPC5_QM_CQ_CFG1_3 0xF48130 |
| |
| #define mmTPC5_QM_CQ_CFG1_4 0xF48134 |
| |
| #define mmTPC5_QM_CQ_ARUSER_31_11_0 0xF48138 |
| |
| #define mmTPC5_QM_CQ_ARUSER_31_11_1 0xF4813C |
| |
| #define mmTPC5_QM_CQ_ARUSER_31_11_2 0xF48140 |
| |
| #define mmTPC5_QM_CQ_ARUSER_31_11_3 0xF48144 |
| |
| #define mmTPC5_QM_CQ_ARUSER_31_11_4 0xF48148 |
| |
| #define mmTPC5_QM_CQ_STS0_0 0xF4814C |
| |
| #define mmTPC5_QM_CQ_STS0_1 0xF48150 |
| |
| #define mmTPC5_QM_CQ_STS0_2 0xF48154 |
| |
| #define mmTPC5_QM_CQ_STS0_3 0xF48158 |
| |
| #define mmTPC5_QM_CQ_STS0_4 0xF4815C |
| |
| #define mmTPC5_QM_CQ_STS1_0 0xF48160 |
| |
| #define mmTPC5_QM_CQ_STS1_1 0xF48164 |
| |
| #define mmTPC5_QM_CQ_STS1_2 0xF48168 |
| |
| #define mmTPC5_QM_CQ_STS1_3 0xF4816C |
| |
| #define mmTPC5_QM_CQ_STS1_4 0xF48170 |
| |
| #define mmTPC5_QM_CQ_PTR_LO_0 0xF48174 |
| |
| #define mmTPC5_QM_CQ_PTR_HI_0 0xF48178 |
| |
| #define mmTPC5_QM_CQ_TSIZE_0 0xF4817C |
| |
| #define mmTPC5_QM_CQ_CTL_0 0xF48180 |
| |
| #define mmTPC5_QM_CQ_PTR_LO_1 0xF48184 |
| |
| #define mmTPC5_QM_CQ_PTR_HI_1 0xF48188 |
| |
| #define mmTPC5_QM_CQ_TSIZE_1 0xF4818C |
| |
| #define mmTPC5_QM_CQ_CTL_1 0xF48190 |
| |
| #define mmTPC5_QM_CQ_PTR_LO_2 0xF48194 |
| |
| #define mmTPC5_QM_CQ_PTR_HI_2 0xF48198 |
| |
| #define mmTPC5_QM_CQ_TSIZE_2 0xF4819C |
| |
| #define mmTPC5_QM_CQ_CTL_2 0xF481A0 |
| |
| #define mmTPC5_QM_CQ_PTR_LO_3 0xF481A4 |
| |
| #define mmTPC5_QM_CQ_PTR_HI_3 0xF481A8 |
| |
| #define mmTPC5_QM_CQ_TSIZE_3 0xF481AC |
| |
| #define mmTPC5_QM_CQ_CTL_3 0xF481B0 |
| |
| #define mmTPC5_QM_CQ_PTR_LO_4 0xF481B4 |
| |
| #define mmTPC5_QM_CQ_PTR_HI_4 0xF481B8 |
| |
| #define mmTPC5_QM_CQ_TSIZE_4 0xF481BC |
| |
| #define mmTPC5_QM_CQ_CTL_4 0xF481C0 |
| |
| #define mmTPC5_QM_CQ_PTR_LO_STS_0 0xF481C4 |
| |
| #define mmTPC5_QM_CQ_PTR_LO_STS_1 0xF481C8 |
| |
| #define mmTPC5_QM_CQ_PTR_LO_STS_2 0xF481CC |
| |
| #define mmTPC5_QM_CQ_PTR_LO_STS_3 0xF481D0 |
| |
| #define mmTPC5_QM_CQ_PTR_LO_STS_4 0xF481D4 |
| |
| #define mmTPC5_QM_CQ_PTR_HI_STS_0 0xF481D8 |
| |
| #define mmTPC5_QM_CQ_PTR_HI_STS_1 0xF481DC |
| |
| #define mmTPC5_QM_CQ_PTR_HI_STS_2 0xF481E0 |
| |
| #define mmTPC5_QM_CQ_PTR_HI_STS_3 0xF481E4 |
| |
| #define mmTPC5_QM_CQ_PTR_HI_STS_4 0xF481E8 |
| |
| #define mmTPC5_QM_CQ_TSIZE_STS_0 0xF481EC |
| |
| #define mmTPC5_QM_CQ_TSIZE_STS_1 0xF481F0 |
| |
| #define mmTPC5_QM_CQ_TSIZE_STS_2 0xF481F4 |
| |
| #define mmTPC5_QM_CQ_TSIZE_STS_3 0xF481F8 |
| |
| #define mmTPC5_QM_CQ_TSIZE_STS_4 0xF481FC |
| |
| #define mmTPC5_QM_CQ_CTL_STS_0 0xF48200 |
| |
| #define mmTPC5_QM_CQ_CTL_STS_1 0xF48204 |
| |
| #define mmTPC5_QM_CQ_CTL_STS_2 0xF48208 |
| |
| #define mmTPC5_QM_CQ_CTL_STS_3 0xF4820C |
| |
| #define mmTPC5_QM_CQ_CTL_STS_4 0xF48210 |
| |
| #define mmTPC5_QM_CQ_IFIFO_CNT_0 0xF48214 |
| |
| #define mmTPC5_QM_CQ_IFIFO_CNT_1 0xF48218 |
| |
| #define mmTPC5_QM_CQ_IFIFO_CNT_2 0xF4821C |
| |
| #define mmTPC5_QM_CQ_IFIFO_CNT_3 0xF48220 |
| |
| #define mmTPC5_QM_CQ_IFIFO_CNT_4 0xF48224 |
| |
| #define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 0xF48228 |
| |
| #define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 0xF4822C |
| |
| #define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 0xF48230 |
| |
| #define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 0xF48234 |
| |
| #define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 0xF48238 |
| |
| #define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 0xF4823C |
| |
| #define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 0xF48240 |
| |
| #define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 0xF48244 |
| |
| #define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 0xF48248 |
| |
| #define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 0xF4824C |
| |
| #define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 0xF48250 |
| |
| #define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 0xF48254 |
| |
| #define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 0xF48258 |
| |
| #define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 0xF4825C |
| |
| #define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 0xF48260 |
| |
| #define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 0xF48264 |
| |
| #define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 0xF48268 |
| |
| #define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 0xF4826C |
| |
| #define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 0xF48270 |
| |
| #define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 0xF48274 |
| |
| #define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 0xF48278 |
| |
| #define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 0xF4827C |
| |
| #define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 0xF48280 |
| |
| #define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 0xF48284 |
| |
| #define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 0xF48288 |
| |
| #define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 0xF4828C |
| |
| #define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 0xF48290 |
| |
| #define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 0xF48294 |
| |
| #define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 0xF48298 |
| |
| #define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 0xF4829C |
| |
| #define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 0xF482A0 |
| |
| #define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 0xF482A4 |
| |
| #define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 0xF482A8 |
| |
| #define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 0xF482AC |
| |
| #define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 0xF482B0 |
| |
| #define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 0xF482B4 |
| |
| #define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 0xF482B8 |
| |
| #define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 0xF482BC |
| |
| #define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 0xF482C0 |
| |
| #define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 0xF482C4 |
| |
| #define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 0xF482C8 |
| |
| #define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 0xF482CC |
| |
| #define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 0xF482D0 |
| |
| #define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 0xF482D4 |
| |
| #define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 0xF482D8 |
| |
| #define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF482E0 |
| |
| #define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF482E4 |
| |
| #define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF482E8 |
| |
| #define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF482EC |
| |
| #define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF482F0 |
| |
| #define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF482F4 |
| |
| #define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF482F8 |
| |
| #define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF482FC |
| |
| #define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF48300 |
| |
| #define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF48304 |
| |
| #define mmTPC5_QM_CP_FENCE0_RDATA_0 0xF48308 |
| |
| #define mmTPC5_QM_CP_FENCE0_RDATA_1 0xF4830C |
| |
| #define mmTPC5_QM_CP_FENCE0_RDATA_2 0xF48310 |
| |
| #define mmTPC5_QM_CP_FENCE0_RDATA_3 0xF48314 |
| |
| #define mmTPC5_QM_CP_FENCE0_RDATA_4 0xF48318 |
| |
| #define mmTPC5_QM_CP_FENCE1_RDATA_0 0xF4831C |
| |
| #define mmTPC5_QM_CP_FENCE1_RDATA_1 0xF48320 |
| |
| #define mmTPC5_QM_CP_FENCE1_RDATA_2 0xF48324 |
| |
| #define mmTPC5_QM_CP_FENCE1_RDATA_3 0xF48328 |
| |
| #define mmTPC5_QM_CP_FENCE1_RDATA_4 0xF4832C |
| |
| #define mmTPC5_QM_CP_FENCE2_RDATA_0 0xF48330 |
| |
| #define mmTPC5_QM_CP_FENCE2_RDATA_1 0xF48334 |
| |
| #define mmTPC5_QM_CP_FENCE2_RDATA_2 0xF48338 |
| |
| #define mmTPC5_QM_CP_FENCE2_RDATA_3 0xF4833C |
| |
| #define mmTPC5_QM_CP_FENCE2_RDATA_4 0xF48340 |
| |
| #define mmTPC5_QM_CP_FENCE3_RDATA_0 0xF48344 |
| |
| #define mmTPC5_QM_CP_FENCE3_RDATA_1 0xF48348 |
| |
| #define mmTPC5_QM_CP_FENCE3_RDATA_2 0xF4834C |
| |
| #define mmTPC5_QM_CP_FENCE3_RDATA_3 0xF48350 |
| |
| #define mmTPC5_QM_CP_FENCE3_RDATA_4 0xF48354 |
| |
| #define mmTPC5_QM_CP_FENCE0_CNT_0 0xF48358 |
| |
| #define mmTPC5_QM_CP_FENCE0_CNT_1 0xF4835C |
| |
| #define mmTPC5_QM_CP_FENCE0_CNT_2 0xF48360 |
| |
| #define mmTPC5_QM_CP_FENCE0_CNT_3 0xF48364 |
| |
| #define mmTPC5_QM_CP_FENCE0_CNT_4 0xF48368 |
| |
| #define mmTPC5_QM_CP_FENCE1_CNT_0 0xF4836C |
| |
| #define mmTPC5_QM_CP_FENCE1_CNT_1 0xF48370 |
| |
| #define mmTPC5_QM_CP_FENCE1_CNT_2 0xF48374 |
| |
| #define mmTPC5_QM_CP_FENCE1_CNT_3 0xF48378 |
| |
| #define mmTPC5_QM_CP_FENCE1_CNT_4 0xF4837C |
| |
| #define mmTPC5_QM_CP_FENCE2_CNT_0 0xF48380 |
| |
| #define mmTPC5_QM_CP_FENCE2_CNT_1 0xF48384 |
| |
| #define mmTPC5_QM_CP_FENCE2_CNT_2 0xF48388 |
| |
| #define mmTPC5_QM_CP_FENCE2_CNT_3 0xF4838C |
| |
| #define mmTPC5_QM_CP_FENCE2_CNT_4 0xF48390 |
| |
| #define mmTPC5_QM_CP_FENCE3_CNT_0 0xF48394 |
| |
| #define mmTPC5_QM_CP_FENCE3_CNT_1 0xF48398 |
| |
| #define mmTPC5_QM_CP_FENCE3_CNT_2 0xF4839C |
| |
| #define mmTPC5_QM_CP_FENCE3_CNT_3 0xF483A0 |
| |
| #define mmTPC5_QM_CP_FENCE3_CNT_4 0xF483A4 |
| |
| #define mmTPC5_QM_CP_STS_0 0xF483A8 |
| |
| #define mmTPC5_QM_CP_STS_1 0xF483AC |
| |
| #define mmTPC5_QM_CP_STS_2 0xF483B0 |
| |
| #define mmTPC5_QM_CP_STS_3 0xF483B4 |
| |
| #define mmTPC5_QM_CP_STS_4 0xF483B8 |
| |
| #define mmTPC5_QM_CP_CURRENT_INST_LO_0 0xF483BC |
| |
| #define mmTPC5_QM_CP_CURRENT_INST_LO_1 0xF483C0 |
| |
| #define mmTPC5_QM_CP_CURRENT_INST_LO_2 0xF483C4 |
| |
| #define mmTPC5_QM_CP_CURRENT_INST_LO_3 0xF483C8 |
| |
| #define mmTPC5_QM_CP_CURRENT_INST_LO_4 0xF483CC |
| |
| #define mmTPC5_QM_CP_CURRENT_INST_HI_0 0xF483D0 |
| |
| #define mmTPC5_QM_CP_CURRENT_INST_HI_1 0xF483D4 |
| |
| #define mmTPC5_QM_CP_CURRENT_INST_HI_2 0xF483D8 |
| |
| #define mmTPC5_QM_CP_CURRENT_INST_HI_3 0xF483DC |
| |
| #define mmTPC5_QM_CP_CURRENT_INST_HI_4 0xF483E0 |
| |
| #define mmTPC5_QM_CP_BARRIER_CFG_0 0xF483F4 |
| |
| #define mmTPC5_QM_CP_BARRIER_CFG_1 0xF483F8 |
| |
| #define mmTPC5_QM_CP_BARRIER_CFG_2 0xF483FC |
| |
| #define mmTPC5_QM_CP_BARRIER_CFG_3 0xF48400 |
| |
| #define mmTPC5_QM_CP_BARRIER_CFG_4 0xF48404 |
| |
| #define mmTPC5_QM_CP_DBG_0_0 0xF48408 |
| |
| #define mmTPC5_QM_CP_DBG_0_1 0xF4840C |
| |
| #define mmTPC5_QM_CP_DBG_0_2 0xF48410 |
| |
| #define mmTPC5_QM_CP_DBG_0_3 0xF48414 |
| |
| #define mmTPC5_QM_CP_DBG_0_4 0xF48418 |
| |
| #define mmTPC5_QM_CP_ARUSER_31_11_0 0xF4841C |
| |
| #define mmTPC5_QM_CP_ARUSER_31_11_1 0xF48420 |
| |
| #define mmTPC5_QM_CP_ARUSER_31_11_2 0xF48424 |
| |
| #define mmTPC5_QM_CP_ARUSER_31_11_3 0xF48428 |
| |
| #define mmTPC5_QM_CP_ARUSER_31_11_4 0xF4842C |
| |
| #define mmTPC5_QM_CP_AWUSER_31_11_0 0xF48430 |
| |
| #define mmTPC5_QM_CP_AWUSER_31_11_1 0xF48434 |
| |
| #define mmTPC5_QM_CP_AWUSER_31_11_2 0xF48438 |
| |
| #define mmTPC5_QM_CP_AWUSER_31_11_3 0xF4843C |
| |
| #define mmTPC5_QM_CP_AWUSER_31_11_4 0xF48440 |
| |
| #define mmTPC5_QM_ARB_CFG_0 0xF48A00 |
| |
| #define mmTPC5_QM_ARB_CHOISE_Q_PUSH 0xF48A04 |
| |
| #define mmTPC5_QM_ARB_WRR_WEIGHT_0 0xF48A08 |
| |
| #define mmTPC5_QM_ARB_WRR_WEIGHT_1 0xF48A0C |
| |
| #define mmTPC5_QM_ARB_WRR_WEIGHT_2 0xF48A10 |
| |
| #define mmTPC5_QM_ARB_WRR_WEIGHT_3 0xF48A14 |
| |
| #define mmTPC5_QM_ARB_CFG_1 0xF48A18 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_0 0xF48A20 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_1 0xF48A24 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_2 0xF48A28 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_3 0xF48A2C |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_4 0xF48A30 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_5 0xF48A34 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_6 0xF48A38 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_7 0xF48A3C |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_8 0xF48A40 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_9 0xF48A44 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_10 0xF48A48 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_11 0xF48A4C |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_12 0xF48A50 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_13 0xF48A54 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_14 0xF48A58 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_15 0xF48A5C |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_16 0xF48A60 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_17 0xF48A64 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_18 0xF48A68 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_19 0xF48A6C |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_20 0xF48A70 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_21 0xF48A74 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_22 0xF48A78 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_23 0xF48A7C |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_24 0xF48A80 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_25 0xF48A84 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_26 0xF48A88 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_27 0xF48A8C |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_28 0xF48A90 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_29 0xF48A94 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_30 0xF48A98 |
| |
| #define mmTPC5_QM_ARB_MST_AVAIL_CRED_31 0xF48A9C |
| |
| #define mmTPC5_QM_ARB_MST_CRED_INC 0xF48AA0 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF48AA4 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF48AA8 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF48AAC |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF48AB0 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF48AB4 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF48AB8 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF48ABC |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF48AC0 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF48AC4 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF48AC8 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF48ACC |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF48AD0 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF48AD4 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF48AD8 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF48ADC |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF48AE0 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF48AE4 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF48AE8 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF48AEC |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF48AF0 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF48AF4 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF48AF8 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF48AFC |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF48B00 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF48B04 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF48B08 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF48B0C |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF48B10 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF48B14 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF48B18 |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF48B1C |
| |
| #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF48B20 |
| |
| #define mmTPC5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF48B28 |
| |
| #define mmTPC5_QM_ARB_MST_SLAVE_EN 0xF48B2C |
| |
| #define mmTPC5_QM_ARB_MST_QUIET_PER 0xF48B34 |
| |
| #define mmTPC5_QM_ARB_SLV_CHOISE_WDT 0xF48B38 |
| |
| #define mmTPC5_QM_ARB_SLV_ID 0xF48B3C |
| |
| #define mmTPC5_QM_ARB_MSG_MAX_INFLIGHT 0xF48B44 |
| |
| #define mmTPC5_QM_ARB_MSG_AWUSER_31_11 0xF48B48 |
| |
| #define mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP 0xF48B4C |
| |
| #define mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF48B50 |
| |
| #define mmTPC5_QM_ARB_BASE_LO 0xF48B54 |
| |
| #define mmTPC5_QM_ARB_BASE_HI 0xF48B58 |
| |
| #define mmTPC5_QM_ARB_STATE_STS 0xF48B80 |
| |
| #define mmTPC5_QM_ARB_CHOISE_FULLNESS_STS 0xF48B84 |
| |
| #define mmTPC5_QM_ARB_MSG_STS 0xF48B88 |
| |
| #define mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD 0xF48B8C |
| |
| #define mmTPC5_QM_ARB_ERR_CAUSE 0xF48B9C |
| |
| #define mmTPC5_QM_ARB_ERR_MSG_EN 0xF48BA0 |
| |
| #define mmTPC5_QM_ARB_ERR_STS_DRP 0xF48BA8 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_0 0xF48BB0 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_1 0xF48BB4 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_2 0xF48BB8 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_3 0xF48BBC |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_4 0xF48BC0 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_5 0xF48BC4 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_6 0xF48BC8 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_7 0xF48BCC |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_8 0xF48BD0 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_9 0xF48BD4 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_10 0xF48BD8 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_11 0xF48BDC |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_12 0xF48BE0 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_13 0xF48BE4 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_14 0xF48BE8 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_15 0xF48BEC |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_16 0xF48BF0 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_17 0xF48BF4 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_18 0xF48BF8 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_19 0xF48BFC |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_20 0xF48C00 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_21 0xF48C04 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_22 0xF48C08 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_23 0xF48C0C |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_24 0xF48C10 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_25 0xF48C14 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_26 0xF48C18 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_27 0xF48C1C |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_28 0xF48C20 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_29 0xF48C24 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_30 0xF48C28 |
| |
| #define mmTPC5_QM_ARB_MST_CRED_STS_31 0xF48C2C |
| |
| #define mmTPC5_QM_CGM_CFG 0xF48C70 |
| |
| #define mmTPC5_QM_CGM_STS 0xF48C74 |
| |
| #define mmTPC5_QM_CGM_CFG1 0xF48C78 |
| |
| #define mmTPC5_QM_LOCAL_RANGE_BASE 0xF48C80 |
| |
| #define mmTPC5_QM_LOCAL_RANGE_SIZE 0xF48C84 |
| |
| #define mmTPC5_QM_CSMR_STRICT_PRIO_CFG 0xF48C90 |
| |
| #define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 0xF48C94 |
| |
| #define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 0xF48C98 |
| |
| #define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 0xF48C9C |
| |
| #define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 0xF48CA0 |
| |
| #define mmTPC5_QM_GLBL_AXCACHE 0xF48CA4 |
| |
| #define mmTPC5_QM_IND_GW_APB_CFG 0xF48CB0 |
| |
| #define mmTPC5_QM_IND_GW_APB_WDATA 0xF48CB4 |
| |
| #define mmTPC5_QM_IND_GW_APB_RDATA 0xF48CB8 |
| |
| #define mmTPC5_QM_IND_GW_APB_STATUS 0xF48CBC |
| |
| #define mmTPC5_QM_GLBL_ERR_ADDR_LO 0xF48CD0 |
| |
| #define mmTPC5_QM_GLBL_ERR_ADDR_HI 0xF48CD4 |
| |
| #define mmTPC5_QM_GLBL_ERR_WDATA 0xF48CD8 |
| |
| #define mmTPC5_QM_GLBL_MEM_INIT_BUSY 0xF48D00 |
| |
| #endif /* ASIC_REG_TPC5_QM_REGS_H_ */ |
