| /* |
| * MPC8360E EMDS Device Tree Source |
| * |
| * Copyright 2006 Freescale Semiconductor Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License as published by the |
| * Free Software Foundation; either version 2 of the License, or (at your |
| * option) any later version. |
| */ |
| |
| |
| /* |
| /memreserve/ 00000000 1000000; |
| */ |
| |
| /dts-v1/; |
| |
| / { |
| model = "MPC8360MDS"; |
| compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| aliases { |
| ethernet0 = &enet0; |
| ethernet1 = &enet1; |
| serial0 = &serial0; |
| serial1 = &serial1; |
| pci0 = &pci0; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| PowerPC,8360@0 { |
| device_type = "cpu"; |
| reg = <0x0>; |
| d-cache-line-size = <32>; // 32 bytes |
| i-cache-line-size = <32>; // 32 bytes |
| d-cache-size = <32768>; // L1, 32K |
| i-cache-size = <32768>; // L1, 32K |
| timebase-frequency = <66000000>; |
| bus-frequency = <264000000>; |
| clock-frequency = <528000000>; |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| reg = <0x00000000 0x10000000>; |
| }; |
| |
| bcsr@f8000000 { |
| device_type = "board-control"; |
| reg = <0xf8000000 0x8000>; |
| }; |
| |
| soc8360@e0000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "soc"; |
| ranges = <0x0 0xe0000000 0x00100000>; |
| reg = <0xe0000000 0x00000200>; |
| bus-frequency = <264000000>; |
| |
| wdt@200 { |
| device_type = "watchdog"; |
| compatible = "mpc83xx_wdt"; |
| reg = <0x200 0x100>; |
| }; |
| |
| i2c@3000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <0>; |
| compatible = "fsl-i2c"; |
| reg = <0x3000 0x100>; |
| interrupts = <14 0x8>; |
| interrupt-parent = <&ipic>; |
| dfsrr; |
| |
| rtc@68 { |
| compatible = "dallas,ds1374"; |
| reg = <0x68>; |
| }; |
| }; |
| |
| i2c@3100 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <1>; |
| compatible = "fsl-i2c"; |
| reg = <0x3100 0x100>; |
| interrupts = <15 0x8>; |
| interrupt-parent = <&ipic>; |
| dfsrr; |
| }; |
| |
| serial0: serial@4500 { |
| cell-index = <0>; |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <0x4500 0x100>; |
| clock-frequency = <264000000>; |
| interrupts = <9 0x8>; |
| interrupt-parent = <&ipic>; |
| }; |
| |
| serial1: serial@4600 { |
| cell-index = <1>; |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <0x4600 0x100>; |
| clock-frequency = <264000000>; |
| interrupts = <10 0x8>; |
| interrupt-parent = <&ipic>; |
| }; |
| |
| crypto@30000 { |
| device_type = "crypto"; |
| model = "SEC2"; |
| compatible = "talitos"; |
| reg = <0x30000 0x10000>; |
| interrupts = <11 0x8>; |
| interrupt-parent = <&ipic>; |
| num-channels = <4>; |
| channel-fifo-len = <24>; |
| exec-units-mask = <0x0000007e>; |
| /* desc mask is for rev1.x, we need runtime fixup for >=2.x */ |
| descriptor-types-mask = <0x01010ebf>; |
| }; |
| |
| ipic: pic@700 { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| reg = <0x700 0x100>; |
| device_type = "ipic"; |
| }; |
| |
| par_io@1400 { |
| reg = <0x1400 0x100>; |
| device_type = "par_io"; |
| num-ports = <7>; |
| |
| pio1: ucc_pin@01 { |
| pio-map = < |
| /* port pin dir open_drain assignment has_irq */ |
| 0 3 1 0 1 0 /* TxD0 */ |
| 0 4 1 0 1 0 /* TxD1 */ |
| 0 5 1 0 1 0 /* TxD2 */ |
| 0 6 1 0 1 0 /* TxD3 */ |
| 1 6 1 0 3 0 /* TxD4 */ |
| 1 7 1 0 1 0 /* TxD5 */ |
| 1 9 1 0 2 0 /* TxD6 */ |
| 1 10 1 0 2 0 /* TxD7 */ |
| 0 9 2 0 1 0 /* RxD0 */ |
| 0 10 2 0 1 0 /* RxD1 */ |
| 0 11 2 0 1 0 /* RxD2 */ |
| 0 12 2 0 1 0 /* RxD3 */ |
| 0 13 2 0 1 0 /* RxD4 */ |
| 1 1 2 0 2 0 /* RxD5 */ |
| 1 0 2 0 2 0 /* RxD6 */ |
| 1 4 2 0 2 0 /* RxD7 */ |
| 0 7 1 0 1 0 /* TX_EN */ |
| 0 8 1 0 1 0 /* TX_ER */ |
| 0 15 2 0 1 0 /* RX_DV */ |
| 0 16 2 0 1 0 /* RX_ER */ |
| 0 0 2 0 1 0 /* RX_CLK */ |
| 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ |
| 2 8 2 0 1 0>; /* GTX125 - CLK9 */ |
| }; |
| pio2: ucc_pin@02 { |
| pio-map = < |
| /* port pin dir open_drain assignment has_irq */ |
| 0 17 1 0 1 0 /* TxD0 */ |
| 0 18 1 0 1 0 /* TxD1 */ |
| 0 19 1 0 1 0 /* TxD2 */ |
| 0 20 1 0 1 0 /* TxD3 */ |
| 1 2 1 0 1 0 /* TxD4 */ |
| 1 3 1 0 2 0 /* TxD5 */ |
| 1 5 1 0 3 0 /* TxD6 */ |
| 1 8 1 0 3 0 /* TxD7 */ |
| 0 23 2 0 1 0 /* RxD0 */ |
| 0 24 2 0 1 0 /* RxD1 */ |
| 0 25 2 0 1 0 /* RxD2 */ |
| 0 26 2 0 1 0 /* RxD3 */ |
| 0 27 2 0 1 0 /* RxD4 */ |
| 1 12 2 0 2 0 /* RxD5 */ |
| 1 13 2 0 3 0 /* RxD6 */ |
| 1 11 2 0 2 0 /* RxD7 */ |
| 0 21 1 0 1 0 /* TX_EN */ |
| 0 22 1 0 1 0 /* TX_ER */ |
| 0 29 2 0 1 0 /* RX_DV */ |
| 0 30 2 0 1 0 /* RX_ER */ |
| 0 31 2 0 1 0 /* RX_CLK */ |
| 2 2 1 0 2 0 /* GTX_CLK - CLK10 */ |
| 2 3 2 0 1 0 /* GTX125 - CLK4 */ |
| 0 1 3 0 2 0 /* MDIO */ |
| 0 2 1 0 1 0>; /* MDC */ |
| }; |
| |
| }; |
| }; |
| |
| qe@e0100000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "qe"; |
| compatible = "fsl,qe"; |
| ranges = <0x0 0xe0100000 0x00100000>; |
| reg = <0xe0100000 0x480>; |
| brg-frequency = <0>; |
| bus-frequency = <396000000>; |
| |
| muram@10000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,qe-muram", "fsl,cpm-muram"; |
| ranges = <0x0 0x00010000 0x0000c000>; |
| |
| data-only@0 { |
| compatible = "fsl,qe-muram-data", |
| "fsl,cpm-muram-data"; |
| reg = <0x0 0xc000>; |
| }; |
| }; |
| |
| spi@4c0 { |
| cell-index = <0>; |
| compatible = "fsl,spi"; |
| reg = <0x4c0 0x40>; |
| interrupts = <2>; |
| interrupt-parent = <&qeic>; |
| mode = "cpu"; |
| }; |
| |
| spi@500 { |
| cell-index = <1>; |
| compatible = "fsl,spi"; |
| reg = <0x500 0x40>; |
| interrupts = <1>; |
| interrupt-parent = <&qeic>; |
| mode = "cpu"; |
| }; |
| |
| usb@6c0 { |
| compatible = "qe_udc"; |
| reg = <0x6c0 0x40 0x8b00 0x100>; |
| interrupts = <11>; |
| interrupt-parent = <&qeic>; |
| mode = "slave"; |
| }; |
| |
| enet0: ucc@2000 { |
| device_type = "network"; |
| compatible = "ucc_geth"; |
| model = "UCC"; |
| cell-index = <1>; |
| device-id = <1>; |
| reg = <0x2000 0x200>; |
| interrupts = <32>; |
| interrupt-parent = <&qeic>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| rx-clock-name = "none"; |
| tx-clock-name = "clk9"; |
| phy-handle = <&phy0>; |
| phy-connection-type = "rgmii-id"; |
| pio-handle = <&pio1>; |
| }; |
| |
| enet1: ucc@3000 { |
| device_type = "network"; |
| compatible = "ucc_geth"; |
| model = "UCC"; |
| cell-index = <2>; |
| device-id = <2>; |
| reg = <0x3000 0x200>; |
| interrupts = <33>; |
| interrupt-parent = <&qeic>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| rx-clock-name = "none"; |
| tx-clock-name = "clk4"; |
| phy-handle = <&phy1>; |
| phy-connection-type = "rgmii-id"; |
| pio-handle = <&pio2>; |
| }; |
| |
| mdio@2120 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x2120 0x18>; |
| compatible = "fsl,ucc-mdio"; |
| |
| phy0: ethernet-phy@00 { |
| interrupt-parent = <&ipic>; |
| interrupts = <17 0x8>; |
| reg = <0x0>; |
| device_type = "ethernet-phy"; |
| }; |
| phy1: ethernet-phy@01 { |
| interrupt-parent = <&ipic>; |
| interrupts = <18 0x8>; |
| reg = <0x1>; |
| device_type = "ethernet-phy"; |
| }; |
| }; |
| |
| qeic: interrupt-controller@80 { |
| interrupt-controller; |
| compatible = "fsl,qe-ic"; |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| reg = <0x80 0x80>; |
| big-endian; |
| interrupts = <32 0x8 33 0x8>; // high:32 low:33 |
| interrupt-parent = <&ipic>; |
| }; |
| }; |
| |
| pci0: pci@e0008500 { |
| cell-index = <1>; |
| interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| interrupt-map = < |
| |
| /* IDSEL 0x11 AD17 */ |
| 0x8800 0x0 0x0 0x1 &ipic 20 0x8 |
| 0x8800 0x0 0x0 0x2 &ipic 21 0x8 |
| 0x8800 0x0 0x0 0x3 &ipic 22 0x8 |
| 0x8800 0x0 0x0 0x4 &ipic 23 0x8 |
| |
| /* IDSEL 0x12 AD18 */ |
| 0x9000 0x0 0x0 0x1 &ipic 22 0x8 |
| 0x9000 0x0 0x0 0x2 &ipic 23 0x8 |
| 0x9000 0x0 0x0 0x3 &ipic 20 0x8 |
| 0x9000 0x0 0x0 0x4 &ipic 21 0x8 |
| |
| /* IDSEL 0x13 AD19 */ |
| 0x9800 0x0 0x0 0x1 &ipic 23 0x8 |
| 0x9800 0x0 0x0 0x2 &ipic 20 0x8 |
| 0x9800 0x0 0x0 0x3 &ipic 21 0x8 |
| 0x9800 0x0 0x0 0x4 &ipic 22 0x8 |
| |
| /* IDSEL 0x15 AD21*/ |
| 0xa800 0x0 0x0 0x1 &ipic 20 0x8 |
| 0xa800 0x0 0x0 0x2 &ipic 21 0x8 |
| 0xa800 0x0 0x0 0x3 &ipic 22 0x8 |
| 0xa800 0x0 0x0 0x4 &ipic 23 0x8 |
| |
| /* IDSEL 0x16 AD22*/ |
| 0xb000 0x0 0x0 0x1 &ipic 23 0x8 |
| 0xb000 0x0 0x0 0x2 &ipic 20 0x8 |
| 0xb000 0x0 0x0 0x3 &ipic 21 0x8 |
| 0xb000 0x0 0x0 0x4 &ipic 22 0x8 |
| |
| /* IDSEL 0x17 AD23*/ |
| 0xb800 0x0 0x0 0x1 &ipic 22 0x8 |
| 0xb800 0x0 0x0 0x2 &ipic 23 0x8 |
| 0xb800 0x0 0x0 0x3 &ipic 20 0x8 |
| 0xb800 0x0 0x0 0x4 &ipic 21 0x8 |
| |
| /* IDSEL 0x18 AD24*/ |
| 0xc000 0x0 0x0 0x1 &ipic 21 0x8 |
| 0xc000 0x0 0x0 0x2 &ipic 22 0x8 |
| 0xc000 0x0 0x0 0x3 &ipic 23 0x8 |
| 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; |
| interrupt-parent = <&ipic>; |
| interrupts = <66 0x8>; |
| bus-range = <0 0>; |
| ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 |
| 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 |
| 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; |
| clock-frequency = <66666666>; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <0xe0008500 0x100>; |
| compatible = "fsl,mpc8349-pci"; |
| device_type = "pci"; |
| }; |
| }; |
