| commit | b12d44db4b0187f536c487713ef39a22da990635 | [log] [tgz] |
|---|---|---|
| author | Ritesh Harjani <riteshh@codeaurora.org> | Mon Nov 21 12:07:21 2016 +0530 |
| committer | Ulf Hansson <ulf.hansson@linaro.org> | Tue Nov 29 09:05:17 2016 +0100 |
| tree | 8cc3c51f4d367633fe1a3fc80d8630e5f961d73f | |
| parent | edc609fd19e1cd1b6d0125915195a28c107a293b [diff] |
mmc: sdhci-msm: Add clock changes for DDR mode. SDHC MSM controller need 2x clock for MCLK at GCC. Hence make required changes to have 2x clock for DDR timing modes. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>