| /* SPDX-License-Identifier: GPL-2.0 */ |
| |
| /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ |
| /* true: device connected */ |
| #define PORT_CONNECT (1 << 0) |
| /* true: port enabled */ |
| #define PORT_PE (1 << 1) |
| /* bit 2 reserved and zeroed */ |
| /* true: port has an over-current condition */ |
| #define PORT_OC (1 << 3) |
| /* true: port reset signaling asserted */ |
| #define PORT_RESET (1 << 4) |
| /* Port Link State - bits 5:8 |
| * A read gives the current link PM state of the port, |
| * a write with Link State Write Strobe set sets the link state. |
| */ |
| #define PORT_PLS_MASK (0xf << 5) |
| #define XDEV_U0 (0x0 << 5) |
| #define XDEV_U1 (0x1 << 5) |
| #define XDEV_U2 (0x2 << 5) |
| #define XDEV_U3 (0x3 << 5) |
| #define XDEV_DISABLED (0x4 << 5) |
| #define XDEV_RXDETECT (0x5 << 5) |
| #define XDEV_INACTIVE (0x6 << 5) |
| #define XDEV_POLLING (0x7 << 5) |
| #define XDEV_RECOVERY (0x8 << 5) |
| #define XDEV_HOT_RESET (0x9 << 5) |
| #define XDEV_COMP_MODE (0xa << 5) |
| #define XDEV_TEST_MODE (0xb << 5) |
| #define XDEV_RESUME (0xf << 5) |
| |
| /* true: port has power (see HCC_PPC) */ |
| #define PORT_POWER (1 << 9) |
| /* bits 10:13 indicate device speed: |
| * 0 - undefined speed - port hasn't be initialized by a reset yet |
| * 1 - full speed |
| * 2 - low speed |
| * 3 - high speed |
| * 4 - super speed |
| * 5-15 reserved |
| */ |
| #define DEV_SPEED_MASK (0xf << 10) |
| #define XDEV_FS (0x1 << 10) |
| #define XDEV_LS (0x2 << 10) |
| #define XDEV_HS (0x3 << 10) |
| #define XDEV_SS (0x4 << 10) |
| #define XDEV_SSP (0x5 << 10) |
| #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) |
| #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) |
| #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) |
| #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) |
| #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) |
| #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP) |
| #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS) |
| #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f) |
| |
| /* Bits 20:23 in the Slot Context are the speed for the device */ |
| #define SLOT_SPEED_FS (XDEV_FS << 10) |
| #define SLOT_SPEED_LS (XDEV_LS << 10) |
| #define SLOT_SPEED_HS (XDEV_HS << 10) |
| #define SLOT_SPEED_SS (XDEV_SS << 10) |
| #define SLOT_SPEED_SSP (XDEV_SSP << 10) |
| /* Port Indicator Control */ |
| #define PORT_LED_OFF (0 << 14) |
| #define PORT_LED_AMBER (1 << 14) |
| #define PORT_LED_GREEN (2 << 14) |
| #define PORT_LED_MASK (3 << 14) |
| /* Port Link State Write Strobe - set this when changing link state */ |
| #define PORT_LINK_STROBE (1 << 16) |
| /* true: connect status change */ |
| #define PORT_CSC (1 << 17) |
| /* true: port enable change */ |
| #define PORT_PEC (1 << 18) |
| /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port |
| * into an enabled state, and the device into the default state. A "warm" reset |
| * also resets the link, forcing the device through the link training sequence. |
| * SW can also look at the Port Reset register to see when warm reset is done. |
| */ |
| #define PORT_WRC (1 << 19) |
| /* true: over-current change */ |
| #define PORT_OCC (1 << 20) |
| /* true: reset change - 1 to 0 transition of PORT_RESET */ |
| #define PORT_RC (1 << 21) |
| /* port link status change - set on some port link state transitions: |
| * Transition Reason |
| * ------------------------------------------------------------------------------ |
| * - U3 to Resume Wakeup signaling from a device |
| * - Resume to Recovery to U0 USB 3.0 device resume |
| * - Resume to U0 USB 2.0 device resume |
| * - U3 to Recovery to U0 Software resume of USB 3.0 device complete |
| * - U3 to U0 Software resume of USB 2.0 device complete |
| * - U2 to U0 L1 resume of USB 2.1 device complete |
| * - U0 to U0 (???) L1 entry rejection by USB 2.1 device |
| * - U0 to disabled L1 entry error with USB 2.1 device |
| * - Any state to inactive Error on USB 3.0 port |
| */ |
| #define PORT_PLC (1 << 22) |
| /* port configure error change - port failed to configure its link partner */ |
| #define PORT_CEC (1 << 23) |
| #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ |
| PORT_RC | PORT_PLC | PORT_CEC) |
| |
| |
| /* Cold Attach Status - xHC can set this bit to report device attached during |
| * Sx state. Warm port reset should be perfomed to clear this bit and move port |
| * to connected state. |
| */ |
| #define PORT_CAS (1 << 24) |
| /* wake on connect (enable) */ |
| #define PORT_WKCONN_E (1 << 25) |
| /* wake on disconnect (enable) */ |
| #define PORT_WKDISC_E (1 << 26) |
| /* wake on over-current (enable) */ |
| #define PORT_WKOC_E (1 << 27) |
| /* bits 28:29 reserved */ |
| /* true: device is non-removable - for USB 3.0 roothub emulation */ |
| #define PORT_DEV_REMOVE (1 << 30) |
| /* Initiate a warm port reset - complete when PORT_WRC is '1' */ |
| #define PORT_WR (1 << 31) |
| |
| /* We mark duplicate entries with -1 */ |
| #define DUPLICATE_ENTRY ((u8)(-1)) |
| |
| /* Port Power Management Status and Control - port_power_base bitmasks */ |
| /* Inactivity timer value for transitions into U1, in microseconds. |
| * Timeout can be up to 127us. 0xFF means an infinite timeout. |
| */ |
| #define PORT_U1_TIMEOUT(p) ((p) & 0xff) |
| #define PORT_U1_TIMEOUT_MASK 0xff |
| /* Inactivity timer value for transitions into U2 */ |
| #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) |
| #define PORT_U2_TIMEOUT_MASK (0xff << 8) |
| /* Bits 24:31 for port testing */ |
| |
| /* USB2 Protocol PORTSPMSC */ |
| #define PORT_L1S_MASK 7 |
| #define PORT_L1S_SUCCESS 1 |
| #define PORT_RWE (1 << 3) |
| #define PORT_HIRD(p) (((p) & 0xf) << 4) |
| #define PORT_HIRD_MASK (0xf << 4) |
| #define PORT_L1DS_MASK (0xff << 8) |
| #define PORT_L1DS(p) (((p) & 0xff) << 8) |
| #define PORT_HLE (1 << 16) |
| #define PORT_TEST_MODE_SHIFT 28 |
| |
| /* USB3 Protocol PORTLI Port Link Information */ |
| #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) |
| #define PORT_TX_LANES(p) (((p) >> 20) & 0xf) |
| |
| /* USB2 Protocol PORTHLPMC */ |
| #define PORT_HIRDM(p)((p) & 3) |
| #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) |
| #define PORT_BESLD(p)(((p) & 0xf) << 10) |
| |
| /* use 512 microseconds as USB2 LPM L1 default timeout. */ |
| #define XHCI_L1_TIMEOUT 512 |
| |
| /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. |
| * Safe to use with mixed HIRD and BESL systems (host and device) and is used |
| * by other operating systems. |
| * |
| * XHCI 1.0 errata 8/14/12 Table 13 notes: |
| * "Software should choose xHC BESL/BESLD field values that do not violate a |
| * device's resume latency requirements, |
| * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, |
| * or not program values < '4' if BLC = '0' and a BESL device is attached. |
| */ |
| #define XHCI_DEFAULT_BESL 4 |
| |
| /* |
| * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports |
| * to complete link training. usually link trainig completes much faster |
| * so check status 10 times with 36ms sleep in places we need to wait for |
| * polling to complete. |
| */ |
| #define XHCI_PORT_POLLING_LFPS_TIME 36 |
