| /* |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| #include <dt-bindings/input/input.h> |
| |
| / { |
| cpus { |
| cpu@0 { |
| cpu0-supply = <&vcc>; |
| }; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x80000000 0>; |
| }; |
| |
| wl12xx_vmmc: wl12xx_vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "vwl1271"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| gpio = <&gpio1 3 0>; /* gpio_3 */ |
| startup-delay-us = <70000>; |
| enable-active-high; |
| vin-supply = <&vmmc2>; |
| }; |
| |
| /* HS USB Host PHY on PORT 1 */ |
| hsusb2_phy: hsusb2_phy { |
| compatible = "usb-nop-xceiv"; |
| reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ |
| #phy-cells = <0>; |
| }; |
| }; |
| |
| &gpmc { |
| ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ |
| |
| nand@0,0 { |
| compatible = "ti,omap2-nand"; |
| reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ |
| interrupt-parent = <&gpmc>; |
| interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ |
| <1 IRQ_TYPE_NONE>; /* termcount */ |
| linux,mtd-name = "micron,mt29f4g16abbda3w"; |
| nand-bus-width = <16>; |
| ti,nand-ecc-opt = "bch8"; |
| rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ |
| gpmc,sync-clk-ps = <0>; |
| gpmc,cs-on-ns = <0>; |
| gpmc,cs-rd-off-ns = <44>; |
| gpmc,cs-wr-off-ns = <44>; |
| gpmc,adv-on-ns = <6>; |
| gpmc,adv-rd-off-ns = <34>; |
| gpmc,adv-wr-off-ns = <44>; |
| gpmc,we-off-ns = <40>; |
| gpmc,oe-off-ns = <54>; |
| gpmc,access-ns = <64>; |
| gpmc,rd-cycle-ns = <82>; |
| gpmc,wr-cycle-ns = <82>; |
| gpmc,wr-access-ns = <40>; |
| gpmc,wr-data-mux-bus-ns = <0>; |
| gpmc,device-width = <2>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| }; |
| |
| &i2c1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c1_pins>; |
| clock-frequency = <2600000>; |
| |
| twl: twl@48 { |
| reg = <0x48>; |
| interrupts = <7>; /* SYS_NIRQ cascaded to intc */ |
| interrupt-parent = <&intc>; |
| twl_audio: audio { |
| compatible = "ti,twl4030-audio"; |
| codec { |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c2_pins>; |
| clock-frequency = <400000>; |
| }; |
| |
| &i2c3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c3_pins>; |
| clock-frequency = <400000>; |
| }; |
| |
| &mmc3 { |
| interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>; |
| pinctrl-0 = <&mmc3_pins &wl127x_gpio>; |
| pinctrl-names = "default"; |
| vmmc-supply = <&wl12xx_vmmc>; |
| non-removable; |
| bus-width = <4>; |
| cap-power-off-card; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| wlcore: wlcore@2 { |
| compatible = "ti,wl1273"; |
| reg = <2>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 2 */ |
| ref-clock-frequency = <26000000>; |
| }; |
| }; |
| |
| &usbhshost { |
| port2-mode = "ehci-phy"; |
| }; |
| |
| &usbhsehci { |
| phys = <0 &hsusb2_phy>; |
| }; |
| |
| |
| &omap3_pmx_core { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&hsusb2_pins>; |
| |
| mmc3_pins: pinmux_mm3_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ |
| OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ |
| OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ |
| OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ |
| OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ |
| OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ |
| >; |
| }; |
| mcbsp2_pins: pinmux_mcbsp2_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ |
| OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ |
| OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ |
| OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ |
| >; |
| }; |
| uart2_pins: pinmux_uart2_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ |
| OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ |
| OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ |
| OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ |
| OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ |
| >; |
| }; |
| mcspi1_pins: pinmux_mcspi1_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ |
| OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ |
| OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ |
| OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ |
| >; |
| }; |
| |
| hsusb2_pins: pinmux_hsusb2_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ |
| OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ |
| OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ |
| OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ |
| OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ |
| OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ |
| >; |
| }; |
| |
| hsusb_otg_pins: pinmux_hsusb_otg_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ |
| OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ |
| OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ |
| OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ |
| OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ |
| OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ |
| OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ |
| OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ |
| OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ |
| OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ |
| OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ |
| OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ |
| >; |
| }; |
| |
| i2c1_pins: pinmux_i2c1_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ |
| OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ |
| >; |
| }; |
| }; |
| |
| &omap3_pmx_wkup { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&hsusb2_reset_pin>; |
| hsusb2_reset_pin: pinmux_hsusb1_reset_pin { |
| pinctrl-single,pins = < |
| OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ |
| >; |
| }; |
| wl127x_gpio: pinmux_wl127x_gpio_pin { |
| pinctrl-single,pins = < |
| OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ |
| OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ |
| >; |
| }; |
| i2c2_pins: pinmux_i2c2_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ |
| OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ |
| >; |
| }; |
| i2c3_pins: pinmux_i2c3_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ |
| OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ |
| >; |
| }; |
| }; |
| |
| &omap3_pmx_core2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&hsusb2_2_pins>; |
| hsusb2_2_pins: pinmux_hsusb2_2_pins { |
| pinctrl-single,pins = < |
| OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ |
| OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ |
| OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ |
| OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ |
| OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ |
| OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ |
| >; |
| }; |
| }; |
| |
| &uart2 { |
| interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart2_pins>; |
| }; |
| |
| &mcspi1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcspi1_pins>; |
| }; |
| |
| #include "twl4030.dtsi" |
| #include "twl4030_omap3.dtsi" |
| |
| &twl { |
| twl_power: power { |
| compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; |
| ti,use_poweroff; |
| }; |
| }; |
| |
| &twl_gpio { |
| ti,use-leds; |
| }; |
