Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt

* Cadence NAND controller

Required properties:
  - compatible : "cdns,hp-nfc"
  - reg : Contains two entries, each of which is a tuple consisting of a
	  physical address and length. The first entry is the address and
	  length of the controller register set. The second entry is the
	  address and length of the Slave DMA data port.
  - reg-names: should contain "reg" and "sdma"
  - #address-cells: should be 1. The cell encodes the chip select connection.
  - #size-cells : should be 0.
  - interrupts : The interrupt number.
  - clocks: phandle of the controller core clock (nf_clk).

Optional properties:
  - dmas: shall reference DMA channel associated to the NAND controller
  - cdns,board-delay-ps : Estimated Board delay. The value includes the total
    round trip delay for the signals and is used for deciding on values
    associated with data read capture. The example formula for SDR mode is
    the following:
    board delay = RE#PAD delay + PCB trace to device + PCB trace from device
    + DQ PAD delay

Child nodes represent the available NAND chips.

Required properties of NAND chips:
  - reg: shall contain the native Chip Select ids from 0 to max supported by
    the cadence nand flash controller

See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
generic bindings.

Example:

nand_controller: nand-controller@60000000 {
	  compatible = "cdns,hp-nfc";
	  #address-cells = <1>;
	  #size-cells = <0>;
	  reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
	  reg-names = "reg", "sdma";
	  clocks = <&nf_clk>;
	  cdns,board-delay-ps = <4830>;
	  interrupts = <2 0>;
	  nand@0 {
	      reg = <0>;
	      label = "nand-1";
	  };
	  nand@1 {
	      reg = <1>;
	      label = "nand-2";
	  };

};