| // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| /* |
| * Device Tree Source for the RZ/V2M SoC |
| * |
| * Copyright (C) 2022 Renesas Electronics Corp. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/r9a09g011-cpg.h> |
| |
| / { |
| compatible = "renesas,r9a09g011"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ |
| extal_clk: extal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| }; |
| }; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a53"; |
| reg = <0>; |
| device_type = "cpu"; |
| clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>; |
| }; |
| }; |
| |
| soc: soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gic: interrupt-controller@82000000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x0 0x82010000 0 0x1000>, |
| <0x0 0x82020000 0 0x20000>, |
| <0x0 0x82040000 0 0x20000>, |
| <0x0 0x82060000 0 0x20000>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; |
| clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>; |
| clock-names = "clk"; |
| }; |
| |
| avb: ethernet@a3300000 { |
| compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m"; |
| reg = <0 0xa3300000 0 0x800>; |
| interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */ |
| <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */ |
| <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */ |
| <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */ |
| <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */ |
| <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */ |
| <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */ |
| <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */ |
| <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */ |
| <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */ |
| <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */ |
| interrupt-names = "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15", |
| "ch16", "ch17", "ch18", "ch19", |
| "ch20", "ch21", "dia", "dib", |
| "err_a", "err_b", "mgmt_a", "mgmt_b", |
| "line3"; |
| clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>, |
| <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>, |
| <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>; |
| clock-names = "axi", "chi", "gptp"; |
| resets = <&cpg R9A09G011_ETH0_RST_HW_N>; |
| power-domains = <&cpg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disable"; |
| }; |
| |
| cpg: clock-controller@a3500000 { |
| compatible = "renesas,r9a09g011-cpg"; |
| reg = <0 0xa3500000 0 0x1000>; |
| clocks = <&extal_clk>; |
| clock-names = "extal"; |
| #clock-cells = <2>; |
| #reset-cells = <1>; |
| #power-domain-cells = <0>; |
| }; |
| |
| uart0: serial@a4040000 { |
| compatible = "renesas,r9a09g011-uart", "renesas,em-uart"; |
| reg = <0 0xa4040000 0 0x80>; |
| interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>, |
| <&cpg CPG_MOD R9A09G011_URT_PCLK>; |
| clock-names = "sclk", "pclk"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| }; |