| # SPDX-License-Identifier: GPL-2.0-only |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Marvell MMP/Orion Interrupt controller bindings |
| |
| maintainers: |
| - Thomas Gleixner <tglx@linutronix.de> |
| - Jason Cooper <jason@lakedaemon.net> |
| - Marc Zyngier <maz@kernel.org> |
| - Rob Herring <robh+dt@kernel.org> |
| |
| allOf: |
| - if: |
| properties: |
| compatible: |
| not: |
| contains: |
| const: marvell,orion-intc |
| then: |
| required: |
| - mrvl,intc-nr-irqs |
| - if: |
| properties: |
| compatible: |
| contains: |
| enum: |
| - mrvl,mmp-intc |
| - mrvl,mmp2-intc |
| then: |
| properties: |
| reg: |
| maxItems: 1 |
| - if: |
| properties: |
| compatible: |
| contains: |
| enum: |
| - marvell,mmp3-intc |
| - mrvl,mmp2-mux-intc |
| then: |
| properties: |
| reg: |
| minItems: 2 |
| - if: |
| properties: |
| compatible: |
| contains: |
| const: mrvl,mmp2-mux-intc |
| then: |
| properties: |
| interrupts: |
| maxItems: 1 |
| reg-names: |
| items: |
| - const: 'mux status' |
| - const: 'mux mask' |
| required: |
| - interrupts |
| else: |
| properties: |
| interrupts: false |
| |
| properties: |
| '#interrupt-cells': |
| const: 1 |
| |
| compatible: |
| enum: |
| - mrvl,mmp-intc |
| - mrvl,mmp2-intc |
| - marvell,mmp3-intc |
| - marvell,orion-intc |
| - mrvl,mmp2-mux-intc |
| |
| reg: |
| minItems: 1 |
| maxItems: 2 |
| |
| reg-names: true |
| |
| interrupts: true |
| |
| interrupt-controller: true |
| |
| mrvl,intc-nr-irqs: |
| description: | |
| Specifies the number of interrupts in the interrupt controller. |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| |
| mrvl,clr-mfp-irq: |
| description: | |
| Specifies the interrupt that needs to clear MFP edge detection first. |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| |
| required: |
| - '#interrupt-cells' |
| - compatible |
| - reg |
| - interrupt-controller |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| interrupt-controller@d4282000 { |
| compatible = "mrvl,mmp2-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| reg = <0xd4282000 0x1000>; |
| mrvl,intc-nr-irqs = <64>; |
| }; |
| |
| interrupt-controller@d4282150 { |
| compatible = "mrvl,mmp2-mux-intc"; |
| interrupts = <4>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| reg = <0x150 0x4>, <0x168 0x4>; |
| reg-names = "mux status", "mux mask"; |
| mrvl,intc-nr-irqs = <2>; |
| }; |
| - | |
| interrupt-controller@fed20204 { |
| compatible = "marvell,orion-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| reg = <0xfed20204 0x04>, |
| <0xfed20214 0x04>; |
| }; |
| |
| ... |
