Documentation/devicetree/bindings/net/dsa/mt7530.txt - linux - Git at Google

 Mediatek MT7530 Ethernet switch
 ================================

 Required properties:

 - compatible: may be compatible = "mediatek,mt7530"
 	or compatible = "mediatek,mt7621"
 	or compatible = "mediatek,mt7531"
 - #address-cells: Must be 1.
 - #size-cells: Must be 0.
 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
 	on multi-chip module belong to MT7623A has or the remotely standalone
 	chip as the function MT7623N reference board provided for.

 If compatible mediatek,mt7530 is set then the following properties are required

 - core-supply: Phandle to the regulator node necessary for the core power.
 - io-supply: Phandle to the regulator node necessary for the I/O power.
 	See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
 	for details for the regulator setup on these boards.

 If the property mediatek,mcm isn't defined, following property is required

 - reset-gpios: Should be a gpio specifier for a reset line.

 Else, following properties are required

 - resets : Phandle pointing to the system reset controller with
 	line index for the ethsys.
 - reset-names : Should be set to "mcm".

 Required properties for the child nodes within ports container:

 - reg: Port address described must be 6 for CPU port and from 0 to 5 for
 	user ports.
 - phy-mode: String, the following values are acceptable for port labeled
 	"cpu":
 	If compatible mediatek,mt7530 or mediatek,mt7621 is set,
 	must be either "trgmii" or "rgmii"
 	If compatible mediatek,mt7531 is set,
 	must be either "sgmii", "1000base-x" or "2500base-x"

 Port 5 of mt7530 and mt7621 switch is muxed between:
 1. GMAC5: GMAC5 can interface with another external MAC or PHY.
 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
    of the SOC. Used in many setups where port 0/4 becomes the WAN port.
    Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
 	 GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
 	 connected to external component!

 Port 5 modes/configurations:
 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
    GMAC of the SOC.
    In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
    GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
    It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
    and RGMII delay.
 3. Port 5 is muxed to GMAC5 and can interface to an external phy.
    Port 5 becomes an extra switch port.
    Only works on platform where external phy TX<->RX lines are swapped.
    Like in the Ubiquiti ER-X-SFP.
 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
    Currently a 2nd CPU port is not supported by DSA code.

 Depending on how the external PHY is wired:
 1. normal: The PHY can only connect to 2nd GMAC but not to the switch
 2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
    a ethernet port. But can't interface to the 2nd GMAC.

 Based on the DT the port 5 mode is configured.

 Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
 When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
 phy-mode must be set, see also example 2 below!
  * mt7621: phy-mode = "rgmii-txid";
  * mt7623: phy-mode = "rgmii";

 Optional properties:

 - gpio-controller: Boolean; if defined, MT7530's LED controller will run on
 	GPIO mode.
 - #gpio-cells: Must be 2 if gpio-controller is defined.
 - interrupt-controller: Boolean; Enables the internal interrupt controller.

 If interrupt-controller is defined, the following properties are required.

 - #interrupt-cells: Must be 1.
 - interrupts: Parent interrupt for the interrupt controller.

 See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
 required, optional properties and how the integrated switch subnodes must
 be specified.

 Example:

 	&mdio0 {
 		switch@0 {
 			compatible = "mediatek,mt7530";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0>;

 			core-supply = <&mt6323_vpa_reg>;
 			io-supply = <&mt6323_vemc3v3_reg>;
 			reset-gpios = <&pio 33 0>;

 			ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				reg = <0>;
 				port@0 {
 					reg = <0>;
 					label = "lan0";
 				};

 				port@1 {
 					reg = <1>;
 					label = "lan1";
 				};

 				port@2 {
 					reg = <2>;
 					label = "lan2";
 				};

 				port@3 {
 					reg = <3>;
 					label = "lan3";
 				};

 				port@4 {
 					reg = <4>;
 					label = "wan";
 				};

 				port@6 {
 					reg = <6>;
 					label = "cpu";
 					ethernet = <&gmac0>;
 					phy-mode = "trgmii";
 					fixed-link {
 						speed = <1000>;
 						full-duplex;
 					};
 				};
 			};
 		};
 	};

 Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.

 &eth {
 	gmac0: mac@0 {
 		compatible = "mediatek,eth-mac";
 		reg = <0>;
 		phy-mode = "rgmii";

 		fixed-link {
 			speed = <1000>;
 			full-duplex;
 			pause;
 		};
 	};

 	gmac1: mac@1 {
 		compatible = "mediatek,eth-mac";
 		reg = <1>;
 		phy-mode = "rgmii-txid";
 		phy-handle = <&phy4>;
 	};

 	mdio: mdio-bus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		/* Internal phy */
 		phy4: ethernet-phy@4 {
 			reg = <4>;
 		};

 		mt7530: switch@1f {
 			compatible = "mediatek,mt7621";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x1f>;
 			pinctrl-names = "default";
 			mediatek,mcm;

 			resets = <&rstctrl 2>;
 			reset-names = "mcm";

 			ports {
 				#address-cells = <1>;
 				#size-cells = <0>;

 				port@0 {
 					reg = <0>;
 					label = "lan0";
 				};

 				port@1 {
 					reg = <1>;
 					label = "lan1";
 				};

 				port@2 {
 					reg = <2>;
 					label = "lan2";
 				};

 				port@3 {
 					reg = <3>;
 					label = "lan3";
 				};

 /* Commented out. Port 4 is handled by 2nd GMAC.
 				port@4 {
 					reg = <4>;
 					label = "lan4";
 				};
 */

 				cpu_port0: port@6 {
 					reg = <6>;
 					label = "cpu";
 					ethernet = <&gmac0>;
 					phy-mode = "rgmii";

 					fixed-link {
 						speed = <1000>;
 						full-duplex;
 						pause;
 					};
 				};
 			};
 		};
 	};
 };

 Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.

 &eth {
 	gmac0: mac@0 {
 		compatible = "mediatek,eth-mac";
 		reg = <0>;
 		phy-mode = "rgmii";

 		fixed-link {
 			speed = <1000>;
 			full-duplex;
 			pause;
 		};
 	};

 	mdio: mdio-bus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		/* External phy */
 		ephy5: ethernet-phy@7 {
 			reg = <7>;
 		};

 		mt7530: switch@1f {
 			compatible = "mediatek,mt7621";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x1f>;
 			pinctrl-names = "default";
 			mediatek,mcm;

 			resets = <&rstctrl 2>;
 			reset-names = "mcm";

 			ports {
 				#address-cells = <1>;
 				#size-cells = <0>;

 				port@0 {
 					reg = <0>;
 					label = "lan0";
 				};

 				port@1 {
 					reg = <1>;
 					label = "lan1";
 				};

 				port@2 {
 					reg = <2>;
 					label = "lan2";
 				};

 				port@3 {
 					reg = <3>;
 					label = "lan3";
 				};

 				port@4 {
 					reg = <4>;
 					label = "lan4";
 				};

 				port@5 {
 					reg = <5>;
 					label = "lan5";
 					phy-mode = "rgmii";
 					phy-handle = <&ephy5>;
 				};

 				cpu_port0: port@6 {
 					reg = <6>;
 					label = "cpu";
 					ethernet = <&gmac0>;
 					phy-mode = "rgmii";

 					fixed-link {
 						speed = <1000>;
 						full-duplex;
 						pause;
 					};
 				};
 			};
 		};
 	};
 };
	Mediatek MT7530 Ethernet switch
	================================

	Required properties:

	- compatible: may be compatible = "mediatek,mt7530"
	or compatible = "mediatek,mt7621"
	or compatible = "mediatek,mt7531"
	- #address-cells: Must be 1.
	- #size-cells: Must be 0.
	- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
	on multi-chip module belong to MT7623A has or the remotely standalone
	chip as the function MT7623N reference board provided for.

	If compatible mediatek,mt7530 is set then the following properties are required

	- core-supply: Phandle to the regulator node necessary for the core power.
	- io-supply: Phandle to the regulator node necessary for the I/O power.
	See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
	for details for the regulator setup on these boards.

	If the property mediatek,mcm isn't defined, following property is required

	- reset-gpios: Should be a gpio specifier for a reset line.

	Else, following properties are required

	- resets : Phandle pointing to the system reset controller with
	line index for the ethsys.
	- reset-names : Should be set to "mcm".

	Required properties for the child nodes within ports container:

	- reg: Port address described must be 6 for CPU port and from 0 to 5 for
	user ports.
	- phy-mode: String, the following values are acceptable for port labeled
	"cpu":
	If compatible mediatek,mt7530 or mediatek,mt7621 is set,
	must be either "trgmii" or "rgmii"
	If compatible mediatek,mt7531 is set,
	must be either "sgmii", "1000base-x" or "2500base-x"

	Port 5 of mt7530 and mt7621 switch is muxed between:
	1. GMAC5: GMAC5 can interface with another external MAC or PHY.
	2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
	of the SOC. Used in many setups where port 0/4 becomes the WAN port.
	Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
	GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
	connected to external component!

	Port 5 modes/configurations:
	1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
	GMAC of the SOC.
	In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
	GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
	2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
	It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
	and RGMII delay.
	3. Port 5 is muxed to GMAC5 and can interface to an external phy.
	Port 5 becomes an extra switch port.
	Only works on platform where external phy TX<->RX lines are swapped.
	Like in the Ubiquiti ER-X-SFP.
	4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
	Currently a 2nd CPU port is not supported by DSA code.

	Depending on how the external PHY is wired:
	1. normal: The PHY can only connect to 2nd GMAC but not to the switch
	2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
	a ethernet port. But can't interface to the 2nd GMAC.

	Based on the DT the port 5 mode is configured.

	Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
	When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
	phy-mode must be set, see also example 2 below!
	* mt7621: phy-mode = "rgmii-txid";
	* mt7623: phy-mode = "rgmii";

	Optional properties:

	- gpio-controller: Boolean; if defined, MT7530's LED controller will run on
	GPIO mode.
	- #gpio-cells: Must be 2 if gpio-controller is defined.
	- interrupt-controller: Boolean; Enables the internal interrupt controller.

	If interrupt-controller is defined, the following properties are required.

	- #interrupt-cells: Must be 1.
	- interrupts: Parent interrupt for the interrupt controller.

	See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
	required, optional properties and how the integrated switch subnodes must
	be specified.

	Example:

	&mdio0 {
	switch@0 {
	compatible = "mediatek,mt7530";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	core-supply = <&mt6323_vpa_reg>;
	io-supply = <&mt6323_vemc3v3_reg>;
	reset-gpios = <&pio 33 0>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;
	port@0 {
	reg = <0>;
	label = "lan0";
	};

	port@1 {
	reg = <1>;
	label = "lan1";
	};

	port@2 {
	reg = <2>;
	label = "lan2";
	};

	port@3 {
	reg = <3>;
	label = "lan3";
	};

	port@4 {
	reg = <4>;
	label = "wan";
	};

	port@6 {
	reg = <6>;
	label = "cpu";
	ethernet = <&gmac0>;
	phy-mode = "trgmii";
	fixed-link {
	speed = <1000>;
	full-duplex;
	};
	};
	};
	};
	};

	Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.

	&eth {
	gmac0: mac@0 {
	compatible = "mediatek,eth-mac";
	reg = <0>;
	phy-mode = "rgmii";

	fixed-link {
	speed = <1000>;
	full-duplex;
	pause;
	};
	};

	gmac1: mac@1 {
	compatible = "mediatek,eth-mac";
	reg = <1>;
	phy-mode = "rgmii-txid";
	phy-handle = <&phy4>;
	};

	mdio: mdio-bus {
	#address-cells = <1>;
	#size-cells = <0>;

	/* Internal phy */
	phy4: ethernet-phy@4 {
	reg = <4>;
	};

	mt7530: switch@1f {
	compatible = "mediatek,mt7621";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x1f>;
	pinctrl-names = "default";
	mediatek,mcm;

	resets = <&rstctrl 2>;
	reset-names = "mcm";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	label = "lan0";
	};

	port@1 {
	reg = <1>;
	label = "lan1";
	};

	port@2 {
	reg = <2>;
	label = "lan2";
	};

	port@3 {
	reg = <3>;
	label = "lan3";
	};

	/* Commented out. Port 4 is handled by 2nd GMAC.
	port@4 {
	reg = <4>;
	label = "lan4";
	};
	*/

	cpu_port0: port@6 {
	reg = <6>;
	label = "cpu";
	ethernet = <&gmac0>;
	phy-mode = "rgmii";

	fixed-link {
	speed = <1000>;
	full-duplex;
	pause;
	};
	};
	};
	};
	};
	};

	Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.

	&eth {
	gmac0: mac@0 {
	compatible = "mediatek,eth-mac";
	reg = <0>;
	phy-mode = "rgmii";

	fixed-link {
	speed = <1000>;
	full-duplex;
	pause;
	};
	};

	mdio: mdio-bus {
	#address-cells = <1>;
	#size-cells = <0>;

	/* External phy */
	ephy5: ethernet-phy@7 {
	reg = <7>;
	};

	mt7530: switch@1f {
	compatible = "mediatek,mt7621";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x1f>;
	pinctrl-names = "default";
	mediatek,mcm;

	resets = <&rstctrl 2>;
	reset-names = "mcm";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	label = "lan0";
	};

	port@1 {
	reg = <1>;
	label = "lan1";
	};

	port@2 {
	reg = <2>;
	label = "lan2";
	};

	port@3 {
	reg = <3>;
	label = "lan3";
	};

	port@4 {
	reg = <4>;
	label = "lan4";
	};

	port@5 {
	reg = <5>;
	label = "lan5";
	phy-mode = "rgmii";
	phy-handle = <&ephy5>;
	};

	cpu_port0: port@6 {
	reg = <6>;
	label = "cpu";
	ethernet = <&gmac0>;
	phy-mode = "rgmii";

	fixed-link {
	speed = <1000>;
	full-duplex;
	pause;
	};
	};
	};
	};
	};
	};