arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>

dma_subsys: bus@5a000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;

	dma_ipg_clk: clock-dma-ipg {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <120000000>;
		clock-output-names = "dma_ipg_clk";
	};

	lpuart0: serial@5a060000 {
		reg = <0x5a060000 0x1000>;
		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
			 <&uart0_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "baud";
		power-domains = <&pd IMX_SC_R_UART_0>;
		status = "disabled";
	};

	lpuart1: serial@5a070000 {
		reg = <0x5a070000 0x1000>;
		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
			 <&uart1_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "baud";
		power-domains = <&pd IMX_SC_R_UART_1>;
		status = "disabled";
	};

	lpuart2: serial@5a080000 {
		reg = <0x5a080000 0x1000>;
		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
			 <&uart2_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "baud";
		power-domains = <&pd IMX_SC_R_UART_2>;
		status = "disabled";
	};

	lpuart3: serial@5a090000 {
		reg = <0x5a090000 0x1000>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
			 <&uart3_lpcg IMX_LPCG_CLK_0>;
		clock-names = "ipg", "baud";
		power-domains = <&pd IMX_SC_R_UART_3>;
		status = "disabled";
	};

	uart0_lpcg: clock-controller@5a460000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a460000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "uart0_lpcg_baud_clk",
				     "uart0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_0>;
	};

	uart1_lpcg: clock-controller@5a470000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a470000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "uart1_lpcg_baud_clk",
				     "uart1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_1>;
	};

	uart2_lpcg: clock-controller@5a480000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a480000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "uart2_lpcg_baud_clk",
				     "uart2_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_2>;
	};

	uart3_lpcg: clock-controller@5a490000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a490000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "uart3_lpcg_baud_clk",
				     "uart3_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_3>;
	};

	i2c0: i2c@5a800000 {
		reg = <0x5a800000 0x4000>;
		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>;
		clock-names = "per";
		assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_0>;
		status = "disabled";
	};

	i2c1: i2c@5a810000 {
		reg = <0x5a810000 0x4000>;
		interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>;
		clock-names = "per";
		assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_1>;
		status = "disabled";
	};

	i2c2: i2c@5a820000 {
		reg = <0x5a820000 0x4000>;
		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>;
		clock-names = "per";
		assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_2>;
		status = "disabled";
	};

	i2c3: i2c@5a830000 {
		reg = <0x5a830000 0x4000>;
		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>;
		clock-names = "per";
		assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_3>;
		status = "disabled";
	};

	i2c0_lpcg: clock-controller@5ac00000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac00000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "i2c0_lpcg_clk",
				     "i2c0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_0>;
	};

	i2c1_lpcg: clock-controller@5ac10000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac10000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "i2c1_lpcg_clk",
				     "i2c1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_1>;
	};

	i2c2_lpcg: clock-controller@5ac20000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac20000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "i2c2_lpcg_clk",
				     "i2c2_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_2>;
	};

	i2c3_lpcg: clock-controller@5ac30000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac30000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "i2c3_lpcg_clk",
				     "i2c3_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_3>;
	};
};