| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2020 Gateworks Corporation |
| */ |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/input/linux-event-codes.h> |
| #include <dt-bindings/net/ti-dp83867.h> |
| |
| / { |
| memory@40000000 { |
| device_type = "memory"; |
| reg = <0x0 0x40000000 0 0x80000000>; |
| }; |
| |
| gpio-keys { |
| compatible = "gpio-keys"; |
| |
| user-pb { |
| label = "user_pb"; |
| gpios = <&gpio 2 GPIO_ACTIVE_LOW>; |
| linux,code = <BTN_0>; |
| }; |
| |
| user-pb1x { |
| label = "user_pb1x"; |
| linux,code = <BTN_1>; |
| interrupt-parent = <&gsc>; |
| interrupts = <0>; |
| }; |
| |
| key-erased { |
| label = "key_erased"; |
| linux,code = <BTN_2>; |
| interrupt-parent = <&gsc>; |
| interrupts = <1>; |
| }; |
| |
| eeprom-wp { |
| label = "eeprom_wp"; |
| linux,code = <BTN_3>; |
| interrupt-parent = <&gsc>; |
| interrupts = <2>; |
| }; |
| |
| tamper { |
| label = "tamper"; |
| linux,code = <BTN_4>; |
| interrupt-parent = <&gsc>; |
| interrupts = <5>; |
| }; |
| |
| switch-hold { |
| label = "switch_hold"; |
| linux,code = <BTN_5>; |
| interrupt-parent = <&gsc>; |
| interrupts = <7>; |
| }; |
| }; |
| }; |
| |
| &A53_0 { |
| cpu-supply = <&buck3_reg>; |
| }; |
| |
| &A53_1 { |
| cpu-supply = <&buck3_reg>; |
| }; |
| |
| &A53_2 { |
| cpu-supply = <&buck3_reg>; |
| }; |
| |
| &A53_3 { |
| cpu-supply = <&buck3_reg>; |
| }; |
| |
| &ddrc { |
| operating-points-v2 = <&ddrc_opp_table>; |
| |
| ddrc_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-25M { |
| opp-hz = /bits/ 64 <25000000>; |
| }; |
| |
| opp-100M { |
| opp-hz = /bits/ 64 <100000000>; |
| }; |
| |
| opp-750M { |
| opp-hz = /bits/ 64 <750000000>; |
| }; |
| }; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy0>; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| }; |
| }; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| |
| gsc: gsc@20 { |
| compatible = "gw,gsc"; |
| reg = <0x20>; |
| pinctrl-0 = <&pinctrl_gsc>; |
| interrupt-parent = <&gpio2>; |
| interrupts = <6 IRQ_TYPE_EDGE_FALLING>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| adc { |
| compatible = "gw,gsc-adc"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| channel@6 { |
| gw,mode = <0>; |
| reg = <0x06>; |
| label = "temp"; |
| }; |
| |
| channel@8 { |
| gw,mode = <1>; |
| reg = <0x08>; |
| label = "vdd_bat"; |
| }; |
| |
| channel@16 { |
| gw,mode = <4>; |
| reg = <0x16>; |
| label = "fan_tach"; |
| }; |
| |
| channel@82 { |
| gw,mode = <2>; |
| reg = <0x82>; |
| label = "vdd_vin"; |
| gw,voltage-divider-ohms = <22100 1000>; |
| }; |
| |
| channel@84 { |
| gw,mode = <2>; |
| reg = <0x84>; |
| label = "vdd_adc1"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| |
| channel@86 { |
| gw,mode = <2>; |
| reg = <0x86>; |
| label = "vdd_adc2"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| |
| channel@88 { |
| gw,mode = <2>; |
| reg = <0x88>; |
| label = "vdd_dram"; |
| }; |
| |
| channel@8c { |
| gw,mode = <2>; |
| reg = <0x8c>; |
| label = "vdd_1p2"; |
| }; |
| |
| channel@8e { |
| gw,mode = <2>; |
| reg = <0x8e>; |
| label = "vdd_1p0"; |
| }; |
| |
| channel@90 { |
| gw,mode = <2>; |
| reg = <0x90>; |
| label = "vdd_2p5"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| |
| channel@92 { |
| gw,mode = <2>; |
| reg = <0x92>; |
| label = "vdd_3p3"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| |
| channel@98 { |
| gw,mode = <2>; |
| reg = <0x98>; |
| label = "vdd_0p95"; |
| }; |
| |
| channel@9a { |
| gw,mode = <2>; |
| reg = <0x9a>; |
| label = "vdd_1p8"; |
| }; |
| |
| channel@a2 { |
| gw,mode = <2>; |
| reg = <0xa2>; |
| label = "vdd_gsc"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| }; |
| |
| fan-controller@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "gw,gsc-fan"; |
| reg = <0x0a>; |
| }; |
| }; |
| |
| gpio: gpio@23 { |
| compatible = "nxp,pca9555"; |
| reg = <0x23>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&gsc>; |
| interrupts = <4>; |
| }; |
| |
| eeprom@50 { |
| compatible = "atmel,24c02"; |
| reg = <0x50>; |
| pagesize = <16>; |
| }; |
| |
| eeprom@51 { |
| compatible = "atmel,24c02"; |
| reg = <0x51>; |
| pagesize = <16>; |
| }; |
| |
| eeprom@52 { |
| compatible = "atmel,24c02"; |
| reg = <0x52>; |
| pagesize = <16>; |
| }; |
| |
| eeprom@53 { |
| compatible = "atmel,24c02"; |
| reg = <0x53>; |
| pagesize = <16>; |
| }; |
| |
| rtc@68 { |
| compatible = "dallas,ds1672"; |
| reg = <0x68>; |
| }; |
| |
| pmic@69 { |
| compatible = "mps,mp5416"; |
| reg = <0x69>; |
| |
| regulators { |
| /* vdd_0p95: DRAM/GPU/VPU */ |
| buck1 { |
| regulator-name = "buck1"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1000000>; |
| regulator-min-microamp = <3800000>; |
| regulator-max-microamp = <6800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_soc */ |
| buck2 { |
| regulator-name = "buck2"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <900000>; |
| regulator-min-microamp = <2200000>; |
| regulator-max-microamp = <5200000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_arm */ |
| buck3_reg: buck3 { |
| regulator-name = "buck3"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1000000>; |
| regulator-min-microamp = <3800000>; |
| regulator-max-microamp = <6800000>; |
| regulator-always-on; |
| }; |
| |
| /* vdd_1p8 */ |
| buck4 { |
| regulator-name = "buck4"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-min-microamp = <2200000>; |
| regulator-max-microamp = <5200000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* nvcc_snvs_1p8 */ |
| ldo1 { |
| regulator-name = "ldo1"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_snvs_0p8 */ |
| ldo2 { |
| regulator-name = "ldo2"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_0p9 */ |
| ldo3 { |
| regulator-name = "ldo3"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <900000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_1p8 */ |
| ldo4 { |
| regulator-name = "ldo4"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| status = "okay"; |
| |
| eeprom@52 { |
| compatible = "atmel,24c32"; |
| reg = <0x52>; |
| pagesize = <32>; |
| }; |
| }; |
| |
| /* console */ |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| status = "okay"; |
| }; |
| |
| /* eMMC */ |
| &usdhc3 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 |
| MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 |
| MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f |
| MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f |
| MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f |
| MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f |
| MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 |
| MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 |
| MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 |
| MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 |
| MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f |
| MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 |
| MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 |
| MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f |
| MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 |
| >; |
| }; |
| |
| pinctrl_gsc: gscgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_uart2: uart2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 |
| MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 |
| >; |
| }; |
| |
| pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 |
| >; |
| }; |
| |
| pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 |
| >; |
| }; |
| }; |
